1 /*
2 * Copyright (c) 2015-2019, ARM Limited and Contributors. All rights reserved.
3 * Copyright (c) 2020, NVIDIA Corporation. All rights reserved.
4 *
5 * SPDX-License-Identifier: BSD-3-Clause
6 */
7
8 #include <arch_helpers.h>
9 #include <assert.h>
10 #include <cortex_a57.h>
11 #include <common/bl_common.h>
12 #include <common/debug.h>
13 #include <common/interrupt_props.h>
14 #include <drivers/console.h>
15 #include <lib/xlat_tables/xlat_tables_v2.h>
16 #include <drivers/arm/gic_common.h>
17 #include <drivers/arm/gicv2.h>
18 #include <bl31/interrupt_mgmt.h>
19
20 #include <bpmp.h>
21 #include <flowctrl.h>
22 #include <memctrl.h>
23 #include <plat/common/platform.h>
24 #include <security_engine.h>
25 #include <tegra_def.h>
26 #include <tegra_platform.h>
27 #include <tegra_private.h>
28
29 /* sets of MMIO ranges setup */
30 #define MMIO_RANGE_0_ADDR 0x50000000
31 #define MMIO_RANGE_1_ADDR 0x60000000
32 #define MMIO_RANGE_2_ADDR 0x70000000
33 #define MMIO_RANGE_SIZE 0x200000
34
35 /*
36 * Table of regions to map using the MMU.
37 */
38 static const mmap_region_t tegra_mmap[] = {
39 MAP_REGION_FLAT(TEGRA_IRAM_BASE, 0x40000, /* 256KB */
40 MT_DEVICE | MT_RW | MT_SECURE),
41 MAP_REGION_FLAT(MMIO_RANGE_0_ADDR, MMIO_RANGE_SIZE,
42 MT_DEVICE | MT_RW | MT_SECURE),
43 MAP_REGION_FLAT(MMIO_RANGE_1_ADDR, MMIO_RANGE_SIZE,
44 MT_DEVICE | MT_RW | MT_SECURE),
45 MAP_REGION_FLAT(MMIO_RANGE_2_ADDR, MMIO_RANGE_SIZE,
46 MT_DEVICE | MT_RW | MT_SECURE),
47 {0}
48 };
49
50 /*******************************************************************************
51 * Set up the pagetables as per the platform memory map & initialize the MMU
52 ******************************************************************************/
plat_get_mmio_map(void)53 const mmap_region_t *plat_get_mmio_map(void)
54 {
55 /* Add the map region for security engine SE2 */
56 if (tegra_chipid_is_t210_b01()) {
57 mmap_add_region((uint64_t)TEGRA_SE2_BASE,
58 (uint64_t)TEGRA_SE2_BASE,
59 (uint64_t)TEGRA_SE2_RANGE_SIZE,
60 MT_DEVICE | MT_RW | MT_SECURE);
61 }
62
63 /* MMIO space */
64 return tegra_mmap;
65 }
66
67 /*******************************************************************************
68 * The Tegra power domain tree has a single system level power domain i.e. a
69 * single root node. The first entry in the power domain descriptor specifies
70 * the number of power domains at the highest power level.
71 *******************************************************************************
72 */
73 const unsigned char tegra_power_domain_tree_desc[] = {
74 /* No of root nodes */
75 1,
76 /* No of clusters */
77 PLATFORM_CLUSTER_COUNT,
78 /* No of CPU cores - cluster0 */
79 PLATFORM_MAX_CPUS_PER_CLUSTER,
80 /* No of CPU cores - cluster1 */
81 PLATFORM_MAX_CPUS_PER_CLUSTER
82 };
83
84 /*******************************************************************************
85 * This function returns the Tegra default topology tree information.
86 ******************************************************************************/
plat_get_power_domain_tree_desc(void)87 const unsigned char *plat_get_power_domain_tree_desc(void)
88 {
89 return tegra_power_domain_tree_desc;
90 }
91
92 /*******************************************************************************
93 * Handler to get the System Counter Frequency
94 ******************************************************************************/
plat_get_syscnt_freq2(void)95 unsigned int plat_get_syscnt_freq2(void)
96 {
97 return 19200000;
98 }
99
100 /*******************************************************************************
101 * Maximum supported UART controllers
102 ******************************************************************************/
103 #define TEGRA210_MAX_UART_PORTS 5
104
105 /*******************************************************************************
106 * This variable holds the UART port base addresses
107 ******************************************************************************/
108 static uint32_t tegra210_uart_addresses[TEGRA210_MAX_UART_PORTS + 1] = {
109 0, /* undefined - treated as an error case */
110 TEGRA_UARTA_BASE,
111 TEGRA_UARTB_BASE,
112 TEGRA_UARTC_BASE,
113 TEGRA_UARTD_BASE,
114 TEGRA_UARTE_BASE,
115 };
116
117 /*******************************************************************************
118 * Enable console corresponding to the console ID
119 ******************************************************************************/
plat_enable_console(int32_t id)120 void plat_enable_console(int32_t id)
121 {
122 static console_t uart_console;
123 uint32_t console_clock;
124
125 if ((id > 0) && (id < TEGRA210_MAX_UART_PORTS)) {
126 /*
127 * Reference clock used by the FPGAs is a lot slower.
128 */
129 if (tegra_platform_is_fpga()) {
130 console_clock = TEGRA_BOOT_UART_CLK_13_MHZ;
131 } else {
132 console_clock = TEGRA_BOOT_UART_CLK_408_MHZ;
133 }
134
135 (void)console_16550_register(tegra210_uart_addresses[id],
136 console_clock,
137 TEGRA_CONSOLE_BAUDRATE,
138 &uart_console);
139 console_set_scope(&uart_console, CONSOLE_FLAG_BOOT |
140 CONSOLE_FLAG_RUNTIME | CONSOLE_FLAG_CRASH);
141 }
142 }
143
144 /*******************************************************************************
145 * Return pointer to the BL31 params from previous bootloader
146 ******************************************************************************/
plat_get_bl31_params(void)147 struct tegra_bl31_params *plat_get_bl31_params(void)
148 {
149 return NULL;
150 }
151
152 /*******************************************************************************
153 * Return pointer to the BL31 platform params from previous bootloader
154 ******************************************************************************/
plat_get_bl31_plat_params(void)155 plat_params_from_bl2_t *plat_get_bl31_plat_params(void)
156 {
157 return NULL;
158 }
159
160 /*******************************************************************************
161 * Handler for early platform setup
162 ******************************************************************************/
plat_early_platform_setup(void)163 void plat_early_platform_setup(void)
164 {
165 const plat_params_from_bl2_t *plat_params = bl31_get_plat_params();
166 uint64_t val;
167
168 /* Verify chip id is t210 */
169 assert(tegra_chipid_is_t210());
170
171 /*
172 * Do initial security configuration to allow DRAM/device access.
173 */
174 tegra_memctrl_tzdram_setup(plat_params->tzdram_base,
175 (uint32_t)plat_params->tzdram_size);
176
177 /* platform parameter passed by the previous bootloader */
178 if (plat_params->l2_ecc_parity_prot_dis != 1) {
179 /* Enable ECC Parity Protection for Cortex-A57 CPUs */
180 val = read_l2ctlr_el1();
181 val |= (uint64_t)CORTEX_A57_L2_ECC_PARITY_PROTECTION_BIT;
182 write_l2ctlr_el1(val);
183 }
184
185 /* Initialize security engine driver */
186 tegra_se_init();
187 }
188
189 /* Secure IRQs for Tegra186 */
190 static const interrupt_prop_t tegra210_interrupt_props[] = {
191 INTR_PROP_DESC(TEGRA_SDEI_SGI_PRIVATE, PLAT_SDEI_CRITICAL_PRI,
192 GICV2_INTR_GROUP0, GIC_INTR_CFG_EDGE),
193 INTR_PROP_DESC(TEGRA210_TIMER1_IRQ, PLAT_TEGRA_WDT_PRIO,
194 GICV2_INTR_GROUP0, GIC_INTR_CFG_EDGE),
195 INTR_PROP_DESC(TEGRA210_WDT_CPU_LEGACY_FIQ, PLAT_TEGRA_WDT_PRIO,
196 GICV2_INTR_GROUP0, GIC_INTR_CFG_EDGE),
197 };
198
199 /*******************************************************************************
200 * Handler for late platform setup
201 ******************************************************************************/
plat_late_platform_setup(void)202 void plat_late_platform_setup(void)
203 {
204 const plat_params_from_bl2_t *plat_params = bl31_get_plat_params();
205 uint64_t sc7entry_end, offset;
206 int ret;
207 uint32_t val;
208
209 /* memmap TZDRAM area containing the SC7 Entry Firmware */
210 if (plat_params->sc7entry_fw_base && plat_params->sc7entry_fw_size) {
211
212 assert(plat_params->sc7entry_fw_size <= TEGRA_IRAM_A_SIZE);
213
214 /*
215 * Verify that the SC7 entry firmware resides inside the TZDRAM
216 * aperture, _before_ the BL31 code and the start address is
217 * exactly 1MB from BL31 base.
218 */
219
220 /* sc7entry-fw must be _before_ BL31 base */
221 assert(plat_params->tzdram_base > plat_params->sc7entry_fw_base);
222
223 sc7entry_end = plat_params->sc7entry_fw_base +
224 plat_params->sc7entry_fw_size;
225 assert(sc7entry_end < plat_params->tzdram_base);
226
227 /* sc7entry-fw start must be exactly 1MB behind BL31 base */
228 offset = plat_params->tzdram_base - plat_params->sc7entry_fw_base;
229 assert(offset == 0x100000);
230
231 /* secure TZDRAM area */
232 tegra_memctrl_tzdram_setup(plat_params->sc7entry_fw_base,
233 plat_params->tzdram_size + offset);
234
235 /* power off BPMP processor until SC7 entry */
236 tegra_fc_bpmp_off();
237
238 /* memmap SC7 entry firmware code */
239 ret = mmap_add_dynamic_region(plat_params->sc7entry_fw_base,
240 plat_params->sc7entry_fw_base,
241 plat_params->sc7entry_fw_size,
242 MT_SECURE | MT_RO_DATA);
243 assert(ret == 0);
244
245 /* restrict PMC access to secure world */
246 val = mmio_read_32(TEGRA_MISC_BASE + APB_SLAVE_SECURITY_ENABLE);
247 val |= PMC_SECURITY_EN_BIT;
248 mmio_write_32(TEGRA_MISC_BASE + APB_SLAVE_SECURITY_ENABLE, val);
249 }
250
251 if (!tegra_chipid_is_t210_b01()) {
252 /* restrict PMC access to secure world */
253 val = mmio_read_32(TEGRA_MISC_BASE + APB_SLAVE_SECURITY_ENABLE);
254 val |= PMC_SECURITY_EN_BIT;
255 mmio_write_32(TEGRA_MISC_BASE + APB_SLAVE_SECURITY_ENABLE, val);
256 }
257 }
258
259 /*******************************************************************************
260 * Initialize the GIC and SGIs
261 ******************************************************************************/
plat_gic_setup(void)262 void plat_gic_setup(void)
263 {
264 tegra_gic_setup(tegra210_interrupt_props, ARRAY_SIZE(tegra210_interrupt_props));
265 tegra_gic_init();
266
267 /* Enable handling for FIQs */
268 tegra_fiq_handler_setup();
269
270 /*
271 * Enable routing watchdog FIQs from the flow controller to
272 * the GICD.
273 */
274 tegra_fc_enable_fiq_to_ccplex_routing();
275 }
276 /*******************************************************************************
277 * Handler to indicate support for System Suspend
278 ******************************************************************************/
plat_supports_system_suspend(void)279 bool plat_supports_system_suspend(void)
280 {
281 const plat_params_from_bl2_t *plat_params = bl31_get_plat_params();
282
283 /*
284 * sc7entry-fw is only supported by Tegra210 SoCs.
285 */
286 if (!tegra_chipid_is_t210_b01() && (plat_params->sc7entry_fw_base != 0U)) {
287 return true;
288 } else if (tegra_chipid_is_t210_b01()) {
289 return true;
290 } else {
291 return false;
292 }
293 }
294 /*******************************************************************************
295 * Platform specific runtime setup.
296 ******************************************************************************/
plat_runtime_setup(void)297 void plat_runtime_setup(void)
298 {
299 /*
300 * During cold boot, it is observed that the arbitration
301 * bit is set in the Memory controller leading to false
302 * error interrupts in the non-secure world. To avoid
303 * this, clean the interrupt status register before
304 * booting into the non-secure world
305 */
306 tegra_memctrl_clear_pending_interrupts();
307
308 /*
309 * During boot, USB3 and flash media (SDMMC/SATA) devices need
310 * access to IRAM. Because these clients connect to the MC and
311 * do not have a direct path to the IRAM, the MC implements AHB
312 * redirection during boot to allow path to IRAM. In this mode
313 * accesses to a programmed memory address aperture are directed
314 * to the AHB bus, allowing access to the IRAM. This mode must be
315 * disabled before we jump to the non-secure world.
316 */
317 tegra_memctrl_disable_ahb_redirection();
318 }
319