1/*
2 * Copyright 2021 NXP
3 *
4 * SPDX-License-Identifier: BSD-3-Clause
5 */
6
7#include <asm_macros.S>
8
9#include <soc_default_base_addr.h>
10#include <soc_default_helper_macros.h>
11
12.global ocram_init
13
14/*
15 * void ocram_init(uintptr_t start_addr, size_t size)
16 *
17 * This function will do OCRAM ECC.
18 * OCRAM is initialized with 64-bit writes and then a write
19 * performed to address 0x0010_0534 with the value 0x0000_0008.
20 *
21 * x0: start_addr
22 * x1: size in bytes
23 * Called from C
24 */
25
26func ocram_init
27	/* save the aarch32/64 non-volatile registers */
28	stp	x4,  x5,  [sp, #-16]!
29	stp	x6,  x7,  [sp, #-16]!
30	stp	x8,  x9,  [sp, #-16]!
31	stp	x10, x11, [sp, #-16]!
32	stp	x12, x13, [sp, #-16]!
33	stp	x18, x30, [sp, #-16]!
34
35	/* convert bytes to 64-byte chunks */
36	lsr	x1, x1, #6
371:
38	/* for each location, read and write-back */
39	dc	ivac, x0
40	dsb	sy
41	ldp	x4, x5, [x0]
42	ldp	x6, x7, [x0, #16]
43	ldp	x8, x9, [x0, #32]
44	ldp	x10, x11, [x0, #48]
45	stp	x4, x5, [x0]
46	stp	x6, x7, [x0, #16]
47	stp	x8, x9, [x0, #32]
48	stp	x10, x11, [x0, #48]
49	dc	cvac, x0
50
51	sub	x1, x1, #1
52	cbz	x1, 2f
53	add	x0, x0, #64
54	b	1b
552:
56	/* Clear OCRAM ECC status bit in SBEESR2 and MBEESR2 */
57	ldr	w1, =OCRAM_EESR_MASK
58	ldr	x0, =DCFG_SBEESR2_ADDR
59	str	w1, [x0]
60	ldr	x0, =DCFG_MBEESR2_ADDR
61	str	w1, [x0]
62
63	/* restore the aarch32/64 non-volatile registers */
64	ldp	x18, x30, [sp], #16
65	ldp	x12, x13, [sp], #16
66	ldp	x10, x11, [sp], #16
67	ldp	x8,  x9,  [sp], #16
68	ldp	x6,  x7,  [sp], #16
69	ldp	x4,  x5,  [sp], #16
70	ret
71endfunc ocram_init
72