1# Copyright 2020-2021 NXP
2#
3# SPDX-License-Identifier: BSD-3-Clause
4#
5
6# Adding SoC specific defines
7
8ifneq (${CACHE_LINE},)
9$(eval $(call add_define_val,PLATFORM_CACHE_LINE_SHIFT,${CACHE_LINE}))
10$(eval CACHE_WRITEBACK_GRANULE=$(shell echo $$((1 << $(CACHE_LINE)))))
11$(eval $(call add_define_val,CACHE_WRITEBACK_GRANULE,$(CACHE_WRITEBACK_GRANULE)))
12endif
13
14ifeq (${INTERCONNECT}, "CCI400")
15$(eval $(call add_define,NXP_HAS_${INTERCONNECT}))
16ICNNCT_ID := 0x420
17$(eval $(call add_define,ICNNCT_ID))
18endif
19
20ifeq (${INTERCONNECT}, "CCN508")
21$(eval $(call add_define,NXP_HAS_CCN508))
22endif
23
24ifneq (${CHASSIS},)
25$(eval $(call add_define,CONFIG_CHASSIS_${CHASSIS}))
26endif
27
28ifneq (${PLAT_DDR_PHY},)
29$(eval $(call add_define,NXP_DDR_${PLAT_DDR_PHY}))
30endif
31
32ifneq (${PHYS_SYS},)
33$(eval $(call add_define,CONFIG_PHYS_64BIT))
34endif
35
36ifneq (${CSF_HDR_SZ},)
37$(eval $(call add_define_val,CSF_HDR_SZ,${CSF_HDR_SZ}))
38endif
39
40ifneq (${OCRAM_START_ADDR},)
41$(eval $(call add_define_val,NXP_OCRAM_ADDR,${OCRAM_START_ADDR}))
42endif
43
44ifneq (${OCRAM_SIZE},)
45$(eval $(call add_define_val,NXP_OCRAM_SIZE,${OCRAM_SIZE}))
46endif
47
48ifneq (${NXP_ROM_RSVD},)
49$(eval $(call add_define_val,NXP_ROM_RSVD,${NXP_ROM_RSVD}))
50endif
51
52ifneq (${BL2_BASE},)
53$(eval $(call add_define_val,BL2_BASE,${BL2_BASE}))
54endif
55
56ifeq (${SEC_MEM_NON_COHERENT},yes)
57$(eval $(call add_define,SEC_MEM_NON_COHERENT))
58endif
59
60ifneq (${NXP_ESDHC_ENDIANNESS},)
61$(eval $(call add_define,NXP_ESDHC_${NXP_ESDHC_ENDIANNESS}))
62endif
63
64ifneq (${NXP_SFP_VER},)
65$(eval $(call add_define,NXP_SFP_VER_${NXP_SFP_VER}))
66endif
67
68ifneq (${NXP_SFP_ENDIANNESS},)
69$(eval $(call add_define,NXP_SFP_${NXP_SFP_ENDIANNESS}))
70endif
71
72ifneq (${NXP_GPIO_ENDIANNESS},)
73$(eval $(call add_define,NXP_GPIO_${NXP_GPIO_ENDIANNESS}))
74endif
75
76ifneq (${NXP_SNVS_ENDIANNESS},)
77$(eval $(call add_define,NXP_SNVS_${NXP_SNVS_ENDIANNESS}))
78endif
79
80ifneq (${NXP_GUR_ENDIANNESS},)
81$(eval $(call add_define,NXP_GUR_${NXP_GUR_ENDIANNESS}))
82endif
83
84ifneq (${NXP_FSPI_ENDIANNESS},)
85$(eval $(call add_define,NXP_FSPI_${NXP_FSPI_ENDIANNESS}))
86endif
87
88ifneq (${NXP_SEC_ENDIANNESS},)
89$(eval $(call add_define,NXP_SEC_${NXP_SEC_ENDIANNESS}))
90endif
91
92ifneq (${NXP_DDR_ENDIANNESS},)
93$(eval $(call add_define,NXP_DDR_${NXP_DDR_ENDIANNESS}))
94endif
95
96ifneq (${NXP_QSPI_ENDIANNESS},)
97$(eval $(call add_define,NXP_QSPI_${NXP_QSPI_ENDIANNESS}))
98endif
99
100ifneq (${NXP_SCFG_ENDIANNESS},)
101$(eval $(call add_define,NXP_SCFG_${NXP_SCFG_ENDIANNESS}))
102endif
103
104ifneq (${NXP_IFC_ENDIANNESS},)
105$(eval $(call add_define,NXP_IFC_${NXP_IFC_ENDIANNESS}))
106endif
107
108ifneq (${NXP_DDR_INTLV_256B},)
109$(eval $(call add_define,NXP_DDR_INTLV_256B))
110endif
111
112ifneq (${PLAT_XLAT_TABLES_DYNAMIC},)
113$(eval $(call add_define,PLAT_XLAT_TABLES_DYNAMIC))
114endif
115
116ifeq (${OCRAM_ECC_EN},yes)
117$(eval $(call add_define,CONFIG_OCRAM_ECC_EN))
118include ${PLAT_COMMON_PATH}/ocram/ocram.mk
119endif
120