1 /* 2 * Copyright 2018-2021 NXP 3 * 4 * SPDX-License-Identifier: BSD-3-Clause 5 * 6 */ 7 8 #ifndef PLAT_PSCI_H 9 #define PLAT_PSCI_H 10 #include <cortex_a53.h> 11 #include <cortex_a72.h> 12 13 /* core abort current op */ 14 #define CORE_ABORT_OP 0x1 15 16 /* psci power levels - these are actually affinity levels 17 * in the psci_power_state_t array 18 */ 19 #define PLAT_CORE_LVL PSCI_CPU_PWR_LVL 20 #define PLAT_CLSTR_LVL U(1) 21 #define PLAT_SYS_LVL U(2) 22 #define PLAT_MAX_LVL PLAT_SYS_LVL 23 24 /* core state */ 25 /* OFF states 0x0 - 0xF */ 26 #define CORE_IN_RESET 0x0 27 #define CORE_DISABLED 0x1 28 #define CORE_OFF 0x2 29 #define CORE_STANDBY 0x3 30 #define CORE_PWR_DOWN 0x4 31 #define CORE_WFE 0x6 32 #define CORE_WFI 0x7 33 #define CORE_LAST 0x8 34 #define CORE_OFF_PENDING 0x9 35 #define CORE_WORKING_INIT 0xA 36 #define SYS_OFF_PENDING 0xB 37 #define SYS_OFF 0xC 38 39 /* ON states 0x10 - 0x1F */ 40 #define CORE_PENDING 0x10 41 #define CORE_RELEASED 0x11 42 #define CORE_WAKEUP 0x12 43 /* highest off state */ 44 #define CORE_OFF_MAX 0xF 45 /* lowest on state */ 46 #define CORE_ON_MIN CORE_PENDING 47 48 #define DAIF_SET_MASK 0x3C0 49 #define SCTLR_I_C_M_MASK 0x00001005 50 #define SCTLR_C_MASK 0x00000004 51 #define SCTLR_I_MASK 0x00001000 52 #define CPUACTLR_L1PCTL_MASK 0x0000E000 53 #define DCSR_RCPM2_BASE 0x20170000 54 #define CPUECTLR_SMPEN_MASK 0x40 55 #define CPUECTLR_SMPEN_EN 0x40 56 #define CPUECTLR_RET_MASK 0x7 57 #define CPUECTLR_RET_SET 0x2 58 #define CPUECTLR_TIMER_MASK 0x7 59 #define CPUECTLR_TIMER_8TICKS 0x2 60 #define CPUECTLR_TIMER_2TICKS 0x1 61 #define SCR_IRQ_MASK 0x2 62 #define SCR_FIQ_MASK 0x4 63 64 /* pwr mgmt features supported in the soc-specific code: 65 * value == 0x0, the soc code does not support this feature 66 * value != 0x0, the soc code supports this feature 67 */ 68 #ifndef SOC_CORE_RELEASE 69 #define SOC_CORE_RELEASE 0x1 70 #endif 71 72 #ifndef SOC_CORE_RESTART 73 #define SOC_CORE_RESTART 0x1 74 #endif 75 76 #ifndef SOC_CORE_OFF 77 #define SOC_CORE_OFF 0x1 78 #endif 79 80 #ifndef SOC_CORE_STANDBY 81 #define SOC_CORE_STANDBY 0x1 82 #endif 83 84 #ifndef SOC_CORE_PWR_DWN 85 #define SOC_CORE_PWR_DWN 0x1 86 #endif 87 88 #ifndef SOC_CLUSTER_STANDBY 89 #define SOC_CLUSTER_STANDBY 0x1 90 #endif 91 92 #ifndef SOC_CLUSTER_PWR_DWN 93 #define SOC_CLUSTER_PWR_DWN 0x1 94 #endif 95 96 #ifndef SOC_SYSTEM_STANDBY 97 #define SOC_SYSTEM_STANDBY 0x1 98 #endif 99 100 #ifndef SOC_SYSTEM_PWR_DWN 101 #define SOC_SYSTEM_PWR_DWN 0x1 102 #endif 103 104 #ifndef SOC_SYSTEM_OFF 105 #define SOC_SYSTEM_OFF 0x1 106 #endif 107 108 #ifndef SOC_SYSTEM_RESET 109 #define SOC_SYSTEM_RESET 0x1 110 #endif 111 112 #ifndef SOC_SYSTEM_RESET2 113 #define SOC_SYSTEM_RESET2 0x1 114 #endif 115 116 #ifndef __ASSEMBLER__ 117 118 void __dead2 _psci_system_reset(void); 119 void __dead2 _psci_system_off(void); 120 int _psci_cpu_on(u_register_t core_mask); 121 void _psci_cpu_prep_off(u_register_t core_mask); 122 void __dead2 _psci_cpu_off_wfi(u_register_t core_mask, 123 u_register_t wakeup_address); 124 void __dead2 _psci_cpu_pwrdn_wfi(u_register_t core_mask, 125 u_register_t wakeup_address); 126 void __dead2 _psci_sys_pwrdn_wfi(u_register_t core_mask, 127 u_register_t wakeup_address); 128 void _psci_wakeup(u_register_t core_mask); 129 void _psci_core_entr_stdby(u_register_t core_mask); 130 void _psci_core_prep_stdby(u_register_t core_mask); 131 void _psci_core_exit_stdby(u_register_t core_mask); 132 void _psci_core_prep_pwrdn(u_register_t core_mask); 133 void _psci_core_exit_pwrdn(u_register_t core_mask); 134 void _psci_clstr_prep_stdby(u_register_t core_mask); 135 void _psci_clstr_exit_stdby(u_register_t core_mask); 136 void _psci_clstr_prep_pwrdn(u_register_t core_mask); 137 void _psci_clstr_exit_pwrdn(u_register_t core_mask); 138 void _psci_sys_prep_stdby(u_register_t core_mask); 139 void _psci_sys_exit_stdby(u_register_t core_mask); 140 void _psci_sys_prep_pwrdn(u_register_t core_mask); 141 void _psci_sys_exit_pwrdn(u_register_t core_mask); 142 143 #endif 144 145 #endif /* __PLAT_PSCI_H__ */ 146