1 /*
2 * Copyright 2018-2021 NXP
3 *
4 * SPDX-License-Identifier: BSD-3-Clause
5 */
6 #include <string.h>
7
8 #include <common/debug.h>
9 #include <ddr.h>
10 #include <lib/utils.h>
11
12 #include <platform_def.h>
13
14 #ifdef CONFIG_STATIC_DDR
15 const struct ddr_cfg_regs static_1600 = {
16 .cs[0].config = U(0x80040422),
17 .cs[0].bnds = U(0xFF),
18 .sdram_cfg[0] = U(0xE50C0004),
19 .sdram_cfg[1] = U(0x401100),
20 .timing_cfg[0] = U(0x91550018),
21 .timing_cfg[1] = U(0xBAB40C42),
22 .timing_cfg[2] = U(0x48C111),
23 .timing_cfg[3] = U(0x1111000),
24 .timing_cfg[4] = U(0x2),
25 .timing_cfg[5] = U(0x3401400),
26 .timing_cfg[7] = U(0x23300000),
27 .timing_cfg[8] = U(0x2114600),
28 .sdram_mode[0] = U(0x3010210),
29 .sdram_mode[9] = U(0x4000000),
30 .sdram_mode[8] = U(0x500),
31 .sdram_mode[2] = U(0x10210),
32 .sdram_mode[10] = U(0x400),
33 .sdram_mode[11] = U(0x4000000),
34 .sdram_mode[4] = U(0x10210),
35 .sdram_mode[12] = U(0x400),
36 .sdram_mode[13] = U(0x4000000),
37 .sdram_mode[6] = U(0x10210),
38 .sdram_mode[14] = U(0x400),
39 .sdram_mode[15] = U(0x4000000),
40 .interval = U(0x18600618),
41 .data_init = U(0xdeadbeef),
42 .zq_cntl = U(0x8A090705),
43 .clk_cntl = U(0x2000000),
44 .cdr[0] = U(0x80040000),
45 .cdr[1] = U(0xA181),
46 .wrlvl_cntl[0] = U(0x8675F605),
47 .wrlvl_cntl[1] = U(0x6070700),
48 .wrlvl_cntl[2] = U(0x0000008),
49 .dq_map[0] = U(0x5b65b658),
50 .dq_map[1] = U(0xd96d8000),
51 .dq_map[2] = U(0),
52 .dq_map[3] = U(0x1600000),
53 .debug[28] = U(0x00700046),
54 };
55
board_static_ddr(struct ddr_info * priv)56 unsigned long long board_static_ddr(struct ddr_info *priv)
57 {
58 memcpy(&priv->ddr_reg, &static_1600, sizeof(static_1600));
59 return ULL(0x100000000);
60 }
61
62 #else
63
64 static const struct rc_timing rcz[] = {
65 {1600, 8, 5},
66 {}
67 };
68
69 static const struct board_timing ram[] = {
70 {0x1f, rcz, 0x1020200, 0x00000003},
71 };
72
ddr_board_options(struct ddr_info * priv)73 int ddr_board_options(struct ddr_info *priv)
74 {
75 int ret;
76 struct memctl_opt *popts = &priv->opt;
77
78 ret = cal_board_params(priv, ram, ARRAY_SIZE(ram));
79 if (ret != 0) {
80 return ret;
81 }
82
83 popts->bstopre = U(0x40); /* precharge value */
84 popts->half_strength_drive_en = 1;
85 popts->cpo_sample = U(0x46);
86 popts->ddr_cdr1 = DDR_CDR1_DHC_EN |
87 DDR_CDR1_ODT(DDR_CDR_ODT_80ohm);
88 popts->ddr_cdr2 = DDR_CDR2_ODT(DDR_CDR_ODT_80ohm) |
89 DDR_CDR2_VREF_OVRD(70); /* Vref = 70% */
90
91 popts->addr_hash = 1; /* address hashing */
92 return 0;
93 }
94
95 /* DDR model number: MT40A1G8SA-075:E */
96 struct dimm_params ddr_raw_timing = {
97 .n_ranks = U(1),
98 .rank_density = ULL(4294967296),
99 .capacity = ULL(4294967296),
100 .primary_sdram_width = U(32),
101 .ec_sdram_width = U(4),
102 .rdimm = U(0),
103 .mirrored_dimm = U(0),
104 .n_row_addr = U(16),
105 .n_col_addr = U(10),
106 .bank_group_bits = U(2),
107 .edc_config = U(2),
108 .burst_lengths_bitmask = U(0x0c),
109 .tckmin_x_ps = 750,
110 .tckmax_ps = 1900,
111 .caslat_x = U(0x0001FFE00),
112 .taa_ps = 13500,
113 .trcd_ps = 13500,
114 .trp_ps = 13500,
115 .tras_ps = 32000,
116 .trc_ps = 45500,
117 .twr_ps = 15000,
118 .trfc1_ps = 350000,
119 .trfc2_ps = 260000,
120 .trfc4_ps = 160000,
121 .tfaw_ps = 21000,
122 .trrds_ps = 3000,
123 .trrdl_ps = 4900,
124 .tccdl_ps = 5000,
125 .refresh_rate_ps = U(7800000),
126 .dq_mapping[0] = U(0x16),
127 .dq_mapping[1] = U(0x36),
128 .dq_mapping[2] = U(0x16),
129 .dq_mapping[3] = U(0x36),
130 .dq_mapping[4] = U(0x16),
131 .dq_mapping[5] = U(0x36),
132 .dq_mapping[6] = U(0x16),
133 .dq_mapping[7] = U(0x36),
134 .dq_mapping[8] = U(0x16),
135 .dq_mapping[9] = U(0x0),
136 .dq_mapping[10] = U(0x0),
137 .dq_mapping[11] = U(0x0),
138 .dq_mapping[12] = U(0x0),
139 .dq_mapping[13] = U(0x0),
140 .dq_mapping[14] = U(0x0),
141 .dq_mapping[15] = U(0x0),
142 .dq_mapping[16] = U(0x0),
143 .dq_mapping[17] = U(0x0),
144 .dq_mapping_ors = U(0),
145 .rc = U(0x1f),
146 };
147
ddr_get_ddr_params(struct dimm_params * pdimm,struct ddr_conf * conf)148 int ddr_get_ddr_params(struct dimm_params *pdimm,
149 struct ddr_conf *conf)
150 {
151 static const char dimm_model[] = "Fixed DDR on board";
152
153 conf->dimm_in_use[0] = 1;
154 memcpy(pdimm, &ddr_raw_timing, sizeof(struct dimm_params));
155 memcpy(pdimm->mpart, dimm_model, sizeof(dimm_model) - 1);
156
157 return 1;
158 }
159 #endif
160
init_ddr(void)161 int64_t init_ddr(void)
162 {
163 struct ddr_info info;
164 struct sysinfo sys;
165 int64_t dram_size;
166
167 zeromem(&sys, sizeof(sys));
168 get_clocks(&sys);
169 debug("platform clock %lu\n", sys.freq_platform);
170 debug("DDR PLL1 %lu\n", sys.freq_ddr_pll0);
171
172 zeromem(&info, sizeof(struct ddr_info));
173 info.num_ctlrs = 1;
174 info.dimm_on_ctlr = 1;
175 info.clk = get_ddr_freq(&sys, 0);
176 info.ddr[0] = (void *)NXP_DDR_ADDR;
177
178 dram_size = dram_init(&info);
179
180 if (dram_size < 0) {
181 ERROR("DDR init failed.\n");
182 }
183
184 return dram_size;
185 }
186