1 /*
2  * Copyright (c) 2019, Linaro Limited and Contributors. All rights reserved.
3  *
4  * SPDX-License-Identifier: BSD-3-Clause
5  */
6 
7 #include <drivers/arm/gicv3.h>
8 #include <drivers/arm/gic_common.h>
9 #include <platform_def.h>
10 #include <plat/common/platform.h>
11 
12 static const interrupt_prop_t qemu_interrupt_props[] = {
13 	PLATFORM_G1S_PROPS(INTR_GROUP1S),
14 	PLATFORM_G0_PROPS(INTR_GROUP0)
15 };
16 
17 static uintptr_t qemu_rdistif_base_addrs[PLATFORM_CORE_COUNT];
18 
qemu_mpidr_to_core_pos(unsigned long mpidr)19 static unsigned int qemu_mpidr_to_core_pos(unsigned long mpidr)
20 {
21 	return (unsigned int)plat_core_pos_by_mpidr(mpidr);
22 }
23 
24 static const gicv3_driver_data_t qemu_gicv3_driver_data = {
25 	.gicd_base = GICD_BASE,
26 	.gicr_base = GICR_BASE,
27 	.interrupt_props = qemu_interrupt_props,
28 	.interrupt_props_num = ARRAY_SIZE(qemu_interrupt_props),
29 	.rdistif_num = PLATFORM_CORE_COUNT,
30 	.rdistif_base_addrs = qemu_rdistif_base_addrs,
31 	.mpidr_to_core_pos = qemu_mpidr_to_core_pos
32 };
33 
plat_qemu_gic_init(void)34 void plat_qemu_gic_init(void)
35 {
36 	gicv3_driver_init(&qemu_gicv3_driver_data);
37 	gicv3_distif_init();
38 	gicv3_rdistif_init(plat_my_core_pos());
39 	gicv3_cpuif_enable(plat_my_core_pos());
40 }
41 
qemu_pwr_gic_on_finish(void)42 void qemu_pwr_gic_on_finish(void)
43 {
44 	gicv3_rdistif_init(plat_my_core_pos());
45 	gicv3_cpuif_enable(plat_my_core_pos());
46 }
47 
qemu_pwr_gic_off(void)48 void qemu_pwr_gic_off(void)
49 {
50 	gicv3_cpuif_disable(plat_my_core_pos());
51 	gicv3_rdistif_off(plat_my_core_pos());
52 }
53