1 /*
2 * Copyright (c) 2018, ARM Limited and Contributors. All rights reserved.
3 * Copyright (c) 2018-2020, The Linux Foundation. All rights reserved.
4 *
5 * SPDX-License-Identifier: BSD-3-Clause
6 */
7
8 #include <assert.h>
9
10 #include <bl31/bl31.h>
11 #include <common/debug.h>
12 #include <common/desc_image_load.h>
13 #include <drivers/console.h>
14 #include <drivers/generic_delay_timer.h>
15 #include <lib/bl_aux_params/bl_aux_params.h>
16 #include <lib/coreboot.h>
17 #include <lib/spinlock.h>
18
19 #include <platform.h>
20 #include <qti_interrupt_svc.h>
21 #include <qti_plat.h>
22 #include <qti_uart_console.h>
23 #include <qtiseclib_interface.h>
24
25 /*
26 * Placeholder variables for copying the arguments that have been passed to
27 * BL31 from BL2.
28 */
29 static entry_point_info_t bl33_image_ep_info;
30
31 /*
32 * Variable to hold counter frequency for the CPU's generic timer. In this
33 * platform coreboot image configure counter frequency for boot core before
34 * reaching TF-A.
35 */
36 static uint64_t g_qti_cpu_cntfrq;
37
38 /*
39 * Lock variable to serialize cpuss reset execution.
40 */
41 spinlock_t g_qti_cpuss_boot_lock __attribute__ ((section("tzfw_coherent_mem"),
42 aligned(CACHE_WRITEBACK_GRANULE))) = {0x0};
43
44 /*
45 * Variable to hold bl31 cold boot status. Default value 0x0 means yet to boot.
46 * Any other value means cold booted.
47 */
48 uint32_t g_qti_bl31_cold_booted __attribute__ ((section("tzfw_coherent_mem"))) = 0x0;
49
50 /*******************************************************************************
51 * Perform any BL31 early platform setup common to ARM standard platforms.
52 * Here is an opportunity to copy parameters passed by the calling EL (S-EL1
53 * in BL2 & S-EL3 in BL1) before they are lost (potentially). This needs to be
54 * done before the MMU is initialized so that the memory layout can be used
55 * while creating page tables. BL2 has flushed this information to memory, so
56 * we are guaranteed to pick up good data.
57 ******************************************************************************/
bl31_early_platform_setup(u_register_t from_bl2,u_register_t plat_params_from_bl2)58 void bl31_early_platform_setup(u_register_t from_bl2,
59 u_register_t plat_params_from_bl2)
60 {
61
62 g_qti_cpu_cntfrq = read_cntfrq_el0();
63
64 bl_aux_params_parse(plat_params_from_bl2, NULL);
65
66 #if COREBOOT
67 if (coreboot_serial.baseaddr != 0) {
68 static console_t g_qti_console_uart;
69
70 qti_console_uart_register(&g_qti_console_uart,
71 coreboot_serial.baseaddr);
72 }
73 #endif
74
75 /*
76 * Tell BL31 where the non-trusted software image
77 * is located and the entry state information
78 */
79 bl31_params_parse_helper(from_bl2, NULL, &bl33_image_ep_info);
80 }
81
bl31_early_platform_setup2(u_register_t arg0,u_register_t arg1,u_register_t arg2,u_register_t arg3)82 void bl31_early_platform_setup2(u_register_t arg0, u_register_t arg1,
83 u_register_t arg2, u_register_t arg3)
84 {
85 bl31_early_platform_setup(arg0, arg1);
86 }
87
88 /*******************************************************************************
89 * Perform the very early platform specific architectural setup here. At the
90 * moment this only intializes the mmu in a quick and dirty way.
91 ******************************************************************************/
bl31_plat_arch_setup(void)92 void bl31_plat_arch_setup(void)
93 {
94 qti_setup_page_tables(BL_CODE_BASE,
95 BL_COHERENT_RAM_END - BL_CODE_BASE,
96 BL_CODE_BASE,
97 BL_CODE_END,
98 BL_RO_DATA_BASE,
99 BL_RO_DATA_END,
100 BL_COHERENT_RAM_BASE, BL_COHERENT_RAM_END);
101 enable_mmu_el3(0);
102 }
103
104 /*******************************************************************************
105 * Perform any BL31 platform setup common to ARM standard platforms
106 ******************************************************************************/
bl31_platform_setup(void)107 void bl31_platform_setup(void)
108 {
109 generic_delay_timer_init();
110 /* Initialize the GIC driver, CPU and distributor interfaces */
111 plat_qti_gic_driver_init();
112 plat_qti_gic_init();
113 qti_interrupt_svc_init();
114 qtiseclib_bl31_platform_setup();
115
116 /* set boot state to cold boot complete. */
117 g_qti_bl31_cold_booted = 0x1;
118 }
119
120 /*******************************************************************************
121 * Return a pointer to the 'entry_point_info' structure of the next image for the
122 * security state specified. BL33 corresponds to the non-secure image type
123 * while BL32 corresponds to the secure image type. A NULL pointer is returned
124 * if the image does not exist.
125 ******************************************************************************/
bl31_plat_get_next_image_ep_info(uint32_t type)126 entry_point_info_t *bl31_plat_get_next_image_ep_info(uint32_t type)
127 {
128 /* QTI platform don't have BL32 implementation. */
129 assert(type == NON_SECURE);
130 assert(bl33_image_ep_info.h.type == PARAM_EP);
131 assert(bl33_image_ep_info.h.attr == NON_SECURE);
132 /*
133 * None of the images on the platforms can have 0x0
134 * as the entrypoint.
135 */
136 if (bl33_image_ep_info.pc) {
137 return &bl33_image_ep_info;
138 } else {
139 return NULL;
140 }
141 }
142
143 /*******************************************************************************
144 * This function is used by the architecture setup code to retrieve the counter
145 * frequency for the CPU's generic timer. This value will be programmed into the
146 * CNTFRQ_EL0 register. In Arm standard platforms, it returns the base frequency
147 * of the system counter, which is retrieved from the first entry in the
148 * frequency modes table. This will be used later in warm boot (psci_arch_setup)
149 * of CPUs to set when CPU frequency.
150 ******************************************************************************/
plat_get_syscnt_freq2(void)151 unsigned int plat_get_syscnt_freq2(void)
152 {
153 assert(g_qti_cpu_cntfrq != 0);
154 return g_qti_cpu_cntfrq;
155 }
156