1 /* 2 * Copyright (c) 2018, ARM Limited and Contributors. All rights reserved. 3 * Copyright (c) 2018-2020, The Linux Foundation. All rights reserved. 4 * 5 * SPDX-License-Identifier: BSD-3-Clause 6 */ 7 #ifndef PLATFORM_DEF_H 8 #define PLATFORM_DEF_H 9 10 /* Enable the dynamic translation tables library. */ 11 #define PLAT_XLAT_TABLES_DYNAMIC 1 12 13 #include <common_def.h> 14 15 #include <qti_board_def.h> 16 #include <qtiseclib_defs_plat.h> 17 18 /*----------------------------------------------------------------------------*/ 19 20 /*----------------------------------------------------------------------------*/ 21 /* 22 * MPIDR_PRIMARY_CPU 23 * You just need to have the correct core_affinity_val i.e. [7:0] 24 * and cluster_affinity_val i.e. [15:8] 25 * the other bits will be ignored 26 */ 27 /*----------------------------------------------------------------------------*/ 28 #define MPIDR_PRIMARY_CPU 0x0000 29 /*----------------------------------------------------------------------------*/ 30 31 #define QTI_PWR_LVL0 MPIDR_AFFLVL0 32 #define QTI_PWR_LVL1 MPIDR_AFFLVL1 33 #define QTI_PWR_LVL2 MPIDR_AFFLVL2 34 #define QTI_PWR_LVL3 MPIDR_AFFLVL3 35 36 /* 37 * Macros for local power states encoded by State-ID field 38 * within the power-state parameter. 39 */ 40 /* Local power state for power domains in Run state. */ 41 #define QTI_LOCAL_STATE_RUN 0 42 /* 43 * Local power state for clock-gating. Valid only for CPU and not cluster power 44 * domains 45 */ 46 #define QTI_LOCAL_STATE_STB 1 47 /* 48 * Local power state for retention. Valid for CPU and cluster power 49 * domains 50 */ 51 #define QTI_LOCAL_STATE_RET 2 52 /* 53 * Local power state for OFF/power down. Valid for CPU, cluster, RSC and PDC 54 * power domains 55 */ 56 #define QTI_LOCAL_STATE_OFF 3 57 /* 58 * Local power state for DEEPOFF/power rail down. Valid for CPU, cluster and RSC 59 * power domains 60 */ 61 #define QTI_LOCAL_STATE_DEEPOFF 4 62 63 /* 64 * This macro defines the deepest retention state possible. A higher state 65 * id will represent an invalid or a power down state. 66 */ 67 #define PLAT_MAX_RET_STATE QTI_LOCAL_STATE_RET 68 69 /* 70 * This macro defines the deepest power down states possible. Any state ID 71 * higher than this is invalid. 72 */ 73 #define PLAT_MAX_OFF_STATE QTI_LOCAL_STATE_DEEPOFF 74 75 /****************************************************************************** 76 * Required platform porting definitions common to all ARM standard platforms 77 *****************************************************************************/ 78 79 /* 80 * Platform specific page table and MMU setup constants. 81 */ 82 #define MAX_MMAP_REGIONS (PLAT_QTI_MMAP_ENTRIES) 83 84 #define PLAT_PHY_ADDR_SPACE_SIZE (1ull << 36) 85 #define PLAT_VIRT_ADDR_SPACE_SIZE (1ull << 36) 86 87 #define ARM_CACHE_WRITEBACK_SHIFT 6 88 89 /* 90 * Some data must be aligned on the biggest cache line size in the platform. 91 * This is known only to the platform as it might have a combination of 92 * integrated and external caches. 93 */ 94 #define CACHE_WRITEBACK_GRANULE (1 << ARM_CACHE_WRITEBACK_SHIFT) 95 96 /* 97 * One cache line needed for bakery locks on ARM platforms 98 */ 99 #define PLAT_PERCPU_BAKERY_LOCK_SIZE (1 * CACHE_WRITEBACK_GRANULE) 100 101 /*----------------------------------------------------------------------------*/ 102 /* PSCI power domain topology definitions */ 103 /*----------------------------------------------------------------------------*/ 104 /* One domain each to represent RSC and PDC level */ 105 #define PLAT_PDC_COUNT 1 106 #define PLAT_RSC_COUNT 1 107 108 /* There is one top-level FCM cluster */ 109 #define PLAT_CLUSTER_COUNT 1 110 111 /* No. of cores in the FCM cluster */ 112 #define PLAT_CLUSTER0_CORE_COUNT 8 113 114 #define PLATFORM_CORE_COUNT (PLAT_CLUSTER0_CORE_COUNT) 115 116 #define PLAT_NUM_PWR_DOMAINS (PLAT_PDC_COUNT +\ 117 PLAT_RSC_COUNT +\ 118 PLAT_CLUSTER_COUNT +\ 119 PLATFORM_CORE_COUNT) 120 121 #define PLAT_MAX_PWR_LVL 3 122 123 /*****************************************************************************/ 124 /* Memory mapped Generic timer interfaces */ 125 /*****************************************************************************/ 126 127 /*----------------------------------------------------------------------------*/ 128 /* GIC-600 constants */ 129 /*----------------------------------------------------------------------------*/ 130 #define BASE_GICD_BASE 0x17A00000 131 #define BASE_GICR_BASE 0x17A60000 132 #define BASE_GICC_BASE 0x0 133 #define BASE_GICH_BASE 0x0 134 #define BASE_GICV_BASE 0x0 135 136 #define QTI_GICD_BASE BASE_GICD_BASE 137 #define QTI_GICR_BASE BASE_GICR_BASE 138 #define QTI_GICC_BASE BASE_GICC_BASE 139 140 /*----------------------------------------------------------------------------*/ 141 142 /*----------------------------------------------------------------------------*/ 143 /* UART related constants. */ 144 /*----------------------------------------------------------------------------*/ 145 /* BASE ADDRESS OF DIFFERENT REGISTER SPACES IN HW */ 146 #define GENI4_CFG 0x0 147 #define GENI4_IMAGE_REGS 0x100 148 #define GENI4_DATA 0x600 149 150 /* COMMON STATUS/CONFIGURATION REGISTERS AND MASKS */ 151 #define GENI_STATUS_REG (GENI4_CFG + 0x00000040) 152 #define GENI_STATUS_M_GENI_CMD_ACTIVE_MASK (0x1) 153 #define UART_TX_TRANS_LEN_REG (GENI4_IMAGE_REGS + 0x00000170) 154 /* MASTER/TX ENGINE REGISTERS */ 155 #define GENI_M_CMD0_REG (GENI4_DATA + 0x00000000) 156 /* FIFO, STATUS REGISTERS AND MASKS */ 157 #define GENI_TX_FIFOn_REG (GENI4_DATA + 0x00000100) 158 159 #define GENI_M_CMD_TX (0x08000000) 160 161 /*----------------------------------------------------------------------------*/ 162 /* Device address space for mapping. Excluding starting 4K */ 163 /*----------------------------------------------------------------------------*/ 164 #define QTI_DEVICE_BASE 0x1000 165 #define QTI_DEVICE_SIZE (0x80000000 - QTI_DEVICE_BASE) 166 167 /******************************************************************************* 168 * BL31 specific defines. 169 ******************************************************************************/ 170 /* 171 * Put BL31 at DDR as per memory map. BL31_BASE is calculated using the 172 * current BL31 debug size plus a little space for growth. 173 */ 174 #define BL31_LIMIT (BL31_BASE + BL31_SIZE) 175 176 /*----------------------------------------------------------------------------*/ 177 /* AOSS registers */ 178 /*----------------------------------------------------------------------------*/ 179 #define QTI_PS_HOLD_REG 0x0C264000 180 /*----------------------------------------------------------------------------*/ 181 /* AOP CMD DB address space for mapping */ 182 /*----------------------------------------------------------------------------*/ 183 #define QTI_AOP_CMD_DB_BASE 0x80820000 184 #define QTI_AOP_CMD_DB_SIZE 0x00020000 185 /*----------------------------------------------------------------------------*/ 186 /* SOC hw version register */ 187 /*----------------------------------------------------------------------------*/ 188 #define QTI_SOC_VERSION U(0x7180) 189 #define QTI_SOC_VERSION_MASK U(0xFFFF) 190 #define QTI_SOC_REVISION_REG 0x1FC8000 191 #define QTI_SOC_REVISION_MASK U(0xFFFF) 192 /*----------------------------------------------------------------------------*/ 193 /* LC PON register offsets */ 194 /*----------------------------------------------------------------------------*/ 195 #define PON_PS_HOLD_RESET_CTL 0x85a 196 #define PON_PS_HOLD_RESET_CTL2 0x85b 197 /*----------------------------------------------------------------------------*/ 198 199 #endif /* PLATFORM_DEF_H */ 200