1 /*
2 * Copyright (c) 2013-2014, ARM Limited and Contributors. All rights reserved.
3 * Copyright (c) 2015-2020, Renesas Electronics Corporation. All rights reserved.
4 *
5 * SPDX-License-Identifier: BSD-3-Clause
6 */
7
8 #include <stddef.h>
9
10 #include <arch.h>
11 #include <arch_helpers.h>
12 #include <bl31/bl31.h>
13 #include <common/bl_common.h>
14 #include <common/debug.h>
15 #include <drivers/arm/cci.h>
16 #include <drivers/console.h>
17 #include <lib/mmio.h>
18 #include <plat/common/platform.h>
19
20 #include "pwrc.h"
21 #include "rcar_def.h"
22 #include "rcar_private.h"
23 #include "rcar_version.h"
24
25 static const uint64_t BL31_RO_BASE = BL_CODE_BASE;
26 static const uint64_t BL31_RO_LIMIT = BL_CODE_END;
27
28 #if USE_COHERENT_MEM
29 static const uint64_t BL31_COHERENT_RAM_BASE = BL_COHERENT_RAM_BASE;
30 static const uint64_t BL31_COHERENT_RAM_LIMIT = BL_COHERENT_RAM_END;
31 #endif /* USE_COHERENT_MEM */
32
33 extern void plat_rcar_gic_driver_init(void);
34 extern void plat_rcar_gic_init(void);
35
36 u_register_t rcar_boot_mpidr;
37
38 static int cci_map[] = {
39 CCI500_CLUSTER0_SL_IFACE_IX_FOR_M3,
40 CCI500_CLUSTER1_SL_IFACE_IX_FOR_M3
41 };
42
plat_cci_init(void)43 void plat_cci_init(void)
44 {
45 uint32_t prd;
46
47 prd = mmio_read_32(RCAR_PRR) & (PRR_PRODUCT_MASK | PRR_CUT_MASK);
48
49 if (PRR_PRODUCT_H3_CUT10 == prd || PRR_PRODUCT_H3_CUT11 == prd) {
50 cci_map[0U] = CCI500_CLUSTER0_SL_IFACE_IX;
51 cci_map[1U] = CCI500_CLUSTER1_SL_IFACE_IX;
52 }
53
54 cci_init(RCAR_CCI_BASE, cci_map, ARRAY_SIZE(cci_map));
55 }
56
plat_cci_enable(void)57 void plat_cci_enable(void)
58 {
59 cci_enable_snoop_dvm_reqs(MPIDR_AFFLVL1_VAL(read_mpidr()));
60 }
61
plat_cci_disable(void)62 void plat_cci_disable(void)
63 {
64 cci_disable_snoop_dvm_reqs(MPIDR_AFFLVL1_VAL(read_mpidr()));
65 }
66
bl31_plat_get_next_image_ep_info(uint32_t type)67 struct entry_point_info *bl31_plat_get_next_image_ep_info(uint32_t type)
68 {
69 bl2_to_bl31_params_mem_t *from_bl2 = (bl2_to_bl31_params_mem_t *)
70 PARAMS_BASE;
71 entry_point_info_t *next_image_info;
72
73 next_image_info = (type == NON_SECURE) ?
74 &from_bl2->bl33_ep_info : &from_bl2->bl32_ep_info;
75
76 return next_image_info->pc ? next_image_info : NULL;
77 }
78
bl31_early_platform_setup2(u_register_t arg0,u_register_t arg1,u_register_t arg2,u_register_t arg3)79 void bl31_early_platform_setup2(u_register_t arg0, u_register_t arg1,
80 u_register_t arg2, u_register_t arg3)
81 {
82 rcar_console_runtime_init();
83
84 NOTICE("BL3-1 : Rev.%s\n", version_of_renesas);
85
86 #if RCAR_LSI != RCAR_D3
87 if (rcar_pwrc_get_cluster() == RCAR_CLUSTER_A53A57) {
88 plat_cci_init();
89 plat_cci_enable();
90 }
91 #endif /* RCAR_LSI != RCAR_D3 */
92 }
93
bl31_plat_arch_setup(void)94 void bl31_plat_arch_setup(void)
95 {
96 rcar_configure_mmu_el3(BL31_BASE,
97 BL31_LIMIT - BL31_BASE,
98 BL31_RO_BASE, BL31_RO_LIMIT
99 #if USE_COHERENT_MEM
100 , BL31_COHERENT_RAM_BASE, BL31_COHERENT_RAM_LIMIT
101 #endif /* USE_COHERENT_MEM */
102 );
103 rcar_pwrc_code_copy_to_system_ram();
104 }
105
bl31_platform_setup(void)106 void bl31_platform_setup(void)
107 {
108 plat_rcar_gic_driver_init();
109 plat_rcar_gic_init();
110
111 /* enable the system level generic timer */
112 mmio_write_32(RCAR_CNTC_BASE + CNTCR_OFF, CNTCR_FCREQ(U(0)) | CNTCR_EN);
113
114 rcar_pwrc_setup();
115 #if 0
116 /*
117 * TODO: there is a broad number of rcar-gen3 SoC configurations; to
118 * support all of them, Renesas use the pwrc driver to discover what
119 * cores are on/off before announcing the topology.
120 * This code hasnt been ported yet
121 */
122
123 rcar_setup_topology();
124 #endif
125
126 /*
127 * mask should match the kernel's MPIDR_HWID_BITMASK so the core can be
128 * identified during cpuhotplug (check the kernel's psci migrate set of
129 * functions
130 */
131 rcar_boot_mpidr = read_mpidr_el1() & 0x0000ffffU;
132 }
133