1 /*
2  * Copyright (c) 2016, ARM Limited and Contributors. All rights reserved.
3  *
4  * SPDX-License-Identifier: BSD-3-Clause
5  */
6 
7 #include <platform_def.h>
8 
9 #include <common/bl_common.h>
10 #include <common/interrupt_props.h>
11 #include <drivers/arm/gicv3.h>
12 #include <lib/utils.h>
13 #include <plat/common/platform.h>
14 
15 /******************************************************************************
16  * The following functions are defined as weak to allow a platform to override
17  * the way the GICv3 driver is initialised and used.
18  *****************************************************************************/
19 #pragma weak plat_rockchip_gic_driver_init
20 #pragma weak plat_rockchip_gic_init
21 #pragma weak plat_rockchip_gic_cpuif_enable
22 #pragma weak plat_rockchip_gic_cpuif_disable
23 #pragma weak plat_rockchip_gic_pcpu_init
24 
25 /* The GICv3 driver only needs to be initialized in EL3 */
26 uintptr_t rdistif_base_addrs[PLATFORM_CORE_COUNT];
27 
28 static const interrupt_prop_t g01s_interrupt_props[] = {
29 	PLAT_RK_GICV3_G0_IRQS,
30 	PLAT_RK_GICV3_G1S_IRQS
31 };
32 
plat_rockchip_mpidr_to_core_pos(unsigned long mpidr)33 static unsigned int plat_rockchip_mpidr_to_core_pos(unsigned long mpidr)
34 {
35 	return (unsigned int)plat_core_pos_by_mpidr(mpidr);
36 }
37 
38 const gicv3_driver_data_t rockchip_gic_data = {
39 	.gicd_base = PLAT_RK_GICD_BASE,
40 	.gicr_base = PLAT_RK_GICR_BASE,
41 	.interrupt_props = g01s_interrupt_props,
42 	.interrupt_props_num = ARRAY_SIZE(g01s_interrupt_props),
43 	.rdistif_num = PLATFORM_CORE_COUNT,
44 	.rdistif_base_addrs = rdistif_base_addrs,
45 	.mpidr_to_core_pos = plat_rockchip_mpidr_to_core_pos,
46 };
47 
plat_rockchip_gic_driver_init(void)48 void plat_rockchip_gic_driver_init(void)
49 {
50 	/*
51 	 * The GICv3 driver is initialized in EL3 and does not need
52 	 * to be initialized again in SEL1. This is because the S-EL1
53 	 * can use GIC system registers to manage interrupts and does
54 	 * not need GIC interface base addresses to be configured.
55 	 */
56 #ifdef IMAGE_BL31
57 	gicv3_driver_init(&rockchip_gic_data);
58 #endif
59 }
60 
61 /******************************************************************************
62  * RockChip common helper to initialize the GIC. Only invoked
63  * by BL31
64  *****************************************************************************/
plat_rockchip_gic_init(void)65 void plat_rockchip_gic_init(void)
66 {
67 	gicv3_distif_init();
68 	gicv3_rdistif_init(plat_my_core_pos());
69 	gicv3_cpuif_enable(plat_my_core_pos());
70 }
71 
72 /******************************************************************************
73  * RockChip common helper to enable the GIC CPU interface
74  *****************************************************************************/
plat_rockchip_gic_cpuif_enable(void)75 void plat_rockchip_gic_cpuif_enable(void)
76 {
77 	gicv3_cpuif_enable(plat_my_core_pos());
78 }
79 
80 /******************************************************************************
81  * RockChip common helper to disable the GIC CPU interface
82  *****************************************************************************/
plat_rockchip_gic_cpuif_disable(void)83 void plat_rockchip_gic_cpuif_disable(void)
84 {
85 	gicv3_cpuif_disable(plat_my_core_pos());
86 }
87 
88 /******************************************************************************
89  * RockChip common helper to initialize the per-cpu redistributor interface
90  * in GICv3
91  *****************************************************************************/
plat_rockchip_gic_pcpu_init(void)92 void plat_rockchip_gic_pcpu_init(void)
93 {
94 	gicv3_rdistif_init(plat_my_core_pos());
95 }
96