1 /*
2  * Copyright (c) 2019, ARM Limited and Contributors. All rights reserved.
3  *
4  * SPDX-License-Identifier: BSD-3-Clause
5  */
6 
7 #ifndef __PX30_DEF_H__
8 #define __PX30_DEF_H__
9 
10 #define MAJOR_VERSION		(1)
11 #define MINOR_VERSION		(0)
12 
13 #define SIZE_K(n)		((n) * 1024)
14 #define SIZE_M(n)		((n) * 1024 * 1024)
15 
16 #define WITH_16BITS_WMSK(bits)	(0xffff0000 | (bits))
17 
18 /* Special value used to verify platform parameters from BL2 to BL3-1 */
19 #define RK_BL31_PLAT_PARAM_VAL	0x0f1e2d3c4b5a6978ULL
20 
21 #define PMU_BASE		0xff000000
22 #define PMU_SIZE		SIZE_K(64)
23 
24 #define PMUGRF_BASE		0xff010000
25 #define PMUGRF_SIZE		SIZE_K(64)
26 
27 #define PMUSRAM_BASE		0xff020000
28 #define PMUSRAM_SIZE		SIZE_K(64)
29 #define PMUSRAM_RSIZE		SIZE_K(8)
30 
31 #define UART0_BASE		0xff030000
32 #define UART0_SIZE		SIZE_K(64)
33 
34 #define GPIO0_BASE		0xff040000
35 #define GPIO0_SIZE		SIZE_K(64)
36 
37 #define PMUSGRF_BASE		0xff050000
38 #define PMUSGRF_SIZE		SIZE_K(64)
39 
40 #define INTSRAM_BASE		0xff0e0000
41 #define INTSRAM_SIZE		SIZE_K(64)
42 
43 #define SGRF_BASE		0xff11c000
44 #define SGRF_SIZE		SIZE_K(16)
45 
46 #define GIC400_BASE		0xff130000
47 #define GIC400_SIZE		SIZE_K(64)
48 
49 #define GRF_BASE		0xff140000
50 #define GRF_SIZE		SIZE_K(64)
51 
52 #define UART1_BASE		0xff158000
53 #define UART1_SIZE		SIZE_K(64)
54 
55 #define UART2_BASE		0xff160000
56 #define UART2_SIZE		SIZE_K(64)
57 
58 #define UART3_BASE		0xff168000
59 #define UART3_SIZE		SIZE_K(64)
60 
61 #define UART5_BASE		0xff178000
62 #define UART5_SIZE		SIZE_K(64)
63 
64 #define I2C0_BASE		0xff180000
65 #define I2C0_SIZE		SIZE_K(64)
66 
67 #define PWM0_BASE		0xff200000
68 #define PWM0_SIZE		SIZE_K(32)
69 
70 #define PWM1_BASE		0xff208000
71 #define PWM1_SIZE		SIZE_K(32)
72 
73 #define NTIME_BASE		0xff210000
74 #define NTIME_SIZE		SIZE_K(64)
75 
76 #define STIME_BASE		0xff220000
77 #define STIME_SIZE		SIZE_K(64)
78 
79 #define DCF_BASE		0xff230000
80 #define DCF_SIZE		SIZE_K(64)
81 
82 #define GPIO1_BASE		0xff250000
83 #define GPIO1_SIZE		SIZE_K(64)
84 
85 #define GPIO2_BASE		0xff260000
86 #define GPIO2_SIZE		SIZE_K(64)
87 
88 #define GPIO3_BASE		0xff270000
89 #define GPIO3_SIZE		SIZE_K(64)
90 
91 #define DDR_PHY_BASE		0xff2a0000
92 #define DDR_PHY_SIZE		SIZE_K(64)
93 
94 #define CRU_BASE		0xff2b0000
95 #define CRU_SIZE		SIZE_K(32)
96 
97 #define CRU_BOOST_BASE		0xff2b8000
98 #define CRU_BOOST_SIZE		SIZE_K(16)
99 
100 #define PMUCRU_BASE		0xff2bc000
101 #define PMUCRU_SIZE		SIZE_K(16)
102 
103 #define VOP_BASE		0xff460000
104 #define VOP_SIZE		SIZE_K(16)
105 
106 #define SERVER_MSCH_BASE	0xff530000
107 #define SERVER_MSCH_SIZE	SIZE_K(64)
108 
109 #define FIREWALL_DDR_BASE	0xff534000
110 #define FIREWALL_DDR_SIZE	SIZE_K(16)
111 
112 #define DDR_UPCTL_BASE		0xff600000
113 #define DDR_UPCTL_SIZE		SIZE_K(64)
114 
115 #define DDR_MNTR_BASE		0xff610000
116 #define DDR_MNTR_SIZE		SIZE_K(64)
117 
118 #define DDR_STDBY_BASE		0xff620000
119 #define DDR_STDBY_SIZE		SIZE_K(64)
120 
121 #define DDRGRF_BASE		0xff630000
122 #define DDRGRF_SIZE		SIZE_K(32)
123 
124 /**************************************************************************
125  * UART related constants
126  **************************************************************************/
127 #define PX30_UART_BASE		UART2_BASE
128 #define PX30_BAUDRATE		1500000
129 #define PX30_UART_CLOCK		24000000
130 
131 /******************************************************************************
132  * System counter frequency related constants
133  ******************************************************************************/
134 #define SYS_COUNTER_FREQ_IN_TICKS	24000000
135 #define SYS_COUNTER_FREQ_IN_MHZ		24
136 
137 /******************************************************************************
138  * GIC-400 & interrupt handling related constants
139  ******************************************************************************/
140 
141 /* Base rk_platform compatible GIC memory map */
142 #define PX30_GICD_BASE		(GIC400_BASE + 0x1000)
143 #define PX30_GICC_BASE		(GIC400_BASE + 0x2000)
144 #define PX30_GICR_BASE		0	/* no GICR in GIC-400 */
145 
146 /******************************************************************************
147  * sgi, ppi
148  ******************************************************************************/
149 #define RK_IRQ_SEC_PHY_TIMER	29
150 
151 #define RK_IRQ_SEC_SGI_0	8
152 #define RK_IRQ_SEC_SGI_1	9
153 #define RK_IRQ_SEC_SGI_2	10
154 #define RK_IRQ_SEC_SGI_3	11
155 #define RK_IRQ_SEC_SGI_4	12
156 #define RK_IRQ_SEC_SGI_5	13
157 #define RK_IRQ_SEC_SGI_6	14
158 #define RK_IRQ_SEC_SGI_7	15
159 
160 /*
161  * Define a list of Group 0 interrupts.
162  */
163 #define PLAT_RK_GICV2_G0_IRQS						\
164 	INTR_PROP_DESC(RK_IRQ_SEC_PHY_TIMER, GIC_HIGHEST_SEC_PRIORITY,	\
165 		       GICV2_INTR_GROUP0, GIC_INTR_CFG_LEVEL),		\
166 	INTR_PROP_DESC(RK_IRQ_SEC_SGI_6, GIC_HIGHEST_SEC_PRIORITY,	\
167 		       GICV2_INTR_GROUP0, GIC_INTR_CFG_LEVEL)
168 
169 #define SHARE_MEM_BASE		0x100000/* [1MB, 1MB+60K]*/
170 #define SHARE_MEM_PAGE_NUM	15
171 #define SHARE_MEM_SIZE		SIZE_K(SHARE_MEM_PAGE_NUM * 4)
172 
173 #define DDR_PARAM_BASE		0x02000000
174 #define DDR_PARAM_SIZE		SIZE_K(4)
175 
176 #endif /* __PLAT_DEF_H__ */
177