1 /* 2 * Copyright (c) 2016, ARM Limited and Contributors. All rights reserved. 3 * 4 * SPDX-License-Identifier: BSD-3-Clause 5 */ 6 7 #ifndef SECURE_H 8 #define SECURE_H 9 10 /****************************************************************************** 11 * TZPC TrustZone controller 12 ******************************************************************************/ 13 14 #define TZPC_R0SIZE 0x0 15 #define TZPC_SRAM_SECURE_4K(n) ((n) > 0x200 ? 0x200 : (n)) 16 #define TZPC_DECPROT1STAT 0x80c 17 #define TZPC_DECPROT1SET 0x810 18 #define TZPC_DECPROT1CLR 0x814 19 #define TZPC_DECPROT2STAT 0x818 20 #define TZPC_DECPROT2SET 0x818 21 #define TZPC_DECPROT2CLR 0x820 22 23 /************************************************** 24 * sgrf reg, offset 25 **************************************************/ 26 /* 27 * soc_con0-5 start at 0x0, soc_con6-... start art 0x50 28 * adjusted for the 5 lower registers 29 */ 30 #define SGRF_SOC_CON(n) ((((n) < 6) ? 0x0 : 0x38) + (n) * 4) 31 #define SGRF_BUSDMAC_CON(n) (0x20 + (n) * 4) 32 #define SGRF_CPU_CON(n) (0x40 + (n) * 4) 33 #define SGRF_SOC_STATUS(n) (0x100 + (n) * 4) 34 #define SGRF_FAST_BOOT_ADDR 0x120 35 36 /* SGRF_SOC_CON0 */ 37 #define SGRF_FAST_BOOT_ENA BIT_WITH_WMSK(8) 38 #define SGRF_FAST_BOOT_DIS WMSK_BIT(8) 39 #define SGRF_PCLK_WDT_GATE BIT_WITH_WMSK(6) 40 #define SGRF_PCLK_WDT_UNGATE WMSK_BIT(6) 41 #define SGRF_PCLK_STIMER_GATE BIT_WITH_WMSK(4) 42 43 #define SGRF_SOC_CON2_MST_NS 0xffe0ffe0 44 #define SGRF_SOC_CON3_MST_NS 0x003f003f 45 46 /* SGRF_SOC_CON4 */ 47 #define SGRF_SOC_CON4_SECURE_WMSK 0xffff0000 48 #define SGRF_DDRC1_SECURE BIT_WITH_WMSK(12) 49 #define SGRF_DDRC0_SECURE BIT_WITH_WMSK(11) 50 #define SGRF_PMUSRAM_SECURE BIT_WITH_WMSK(8) 51 #define SGRF_WDT_SECURE BIT_WITH_WMSK(7) 52 #define SGRF_STIMER_SECURE BIT_WITH_WMSK(6) 53 54 /* SGRF_SOC_CON5 */ 55 #define SGRF_SLV_SEC_BYPS BIT_WITH_WMSK(15) 56 #define SGRF_SLV_SEC_NO_BYPS WMSK_BIT(15) 57 #define SGRF_SOC_CON5_SECURE_WMSK 0x00ff0000 58 59 /* ddr regions in SGRF_SOC_CON6 and following */ 60 #define SGRF_DDR_RGN_SECURE_SEL BIT_WITH_WMSK(15) 61 #define SGRF_DDR_RGN_SECURE_EN BIT_WITH_WMSK(14) 62 #define SGRF_DDR_RGN_ADDR_WMSK 0x0fff 63 64 /* SGRF_SOC_CON21 */ 65 /* All security of the DDR RGNs are bypassed */ 66 #define SGRF_DDR_RGN_BYPS BIT_WITH_WMSK(15) 67 #define SGRF_DDR_RGN_NO_BYPS WMSK_BIT(15) 68 69 /* SGRF_CPU_CON0 */ 70 #define SGRF_DAPDEVICE_ENA BIT_WITH_WMSK(0) 71 #define SGRF_DAPDEVICE_MSK WMSK_BIT(0) 72 73 /***************************************************************************** 74 * core-axi 75 *****************************************************************************/ 76 #define CORE_AXI_SECURITY0 0x08 77 #define AXI_SECURITY0_GIC BIT(0) 78 79 /***************************************************************************** 80 * secure timer 81 *****************************************************************************/ 82 #define TIMER_LOAD_COUNT0 0x00 83 #define TIMER_LOAD_COUNT1 0x04 84 #define TIMER_CURRENT_VALUE0 0x08 85 #define TIMER_CURRENT_VALUE1 0x0C 86 #define TIMER_CONTROL_REG 0x10 87 #define TIMER_INTSTATUS 0x18 88 89 #define TIMER_EN 0x1 90 91 #define STIMER1_BASE (STIME_BASE + 0x20) 92 93 /* export secure operating APIs */ 94 void secure_watchdog_gate(void); 95 void secure_watchdog_ungate(void); 96 void secure_gic_init(void); 97 void secure_timer_init(void); 98 void secure_sgrf_init(void); 99 void secure_sgrf_ddr_rgn_init(void); 100 __pmusramfunc void sram_secure_timer_init(void); 101 102 #endif /* SECURE_H */ 103