1 /* 2 * Copyright (c) 2016, ARM Limited and Contributors. All rights reserved. 3 * 4 * SPDX-License-Identifier: BSD-3-Clause 5 */ 6 7 #ifndef DRAM_SPEC_TIMING_H 8 #define DRAM_SPEC_TIMING_H 9 10 #include <stdint.h> 11 12 enum ddr3_speed_rate { 13 /* 5-5-5 */ 14 DDR3_800D = 0, 15 /* 6-6-6 */ 16 DDR3_800E = 1, 17 /* 6-6-6 */ 18 DDR3_1066E = 2, 19 /* 7-7-7 */ 20 DDR3_1066F = 3, 21 /* 8-8-8 */ 22 DDR3_1066G = 4, 23 /* 7-7-7 */ 24 DDR3_1333F = 5, 25 /* 8-8-8 */ 26 DDR3_1333G = 6, 27 /* 9-9-9 */ 28 DDR3_1333H = 7, 29 /* 10-10-10 */ 30 DDR3_1333J = 8, 31 /* 8-8-8 */ 32 DDR3_1600G = 9, 33 /* 9-9-9 */ 34 DDR3_1600H = 10, 35 /* 10-10-10 */ 36 DDR3_1600J = 11, 37 /* 11-11-11 */ 38 DDR3_1600K = 12, 39 /* 10-10-10 */ 40 DDR3_1866J = 13, 41 /* 11-11-11 */ 42 DDR3_1866K = 14, 43 /* 12-12-12 */ 44 DDR3_1866L = 15, 45 /* 13-13-13 */ 46 DDR3_1866M = 16, 47 /* 11-11-11 */ 48 DDR3_2133K = 17, 49 /* 12-12-12 */ 50 DDR3_2133L = 18, 51 /* 13-13-13 */ 52 DDR3_2133M = 19, 53 /* 14-14-14 */ 54 DDR3_2133N = 20, 55 DDR3_DEFAULT = 21, 56 }; 57 58 #define max(a, b) (((a) > (b)) ? (a) : (b)) 59 #define range(mi, val, ma) (((ma) > (val)) ? (max(mi, val)) : (ma)) 60 61 struct dram_timing_t { 62 /* unit MHz */ 63 uint32_t mhz; 64 /* some timing unit is us */ 65 uint32_t tinit1; 66 uint32_t tinit2; 67 uint32_t tinit3; 68 uint32_t tinit4; 69 uint32_t tinit5; 70 /* reset low, DDR3:200us */ 71 uint32_t trstl; 72 /* reset high to CKE high, DDR3:500us */ 73 uint32_t trsth; 74 uint32_t trefi; 75 /* base */ 76 uint32_t trcd; 77 /* trp per bank */ 78 uint32_t trppb; 79 /* trp all bank */ 80 uint32_t trp; 81 uint32_t twr; 82 uint32_t tdal; 83 uint32_t trtp; 84 uint32_t trc; 85 uint32_t trrd; 86 uint32_t tccd; 87 uint32_t twtr; 88 uint32_t trtw; 89 uint32_t tras_max; 90 uint32_t tras_min; 91 uint32_t tfaw; 92 uint32_t trfc; 93 uint32_t tdqsck; 94 uint32_t tdqsck_max; 95 /* pd or sr */ 96 uint32_t txsr; 97 uint32_t txsnr; 98 uint32_t txp; 99 uint32_t txpdll; 100 uint32_t tdllk; 101 uint32_t tcke; 102 uint32_t tckesr; 103 uint32_t tcksre; 104 uint32_t tcksrx; 105 uint32_t tdpd; 106 /* mode regiter timing */ 107 uint32_t tmod; 108 uint32_t tmrd; 109 uint32_t tmrr; 110 uint32_t tmrri; 111 /* ODT */ 112 uint32_t todton; 113 /* ZQ */ 114 uint32_t tzqinit; 115 uint32_t tzqcs; 116 uint32_t tzqoper; 117 uint32_t tzqreset; 118 /* Write Leveling */ 119 uint32_t twlmrd; 120 uint32_t twlo; 121 uint32_t twldqsen; 122 /* CA Training */ 123 uint32_t tcackel; 124 uint32_t tcaent; 125 uint32_t tcamrd; 126 uint32_t tcackeh; 127 uint32_t tcaext; 128 uint32_t tadr; 129 uint32_t tmrz; 130 uint32_t tcacd; 131 /* mode register */ 132 uint32_t mr[4]; 133 uint32_t mr11; 134 /* lpddr4 spec */ 135 uint32_t mr12; 136 uint32_t mr13; 137 uint32_t mr14; 138 uint32_t mr16; 139 uint32_t mr17; 140 uint32_t mr20; 141 uint32_t mr22; 142 uint32_t tccdmw; 143 uint32_t tppd; 144 uint32_t tescke; 145 uint32_t tsr; 146 uint32_t tcmdcke; 147 uint32_t tcscke; 148 uint32_t tckelcs; 149 uint32_t tcsckeh; 150 uint32_t tckehcs; 151 uint32_t tmrwckel; 152 uint32_t tzqcal; 153 uint32_t tzqlat; 154 uint32_t tzqcke; 155 uint32_t tvref_long; 156 uint32_t tvref_short; 157 uint32_t tvrcg_enable; 158 uint32_t tvrcg_disable; 159 uint32_t tfc_long; 160 uint32_t tckfspe; 161 uint32_t tckfspx; 162 uint32_t tckehcmd; 163 uint32_t tckelcmd; 164 uint32_t tckelpd; 165 uint32_t tckckel; 166 /* other */ 167 uint32_t al; 168 uint32_t cl; 169 uint32_t cwl; 170 uint32_t bl; 171 }; 172 173 struct dram_info_t { 174 /* speed_rate only used when DDR3 */ 175 enum ddr3_speed_rate speed_rate; 176 /* 1: use CS0, 2: use CS0 and CS1 */ 177 uint32_t cs_cnt; 178 /* give the max per-die capability on each rank/cs */ 179 uint32_t per_die_capability[2]; 180 }; 181 182 struct timing_related_config { 183 struct dram_info_t dram_info[2]; 184 uint32_t dram_type; 185 /* MHz */ 186 uint32_t freq; 187 uint32_t ch_cnt; 188 uint32_t bl; 189 /* 1:auto precharge, 0:never auto precharge */ 190 uint32_t ap; 191 /* 192 * 1:dll bypass, 0:dll normal 193 * dram and controller dll bypass at the same time 194 */ 195 uint32_t dllbp; 196 /* 1:odt enable, 0:odt disable */ 197 uint32_t odt; 198 /* 1:enable, 0:disabe */ 199 uint32_t rdbi; 200 uint32_t wdbi; 201 /* dram driver strength */ 202 uint32_t dramds; 203 /* dram ODT, if odt=0, this parameter invalid */ 204 uint32_t dramodt; 205 /* 206 * ca ODT, if odt=0, this parameter invalid 207 * it only used by LPDDR4 208 */ 209 uint32_t caodt; 210 }; 211 212 /* mr0 for ddr3 */ 213 #define DDR3_BL8 (0) 214 #define DDR3_BC4_8 (1) 215 #define DDR3_BC4 (2) 216 #define DDR3_CL(n) (((((n) - 4) & 0x7) << 4)\ 217 | ((((n) - 4) & 0x8) >> 1)) 218 #define DDR3_WR(n) (((n) & 0x7) << 9) 219 #define DDR3_DLL_RESET (1 << 8) 220 #define DDR3_DLL_DERESET (0 << 8) 221 222 /* mr1 for ddr3 */ 223 #define DDR3_DLL_ENABLE (0) 224 #define DDR3_DLL_DISABLE (1) 225 #define DDR3_MR1_AL(n) (((n) & 0x3) << 3) 226 227 #define DDR3_DS_40 (0) 228 #define DDR3_DS_34 (1 << 1) 229 #define DDR3_RTT_NOM_DIS (0) 230 #define DDR3_RTT_NOM_60 (1 << 2) 231 #define DDR3_RTT_NOM_120 (1 << 6) 232 #define DDR3_RTT_NOM_40 ((1 << 2) | (1 << 6)) 233 #define DDR3_TDQS (1 << 11) 234 235 /* mr2 for ddr3 */ 236 #define DDR3_MR2_CWL(n) ((((n) - 5) & 0x7) << 3) 237 #define DDR3_RTT_WR_DIS (0) 238 #define DDR3_RTT_WR_60 (1 << 9) 239 #define DDR3_RTT_WR_120 (2 << 9) 240 241 /* 242 * MR0 (Device Information) 243 * 0:DAI complete, 1:DAI still in progress 244 */ 245 #define LPDDR2_DAI (0x1) 246 /* 0:S2 or S4 SDRAM, 1:NVM */ 247 #define LPDDR2_DI (0x1 << 1) 248 /* 0:DNV not supported, 1:DNV supported */ 249 #define LPDDR2_DNVI (0x1 << 2) 250 #define LPDDR2_RZQI (0x3 << 3) 251 252 /* 253 * 00:RZQ self test not supported, 254 * 01:ZQ-pin may connect to VDDCA or float 255 * 10:ZQ-pin may short to GND. 256 * 11:ZQ-pin self test completed, no error condition detected. 257 */ 258 259 /* MR1 (Device Feature) */ 260 #define LPDDR2_BL4 (0x2) 261 #define LPDDR2_BL8 (0x3) 262 #define LPDDR2_BL16 (0x4) 263 #define LPDDR2_N_WR(n) (((n) - 2) << 5) 264 265 /* MR2 (Device Feature 2) */ 266 #define LPDDR2_RL3_WL1 (0x1) 267 #define LPDDR2_RL4_WL2 (0x2) 268 #define LPDDR2_RL5_WL2 (0x3) 269 #define LPDDR2_RL6_WL3 (0x4) 270 #define LPDDR2_RL7_WL4 (0x5) 271 #define LPDDR2_RL8_WL4 (0x6) 272 273 /* MR3 (IO Configuration 1) */ 274 #define LPDDR2_DS_34 (0x1) 275 #define LPDDR2_DS_40 (0x2) 276 #define LPDDR2_DS_48 (0x3) 277 #define LPDDR2_DS_60 (0x4) 278 #define LPDDR2_DS_80 (0x6) 279 /* optional */ 280 #define LPDDR2_DS_120 (0x7) 281 282 /* MR4 (Device Temperature) */ 283 #define LPDDR2_TREF_MASK (0x7) 284 #define LPDDR2_4_TREF (0x1) 285 #define LPDDR2_2_TREF (0x2) 286 #define LPDDR2_1_TREF (0x3) 287 #define LPDDR2_025_TREF (0x5) 288 #define LPDDR2_025_TREF_DERATE (0x6) 289 290 #define LPDDR2_TUF (0x1 << 7) 291 292 /* MR8 (Basic configuration 4) */ 293 #define LPDDR2_S4 (0x0) 294 #define LPDDR2_S2 (0x1) 295 #define LPDDR2_N (0x2) 296 /* Unit:MB */ 297 #define LPDDR2_DENSITY(mr8) (8 << (((mr8) >> 2) & 0xf)) 298 #define LPDDR2_IO_WIDTH(mr8) (32 >> (((mr8) >> 6) & 0x3)) 299 300 /* MR10 (Calibration) */ 301 #define LPDDR2_ZQINIT (0xff) 302 #define LPDDR2_ZQCL (0xab) 303 #define LPDDR2_ZQCS (0x56) 304 #define LPDDR2_ZQRESET (0xc3) 305 306 /* MR16 (PASR Bank Mask), S2 SDRAM Only */ 307 #define LPDDR2_PASR_FULL (0x0) 308 #define LPDDR2_PASR_1_2 (0x1) 309 #define LPDDR2_PASR_1_4 (0x2) 310 #define LPDDR2_PASR_1_8 (0x3) 311 312 /* 313 * MR0 (Device Information) 314 * 0:DAI complete, 315 * 1:DAI still in progress 316 */ 317 #define LPDDR3_DAI (0x1) 318 /* 319 * 00:RZQ self test not supported, 320 * 01:ZQ-pin may connect to VDDCA or float 321 * 10:ZQ-pin may short to GND. 322 * 11:ZQ-pin self test completed, no error condition detected. 323 */ 324 #define LPDDR3_RZQI (0x3 << 3) 325 /* 326 * 0:DRAM does not support WL(Set B), 327 * 1:DRAM support WL(Set B) 328 */ 329 #define LPDDR3_WL_SUPOT (1 << 6) 330 /* 331 * 0:DRAM does not support RL=3,nWR=3,WL=1; 332 * 1:DRAM supports RL=3,nWR=3,WL=1 for frequencies <=166 333 */ 334 #define LPDDR3_RL3_SUPOT (1 << 7) 335 336 /* MR1 (Device Feature) */ 337 #define LPDDR3_BL8 (0x3) 338 #define LPDDR3_N_WR(n) ((n) << 5) 339 340 /* MR2 (Device Feature 2), WL Set A,default */ 341 /* <=166MHz,optional*/ 342 #define LPDDR3_RL3_WL1 (0x1) 343 /* <=400MHz*/ 344 #define LPDDR3_RL6_WL3 (0x4) 345 /* <=533MHz*/ 346 #define LPDDR3_RL8_WL4 (0x6) 347 /* <=600MHz*/ 348 #define LPDDR3_RL9_WL5 (0x7) 349 /* <=667MHz,default*/ 350 #define LPDDR3_RL10_WL6 (0x8) 351 /* <=733MHz*/ 352 #define LPDDR3_RL11_WL6 (0x9) 353 /* <=800MHz*/ 354 #define LPDDR3_RL12_WL6 (0xa) 355 /* <=933MHz*/ 356 #define LPDDR3_RL14_WL8 (0xc) 357 /* <=1066MHz*/ 358 #define LPDDR3_RL16_WL8 (0xe) 359 360 /* WL Set B, optional */ 361 /* <=667MHz,default*/ 362 #define LPDDR3_RL10_WL8 (0x8) 363 /* <=733MHz*/ 364 #define LPDDR3_RL11_WL9 (0x9) 365 /* <=800MHz*/ 366 #define LPDDR3_RL12_WL9 (0xa) 367 /* <=933MHz*/ 368 #define LPDDR3_RL14_WL11 (0xc) 369 /* <=1066MHz*/ 370 #define LPDDR3_RL16_WL13 (0xe) 371 372 /* 1:enable nWR programming > 9(default)*/ 373 #define LPDDR3_N_WRE (1 << 4) 374 /* 1:Select WL Set B*/ 375 #define LPDDR3_WL_S (1 << 6) 376 /* 1:enable*/ 377 #define LPDDR3_WR_LEVEL (1 << 7) 378 379 /* MR3 (IO Configuration 1) */ 380 #define LPDDR3_DS_34 (0x1) 381 #define LPDDR3_DS_40 (0x2) 382 #define LPDDR3_DS_48 (0x3) 383 #define LPDDR3_DS_60 (0x4) 384 #define LPDDR3_DS_80 (0x6) 385 #define LPDDR3_DS_34D_40U (0x9) 386 #define LPDDR3_DS_40D_48U (0xa) 387 #define LPDDR3_DS_34D_48U (0xb) 388 389 /* MR4 (Device Temperature) */ 390 #define LPDDR3_TREF_MASK (0x7) 391 /* SDRAM Low temperature operating limit exceeded */ 392 #define LPDDR3_LT_EXED (0x0) 393 #define LPDDR3_4_TREF (0x1) 394 #define LPDDR3_2_TREF (0x2) 395 #define LPDDR3_1_TREF (0x3) 396 #define LPDDR3_05_TREF (0x4) 397 #define LPDDR3_025_TREF (0x5) 398 #define LPDDR3_025_TREF_DERATE (0x6) 399 /* SDRAM High temperature operating limit exceeded */ 400 #define LPDDR3_HT_EXED (0x7) 401 402 /* 1:value has changed since last read of MR4 */ 403 #define LPDDR3_TUF (0x1 << 7) 404 405 /* MR8 (Basic configuration 4) */ 406 #define LPDDR3_S8 (0x3) 407 #define LPDDR3_DENSITY(mr8) (8 << (((mr8) >> 2) & 0xf)) 408 #define LPDDR3_IO_WIDTH(mr8) (32 >> (((mr8) >> 6) & 0x3)) 409 410 /* MR10 (Calibration) */ 411 #define LPDDR3_ZQINIT (0xff) 412 #define LPDDR3_ZQCL (0xab) 413 #define LPDDR3_ZQCS (0x56) 414 #define LPDDR3_ZQRESET (0xc3) 415 416 /* MR11 (ODT Control) */ 417 #define LPDDR3_ODT_60 (1) 418 #define LPDDR3_ODT_120 (2) 419 #define LPDDR3_ODT_240 (3) 420 #define LPDDR3_ODT_DIS (0) 421 422 /* MR2 (Device Feature 2) */ 423 /* RL & nRTP for DBI-RD Disabled */ 424 #define LPDDR4_RL6_NRTP8 (0x0) 425 #define LPDDR4_RL10_NRTP8 (0x1) 426 #define LPDDR4_RL14_NRTP8 (0x2) 427 #define LPDDR4_RL20_NRTP8 (0x3) 428 #define LPDDR4_RL24_NRTP10 (0x4) 429 #define LPDDR4_RL28_NRTP12 (0x5) 430 #define LPDDR4_RL32_NRTP14 (0x6) 431 #define LPDDR4_RL36_NRTP16 (0x7) 432 /* RL & nRTP for DBI-RD Disabled */ 433 #define LPDDR4_RL12_NRTP8 (0x1) 434 #define LPDDR4_RL16_NRTP8 (0x2) 435 #define LPDDR4_RL22_NRTP8 (0x3) 436 #define LPDDR4_RL28_NRTP10 (0x4) 437 #define LPDDR4_RL32_NRTP12 (0x5) 438 #define LPDDR4_RL36_NRTP14 (0x6) 439 #define LPDDR4_RL40_NRTP16 (0x7) 440 /* WL Set A,default */ 441 #define LPDDR4_A_WL4 (0x0) 442 #define LPDDR4_A_WL6 (0x1) 443 #define LPDDR4_A_WL8 (0x2) 444 #define LPDDR4_A_WL10 (0x3) 445 #define LPDDR4_A_WL12 (0x4) 446 #define LPDDR4_A_WL14 (0x5) 447 #define LPDDR4_A_WL16 (0x6) 448 #define LPDDR4_A_WL18 (0x7) 449 /* WL Set B, optional */ 450 #define LPDDR4_B_WL4 (0x0 << 3) 451 #define LPDDR4_B_WL8 (0x1 << 3) 452 #define LPDDR4_B_WL12 (0x2 << 3) 453 #define LPDDR4_B_WL18 (0x3 << 3) 454 #define LPDDR4_B_WL22 (0x4 << 3) 455 #define LPDDR4_B_WL26 (0x5 << 3) 456 #define LPDDR4_B_WL30 (0x6 << 3) 457 #define LPDDR4_B_WL34 (0x7 << 3) 458 /* 1:Select WL Set B*/ 459 #define LPDDR4_WL_B (1 << 6) 460 /* 1:enable*/ 461 #define LPDDR4_WR_LEVEL (1 << 7) 462 463 /* MR3 */ 464 #define LPDDR4_VDDQ_2_5 (0) 465 #define LPDDR4_VDDQ_3 (1) 466 #define LPDDR4_WRPST_0_5_TCK (0 << 1) 467 #define LPDDR4_WRPST_1_5_TCK (1 << 1) 468 #define LPDDR4_PPR_EN (1 << 2) 469 /* PDDS */ 470 #define LPDDR4_PDDS_240 (0x1 << 3) 471 #define LPDDR4_PDDS_120 (0x2 << 3) 472 #define LPDDR4_PDDS_80 (0x3 << 3) 473 #define LPDDR4_PDDS_60 (0x4 << 3) 474 #define LPDDR4_PDDS_48 (0x5 << 3) 475 #define LPDDR4_PDDS_40 (0x6 << 3) 476 #define LPDDR4_DBI_RD_EN (1 << 6) 477 #define LPDDR4_DBI_WR_EN (1 << 7) 478 479 /* MR11 (ODT Control) */ 480 #define LPDDR4_DQODT_240 (1) 481 #define LPDDR4_DQODT_120 (2) 482 #define LPDDR4_DQODT_80 (3) 483 #define LPDDR4_DQODT_60 (4) 484 #define LPDDR4_DQODT_48 (5) 485 #define LPDDR4_DQODT_40 (6) 486 #define LPDDR4_DQODT_DIS (0) 487 #define LPDDR4_CAODT_240 (1 << 4) 488 #define LPDDR4_CAODT_120 (2 << 4) 489 #define LPDDR4_CAODT_80 (3 << 4) 490 #define LPDDR4_CAODT_60 (4 << 4) 491 #define LPDDR4_CAODT_48 (5 << 4) 492 #define LPDDR4_CAODT_40 (6 << 4) 493 #define LPDDR4_CAODT_DIS (0 << 4) 494 495 /* 496 * Description: depend on input parameter "timing_config", 497 * and calculate correspond "dram_type" 498 * spec timing to "pdram_timing" 499 * parameters: 500 * input: timing_config 501 * output: pdram_timing 502 * NOTE: MR ODT is set, need to disable by controller 503 */ 504 void dram_get_parameter(struct timing_related_config *timing_config, 505 struct dram_timing_t *pdram_timing); 506 507 #endif /* DRAM_SPEC_TIMING_H */ 508