1 /*
2 * Copyright (c) 2016-2019, ARM Limited and Contributors. All rights reserved.
3 *
4 * SPDX-License-Identifier: BSD-3-Clause
5 */
6
7 #include <assert.h>
8
9 #include <arch_helpers.h>
10 #include <common/debug.h>
11 #include <drivers/delay_timer.h>
12
13 #include <plat_private.h>
14 #include <secure.h>
15 #include <soc.h>
16
sgrf_ddr_rgn_global_bypass(uint32_t bypass)17 static void sgrf_ddr_rgn_global_bypass(uint32_t bypass)
18 {
19 if (bypass)
20 /* set bypass (non-secure regions) for whole ddr regions */
21 mmio_write_32(SGRF_BASE + SGRF_DDRRGN_CON0_16(16),
22 SGRF_DDR_RGN_BYPS);
23 else
24 /* cancel bypass for whole ddr regions */
25 mmio_write_32(SGRF_BASE + SGRF_DDRRGN_CON0_16(16),
26 SGRF_DDR_RGN_NO_BYPS);
27 }
28
29 /**
30 * There are 8 + 1 regions for DDR secure control:
31 * DDR_RGN_0 ~ DDR_RGN_7: Per DDR_RGNs grain size is 1MB
32 * DDR_RGN_X - the memories of exclude DDR_RGN_0 ~ DDR_RGN_7
33 *
34 * DDR_RGN_0 - start address of the RGN0
35 * DDR_RGN_8 - end address of the RGN0
36 * DDR_RGN_1 - start address of the RGN1
37 * DDR_RGN_9 - end address of the RGN1
38 * ...
39 * DDR_RGN_7 - start address of the RGN7
40 * DDR_RGN_15 - end address of the RGN7
41 * DDR_RGN_16 - bit 0 ~ 7 is bitmap for RGN0~7 secure,0: disable, 1: enable
42 * bit 8 is setting for RGNx, the rest of the memory and region
43 * which excludes RGN0~7, 0: disable, 1: enable
44 * bit 9, the global secure configuration via bypass, 0: disable
45 * bypass, 1: enable bypass
46 *
47 * @rgn - the DDR regions 0 ~ 7 which are can be configured.
48 * @st - start address to set as secure
49 * @sz - length of area to set as secure
50 * The @st_mb and @ed_mb indicate the start and end addresses for which to set
51 * the security, and the unit is megabyte. When the st_mb == 0, ed_mb == 0, the
52 * address range 0x0 ~ 0xfffff is secure.
53 *
54 * For example, if we would like to set the range [0, 32MB) is security via
55 * DDR_RGN0, then rgn == 0, st_mb == 0, ed_mb == 31.
56 */
sgrf_ddr_rgn_config(uint32_t rgn,uintptr_t st,size_t sz)57 static void sgrf_ddr_rgn_config(uint32_t rgn,
58 uintptr_t st, size_t sz)
59 {
60 uintptr_t ed = st + sz;
61 uintptr_t st_mb, ed_mb;
62
63 assert(rgn <= 7);
64 assert(st < ed);
65
66 /* check aligned 1MB */
67 assert(st % SIZE_M(1) == 0);
68 assert(ed % SIZE_M(1) == 0);
69
70 st_mb = st / SIZE_M(1);
71 ed_mb = ed / SIZE_M(1);
72
73 /* set ddr region addr start */
74 mmio_write_32(SGRF_BASE + SGRF_DDRRGN_CON0_16(rgn),
75 BITS_WITH_WMASK(st_mb, SGRF_DDR_RGN_0_16_WMSK, 0));
76
77 /* set ddr region addr end */
78 mmio_write_32(SGRF_BASE + SGRF_DDRRGN_CON0_16(rgn + 8),
79 BITS_WITH_WMASK((ed_mb - 1), SGRF_DDR_RGN_0_16_WMSK, 0));
80
81 mmio_write_32(SGRF_BASE + SGRF_DDRRGN_CON0_16(16),
82 BIT_WITH_WMSK(rgn));
83 }
84
secure_watchdog_gate(void)85 void secure_watchdog_gate(void)
86 {
87 /**
88 * Disable CA53 and CM0 wdt pclk
89 * BIT[8]: ca53 wdt pclk, 0: enable 1: disable
90 * BIT[10]: cm0 wdt pclk, 0: enable 1: disable
91 */
92 mmio_write_32(SGRF_BASE + SGRF_SOC_CON(3),
93 BIT_WITH_WMSK(PCLK_WDT_CA53_GATE_SHIFT) |
94 BIT_WITH_WMSK(PCLK_WDT_CM0_GATE_SHIFT));
95 }
96
secure_watchdog_ungate(void)97 __pmusramfunc void secure_watchdog_ungate(void)
98 {
99 /**
100 * Enable CA53 and CM0 wdt pclk
101 * BIT[8]: ca53 wdt pclk, 0: enable 1: disable
102 * BIT[10]: cm0 wdt pclk, 0: enable 1: disable
103 */
104 mmio_write_32(SGRF_BASE + SGRF_SOC_CON(3),
105 WMSK_BIT(PCLK_WDT_CA53_GATE_SHIFT) |
106 WMSK_BIT(PCLK_WDT_CM0_GATE_SHIFT));
107 }
108
sram_secure_timer_init(void)109 __pmusramfunc void sram_secure_timer_init(void)
110 {
111 mmio_write_32(STIMER1_CHN_BASE(5) + TIMER_END_COUNT0, 0xffffffff);
112 mmio_write_32(STIMER1_CHN_BASE(5) + TIMER_END_COUNT1, 0xffffffff);
113
114 mmio_write_32(STIMER1_CHN_BASE(5) + TIMER_INIT_COUNT0, 0x0);
115 mmio_write_32(STIMER1_CHN_BASE(5) + TIMER_INIT_COUNT0, 0x0);
116
117 /* auto reload & enable the timer */
118 mmio_write_32(STIMER1_CHN_BASE(5) + TIMER_CONTROL_REG,
119 TIMER_EN | TIMER_FMODE);
120 }
121
secure_timer_init(void)122 void secure_timer_init(void)
123 {
124 mmio_write_32(STIMER1_CHN_BASE(5) + TIMER_END_COUNT0, 0xffffffff);
125 mmio_write_32(STIMER1_CHN_BASE(5) + TIMER_END_COUNT1, 0xffffffff);
126
127 mmio_write_32(STIMER1_CHN_BASE(5) + TIMER_INIT_COUNT0, 0x0);
128 mmio_write_32(STIMER1_CHN_BASE(5) + TIMER_INIT_COUNT0, 0x0);
129
130 /* auto reload & enable the timer */
131 mmio_write_32(STIMER1_CHN_BASE(5) + TIMER_CONTROL_REG,
132 TIMER_EN | TIMER_FMODE);
133 }
134
secure_sgrf_init(void)135 void secure_sgrf_init(void)
136 {
137 /* security config for master */
138 mmio_write_32(SGRF_BASE + SGRF_SOC_CON(5),
139 REG_SOC_WMSK | SGRF_SOC_ALLMST_NS);
140 mmio_write_32(SGRF_BASE + SGRF_SOC_CON(6),
141 REG_SOC_WMSK | SGRF_SOC_ALLMST_NS);
142 mmio_write_32(SGRF_BASE + SGRF_SOC_CON(7),
143 REG_SOC_WMSK | SGRF_SOC_ALLMST_NS);
144
145 /* security config for slave */
146 mmio_write_32(SGRF_BASE + SGRF_PMU_SLV_CON0_1(0),
147 SGRF_PMU_SLV_S_CFGED |
148 SGRF_PMU_SLV_CRYPTO1_NS);
149 mmio_write_32(SGRF_BASE + SGRF_PMU_SLV_CON0_1(1),
150 SGRF_SLV_S_WMSK | SGRF_PMUSRAM_S);
151 mmio_write_32(SGRF_BASE + SGRF_SLV_SECURE_CON0_4(0),
152 SGRF_SLV_S_WMSK | SGRF_SLV_S_ALL_NS);
153 mmio_write_32(SGRF_BASE + SGRF_SLV_SECURE_CON0_4(1),
154 SGRF_SLV_S_WMSK | SGRF_SLV_S_ALL_NS);
155 mmio_write_32(SGRF_BASE + SGRF_SLV_SECURE_CON0_4(2),
156 SGRF_SLV_S_WMSK | SGRF_SLV_S_ALL_NS);
157 mmio_write_32(SGRF_BASE + SGRF_SLV_SECURE_CON0_4(3),
158 SGRF_SLV_S_WMSK | SGRF_SLV_S_ALL_NS);
159 mmio_write_32(SGRF_BASE + SGRF_SLV_SECURE_CON0_4(4),
160 SGRF_SLV_S_WMSK | SGRF_INTSRAM_S);
161 }
162
secure_sgrf_ddr_rgn_init(void)163 void secure_sgrf_ddr_rgn_init(void)
164 {
165 sgrf_ddr_rgn_config(0, TZRAM_BASE, TZRAM_SIZE);
166 sgrf_ddr_rgn_global_bypass(0);
167 }
168