1 /*
2 * Copyright (c) 2015-2019, ARM Limited and Contributors. All rights reserved.
3 *
4 * SPDX-License-Identifier: BSD-3-Clause
5 */
6
7 #include <assert.h>
8
9 #include <platform_def.h>
10
11 #include <arch_helpers.h>
12 #include <common/bl_common.h>
13 #include <common/debug.h>
14 #include <bl31/interrupt_mgmt.h>
15 #include <drivers/console.h>
16 #include <drivers/rpi3/gpio/rpi3_gpio.h>
17 #include <drivers/ti/uart/uart_16550.h>
18 #include <drivers/arm/pl011.h>
19 #include <lib/xlat_tables/xlat_tables_v2.h>
20
21 #include <rpi_hw.h>
22 #include <rpi_shared.h>
23
24 #define MAP_DEVICE0 MAP_REGION_FLAT(DEVICE0_BASE, \
25 DEVICE0_SIZE, \
26 MT_DEVICE | MT_RW | MT_SECURE)
27
28 #ifdef SHARED_RAM_BASE
29 #define MAP_SHARED_RAM MAP_REGION_FLAT(SHARED_RAM_BASE, \
30 SHARED_RAM_SIZE, \
31 MT_DEVICE | MT_RW | MT_SECURE)
32 #endif
33
34 #ifdef RPI3_PRELOADED_DTB_BASE
35 #define MAP_NS_DTB MAP_REGION_FLAT(RPI3_PRELOADED_DTB_BASE, 0x10000, \
36 MT_MEMORY | MT_RW | MT_NS)
37 #endif
38
39 #define MAP_NS_DRAM0 MAP_REGION_FLAT(NS_DRAM0_BASE, NS_DRAM0_SIZE, \
40 MT_MEMORY | MT_RW | MT_NS)
41
42 #define MAP_FIP MAP_REGION_FLAT(PLAT_RPI3_FIP_BASE, \
43 PLAT_RPI3_FIP_MAX_SIZE, \
44 MT_MEMORY | MT_RO | MT_NS)
45
46 #define MAP_BL32_MEM MAP_REGION_FLAT(BL32_MEM_BASE, BL32_MEM_SIZE, \
47 MT_MEMORY | MT_RW | MT_SECURE)
48
49 #ifdef SPD_opteed
50 #define MAP_OPTEE_PAGEABLE MAP_REGION_FLAT( \
51 RPI3_OPTEE_PAGEABLE_LOAD_BASE, \
52 RPI3_OPTEE_PAGEABLE_LOAD_SIZE, \
53 MT_MEMORY | MT_RW | MT_SECURE)
54 #endif
55
56 /*
57 * Table of regions for various BL stages to map using the MMU.
58 */
59 #ifdef IMAGE_BL1
60 static const mmap_region_t plat_rpi3_mmap[] = {
61 #ifdef MAP_SHARED_RAM
62 MAP_SHARED_RAM,
63 #endif
64 MAP_DEVICE0,
65 MAP_FIP,
66 #ifdef SPD_opteed
67 MAP_OPTEE_PAGEABLE,
68 #endif
69 {0}
70 };
71 #endif
72
73 #ifdef IMAGE_BL2
74 static const mmap_region_t plat_rpi3_mmap[] = {
75 #ifdef MAP_SHARED_RAM
76 MAP_SHARED_RAM,
77 #endif
78 MAP_DEVICE0,
79 MAP_FIP,
80 MAP_NS_DRAM0,
81 #ifdef BL32_BASE
82 MAP_BL32_MEM,
83 #endif
84 {0}
85 };
86 #endif
87
88 #ifdef IMAGE_BL31
89 static const mmap_region_t plat_rpi3_mmap[] = {
90 #ifdef MAP_SHARED_RAM
91 MAP_SHARED_RAM,
92 #endif
93 MAP_DEVICE0,
94 #ifdef RPI3_PRELOADED_DTB_BASE
95 MAP_NS_DTB,
96 #endif
97 #ifdef BL32_BASE
98 MAP_BL32_MEM,
99 #endif
100 {0}
101 };
102 #endif
103
104 /*******************************************************************************
105 * Function that sets up the console
106 ******************************************************************************/
107 static console_t rpi3_console;
108
109
rpi3_use_mini_uart(void)110 static bool rpi3_use_mini_uart(void)
111 {
112 return rpi3_gpio_get_select(14) == RPI3_GPIO_FUNC_ALT5;
113 }
114
rpi3_console_init(void)115 void rpi3_console_init(void)
116 {
117 int console_scope = CONSOLE_FLAG_BOOT;
118 int rc;
119
120 if (RPI3_RUNTIME_UART != -1)
121 console_scope |= CONSOLE_FLAG_RUNTIME;
122
123 rpi3_gpio_init();
124
125 if (rpi3_use_mini_uart())
126 rc = console_16550_register(PLAT_RPI_MINI_UART_BASE,
127 0,
128 PLAT_RPI_UART_BAUDRATE,
129 &rpi3_console);
130 else
131 rc = console_pl011_register(PLAT_RPI_PL011_UART_BASE,
132 PLAT_RPI_PL011_UART_CLOCK,
133 PLAT_RPI_UART_BAUDRATE,
134 &rpi3_console);
135
136 if (rc == 0) {
137 /*
138 * The crash console doesn't use the multi console API, it uses
139 * the core console functions directly. It is safe to call panic
140 * and let it print debug information.
141 */
142 panic();
143 }
144
145 console_set_scope(&rpi3_console, console_scope);
146 }
147
148 /*******************************************************************************
149 * Function that sets up the translation tables.
150 ******************************************************************************/
rpi3_setup_page_tables(uintptr_t total_base,size_t total_size,uintptr_t code_start,uintptr_t code_limit,uintptr_t rodata_start,uintptr_t rodata_limit,uintptr_t coh_start,uintptr_t coh_limit)151 void rpi3_setup_page_tables(uintptr_t total_base, size_t total_size,
152 uintptr_t code_start, uintptr_t code_limit,
153 uintptr_t rodata_start, uintptr_t rodata_limit
154 #if USE_COHERENT_MEM
155 , uintptr_t coh_start, uintptr_t coh_limit
156 #endif
157 )
158 {
159 /*
160 * Map the Trusted SRAM with appropriate memory attributes.
161 * Subsequent mappings will adjust the attributes for specific regions.
162 */
163 VERBOSE("Trusted SRAM seen by this BL image: %p - %p\n",
164 (void *) total_base, (void *) (total_base + total_size));
165 mmap_add_region(total_base, total_base,
166 total_size,
167 MT_MEMORY | MT_RW | MT_SECURE);
168
169 /* Re-map the code section */
170 VERBOSE("Code region: %p - %p\n",
171 (void *) code_start, (void *) code_limit);
172 mmap_add_region(code_start, code_start,
173 code_limit - code_start,
174 MT_CODE | MT_SECURE);
175
176 /* Re-map the read-only data section */
177 VERBOSE("Read-only data region: %p - %p\n",
178 (void *) rodata_start, (void *) rodata_limit);
179 mmap_add_region(rodata_start, rodata_start,
180 rodata_limit - rodata_start,
181 MT_RO_DATA | MT_SECURE);
182
183 #if USE_COHERENT_MEM
184 /* Re-map the coherent memory region */
185 VERBOSE("Coherent region: %p - %p\n",
186 (void *) coh_start, (void *) coh_limit);
187 mmap_add_region(coh_start, coh_start,
188 coh_limit - coh_start,
189 MT_DEVICE | MT_RW | MT_SECURE);
190 #endif
191
192 mmap_add(plat_rpi3_mmap);
193
194 init_xlat_tables();
195 }
196
197 /*******************************************************************************
198 * Gets SPSR for BL32 entry
199 ******************************************************************************/
rpi3_get_spsr_for_bl32_entry(void)200 uint32_t rpi3_get_spsr_for_bl32_entry(void)
201 {
202 /*
203 * The Secure Payload Dispatcher service is responsible for
204 * setting the SPSR prior to entry into the BL32 image.
205 */
206 return 0;
207 }
208
209 /*******************************************************************************
210 * Gets SPSR for BL33 entry
211 ******************************************************************************/
rpi3_get_spsr_for_bl33_entry(void)212 uint32_t rpi3_get_spsr_for_bl33_entry(void)
213 {
214 #if RPI3_BL33_IN_AARCH32
215 INFO("BL33 will boot in Non-secure AArch32 Hypervisor mode\n");
216 return SPSR_MODE32(MODE32_hyp, SPSR_T_ARM, SPSR_E_LITTLE,
217 DISABLE_ALL_EXCEPTIONS);
218 #else
219 return SPSR_64(MODE_EL2, MODE_SP_ELX, DISABLE_ALL_EXCEPTIONS);
220 #endif
221 }
222
plat_get_syscnt_freq2(void)223 unsigned int plat_get_syscnt_freq2(void)
224 {
225 return SYS_COUNTER_FREQ_IN_TICKS;
226 }
227
plat_ic_get_pending_interrupt_type(void)228 uint32_t plat_ic_get_pending_interrupt_type(void)
229 {
230 ERROR("rpi3: Interrupt routed to EL3.\n");
231 return INTR_TYPE_INVAL;
232 }
233
plat_interrupt_type_to_line(uint32_t type,uint32_t security_state)234 uint32_t plat_interrupt_type_to_line(uint32_t type, uint32_t security_state)
235 {
236 assert((type == INTR_TYPE_S_EL1) || (type == INTR_TYPE_EL3) ||
237 (type == INTR_TYPE_NS));
238
239 assert(sec_state_is_valid(security_state));
240
241 /* Non-secure interrupts are signalled on the IRQ line always. */
242 if (type == INTR_TYPE_NS)
243 return __builtin_ctz(SCR_IRQ_BIT);
244
245 /* Secure interrupts are signalled on the FIQ line always. */
246 return __builtin_ctz(SCR_FIQ_BIT);
247 }
248