1 /* 2 * Copyright (c) 2016-2018, ARM Limited and Contributors. All rights reserved. 3 * 4 * SPDX-License-Identifier: BSD-3-Clause 5 */ 6 7 #ifndef RPI_HW_H 8 #define RPI_HW_H 9 10 #include <lib/utils_def.h> 11 12 /* 13 * Peripherals 14 */ 15 16 #define RPI_IO_BASE ULL(0x3F000000) 17 #define RPI_IO_SIZE ULL(0x01000000) 18 19 /* 20 * ARM <-> VideoCore mailboxes 21 */ 22 #define RPI3_MBOX_OFFSET ULL(0x0000B880) 23 #define RPI3_MBOX_BASE (RPI_IO_BASE + RPI3_MBOX_OFFSET) 24 /* VideoCore -> ARM */ 25 #define RPI3_MBOX0_READ_OFFSET ULL(0x00000000) 26 #define RPI3_MBOX0_PEEK_OFFSET ULL(0x00000010) 27 #define RPI3_MBOX0_SENDER_OFFSET ULL(0x00000014) 28 #define RPI3_MBOX0_STATUS_OFFSET ULL(0x00000018) 29 #define RPI3_MBOX0_CONFIG_OFFSET ULL(0x0000001C) 30 /* ARM -> VideoCore */ 31 #define RPI3_MBOX1_WRITE_OFFSET ULL(0x00000020) 32 #define RPI3_MBOX1_PEEK_OFFSET ULL(0x00000030) 33 #define RPI3_MBOX1_SENDER_OFFSET ULL(0x00000034) 34 #define RPI3_MBOX1_STATUS_OFFSET ULL(0x00000038) 35 #define RPI3_MBOX1_CONFIG_OFFSET ULL(0x0000003C) 36 /* Mailbox status constants */ 37 #define RPI3_MBOX_STATUS_FULL_MASK U(0x80000000) /* Set if full */ 38 #define RPI3_MBOX_STATUS_EMPTY_MASK U(0x40000000) /* Set if empty */ 39 40 /* 41 * Power management, reset controller, watchdog. 42 */ 43 #define RPI3_IO_PM_OFFSET ULL(0x00100000) 44 #define RPI3_PM_BASE (RPI_IO_BASE + RPI3_IO_PM_OFFSET) 45 /* Registers on top of RPI3_PM_BASE. */ 46 #define RPI3_PM_RSTC_OFFSET ULL(0x0000001C) 47 #define RPI3_PM_RSTS_OFFSET ULL(0x00000020) 48 #define RPI3_PM_WDOG_OFFSET ULL(0x00000024) 49 /* Watchdog constants */ 50 #define RPI3_PM_PASSWORD U(0x5A000000) 51 #define RPI3_PM_RSTC_WRCFG_MASK U(0x00000030) 52 #define RPI3_PM_RSTC_WRCFG_FULL_RESET U(0x00000020) 53 /* 54 * The RSTS register is used by the VideoCore firmware when booting the 55 * Raspberry Pi to know which partition to boot from. The partition value is 56 * formed by bits 0, 2, 4, 6, 8 and 10. Partition 63 is used by said firmware 57 * to indicate halt. 58 */ 59 #define RPI3_PM_RSTS_WRCFG_HALT U(0x00000555) 60 61 /* 62 * Hardware random number generator. 63 */ 64 #define RPI3_IO_RNG_OFFSET ULL(0x00104000) 65 #define RPI3_RNG_BASE (RPI_IO_BASE + RPI3_IO_RNG_OFFSET) 66 #define RPI3_RNG_CTRL_OFFSET ULL(0x00000000) 67 #define RPI3_RNG_STATUS_OFFSET ULL(0x00000004) 68 #define RPI3_RNG_DATA_OFFSET ULL(0x00000008) 69 #define RPI3_RNG_INT_MASK_OFFSET ULL(0x00000010) 70 /* Enable/disable RNG */ 71 #define RPI3_RNG_CTRL_ENABLE U(0x1) 72 #define RPI3_RNG_CTRL_DISABLE U(0x0) 73 /* Number of currently available words */ 74 #define RPI3_RNG_STATUS_NUM_WORDS_SHIFT U(24) 75 #define RPI3_RNG_STATUS_NUM_WORDS_MASK U(0xFF) 76 /* Value to mask interrupts caused by the RNG */ 77 #define RPI3_RNG_INT_MASK_DISABLE U(0x1) 78 79 /* 80 * Serial ports: 81 * 'Mini UART' in the BCM docucmentation is the 8250 compatible UART. 82 * There is also a PL011 UART, multiplexed to the same pins. 83 */ 84 #define RPI3_IO_MINI_UART_OFFSET ULL(0x00215040) 85 #define RPI3_MINI_UART_BASE (RPI_IO_BASE + RPI3_IO_MINI_UART_OFFSET) 86 #define RPI3_IO_PL011_UART_OFFSET ULL(0x00201000) 87 #define RPI3_PL011_UART_BASE (RPI_IO_BASE + RPI3_IO_PL011_UART_OFFSET) 88 #define RPI3_PL011_UART_CLOCK ULL(48000000) 89 90 /* 91 * GPIO controller 92 */ 93 #define RPI3_IO_GPIO_OFFSET ULL(0x00200000) 94 #define RPI3_GPIO_BASE (RPI_IO_BASE + RPI3_IO_GPIO_OFFSET) 95 96 /* 97 * SDHost controller 98 */ 99 #define RPI3_IO_SDHOST_OFFSET ULL(0x00202000) 100 #define RPI3_SDHOST_BASE (RPI_IO_BASE + RPI3_IO_SDHOST_OFFSET) 101 102 /* 103 * Local interrupt controller 104 */ 105 #define RPI3_INTC_BASE_ADDRESS ULL(0x40000000) 106 /* Registers on top of RPI3_INTC_BASE_ADDRESS */ 107 #define RPI3_INTC_CONTROL_OFFSET ULL(0x00000000) 108 #define RPI3_INTC_PRESCALER_OFFSET ULL(0x00000008) 109 #define RPI3_INTC_MBOX_CONTROL_OFFSET ULL(0x00000050) 110 #define RPI3_INTC_MBOX_CONTROL_SLOT3_FIQ ULL(0x00000080) 111 #define RPI3_INTC_PENDING_FIQ_OFFSET ULL(0x00000070) 112 #define RPI3_INTC_PENDING_FIQ_MBOX3 ULL(0x00000080) 113 114 #endif /* RPI_HW_H */ 115