1 /*
2  * Copyright (c) 2015-2019, ARM Limited and Contributors. All rights reserved.
3  *
4  * SPDX-License-Identifier: BSD-3-Clause
5  */
6 
7 #include <assert.h>
8 
9 #include <platform_def.h>
10 
11 #include <arch_helpers.h>
12 #include <common/bl_common.h>
13 #include <common/debug.h>
14 #include <common/desc_image_load.h>
15 #include <lib/optee_utils.h>
16 #include <lib/xlat_tables/xlat_mmu_helpers.h>
17 #include <lib/xlat_tables/xlat_tables_defs.h>
18 #include <drivers/generic_delay_timer.h>
19 #include <drivers/rpi3/gpio/rpi3_gpio.h>
20 #include <drivers/rpi3/sdhost/rpi3_sdhost.h>
21 
22 #include <rpi_shared.h>
23 
24 /* Data structure which holds the extents of the trusted SRAM for BL2 */
25 static meminfo_t bl2_tzram_layout __aligned(CACHE_WRITEBACK_GRANULE);
26 
27 /* Data structure which holds the MMC info */
28 static struct mmc_device_info mmc_info;
29 
rpi3_sdhost_setup(void)30 static void rpi3_sdhost_setup(void)
31 {
32 	struct rpi3_sdhost_params params;
33 
34 	memset(&params, 0, sizeof(struct rpi3_sdhost_params));
35 	params.reg_base = RPI3_SDHOST_BASE;
36 	params.bus_width = MMC_BUS_WIDTH_1;
37 	params.clk_rate = 50000000;
38 	mmc_info.mmc_dev_type = MMC_IS_SD_HC;
39 	rpi3_sdhost_init(&params, &mmc_info);
40 }
41 
42 /*******************************************************************************
43  * BL1 has passed the extents of the trusted SRAM that should be visible to BL2
44  * in x0. This memory layout is sitting at the base of the free trusted SRAM.
45  * Copy it to a safe location before its reclaimed by later BL2 functionality.
46  ******************************************************************************/
47 
bl2_early_platform_setup2(u_register_t arg0,u_register_t arg1,u_register_t arg2,u_register_t arg3)48 void bl2_early_platform_setup2(u_register_t arg0, u_register_t arg1,
49 			       u_register_t arg2, u_register_t arg3)
50 {
51 	meminfo_t *mem_layout = (meminfo_t *) arg1;
52 
53 	/* Initialize the console to provide early debug support */
54 	rpi3_console_init();
55 
56 	/* Enable arch timer */
57 	generic_delay_timer_init();
58 
59 	/* Setup GPIO driver */
60 	rpi3_gpio_init();
61 
62 	/* Setup the BL2 memory layout */
63 	bl2_tzram_layout = *mem_layout;
64 
65 	/* Setup SDHost driver */
66 	rpi3_sdhost_setup();
67 
68 	plat_rpi3_io_setup();
69 }
70 
bl2_platform_setup(void)71 void bl2_platform_setup(void)
72 {
73 	/*
74 	 * This is where a TrustZone address space controller and other
75 	 * security related peripherals would be configured.
76 	 */
77 }
78 
79 /*******************************************************************************
80  * Perform the very early platform specific architectural setup here.
81  ******************************************************************************/
bl2_plat_arch_setup(void)82 void bl2_plat_arch_setup(void)
83 {
84 	rpi3_setup_page_tables(bl2_tzram_layout.total_base,
85 			       bl2_tzram_layout.total_size,
86 			       BL_CODE_BASE, BL_CODE_END,
87 			       BL_RO_DATA_BASE, BL_RO_DATA_END
88 #if USE_COHERENT_MEM
89 			       , BL_COHERENT_RAM_BASE, BL_COHERENT_RAM_END
90 #endif
91 			      );
92 
93 	enable_mmu_el1(0);
94 }
95 
96 /*******************************************************************************
97  * This function can be used by the platforms to update/use image
98  * information for given `image_id`.
99  ******************************************************************************/
bl2_plat_handle_post_image_load(unsigned int image_id)100 int bl2_plat_handle_post_image_load(unsigned int image_id)
101 {
102 	int err = 0;
103 	bl_mem_params_node_t *bl_mem_params = get_bl_mem_params_node(image_id);
104 #ifdef SPD_opteed
105 	bl_mem_params_node_t *pager_mem_params = NULL;
106 	bl_mem_params_node_t *paged_mem_params = NULL;
107 #endif
108 
109 	assert(bl_mem_params != NULL);
110 
111 	switch (image_id) {
112 	case BL32_IMAGE_ID:
113 #ifdef SPD_opteed
114 		pager_mem_params = get_bl_mem_params_node(BL32_EXTRA1_IMAGE_ID);
115 		assert(pager_mem_params);
116 
117 		paged_mem_params = get_bl_mem_params_node(BL32_EXTRA2_IMAGE_ID);
118 		assert(paged_mem_params);
119 
120 		err = parse_optee_header(&bl_mem_params->ep_info,
121 				&pager_mem_params->image_info,
122 				&paged_mem_params->image_info);
123 		if (err != 0)
124 			WARN("OPTEE header parse error.\n");
125 #endif
126 		bl_mem_params->ep_info.spsr = rpi3_get_spsr_for_bl32_entry();
127 		break;
128 
129 	case BL33_IMAGE_ID:
130 		/* BL33 expects to receive the primary CPU MPID (through r0) */
131 		bl_mem_params->ep_info.args.arg0 = 0xffff & read_mpidr();
132 		bl_mem_params->ep_info.spsr = rpi3_get_spsr_for_bl33_entry();
133 
134 		/* Shutting down the SDHost driver to let BL33 drives SDHost.*/
135 		rpi3_sdhost_stop();
136 		break;
137 
138 	default:
139 		/* Do nothing in default case */
140 		break;
141 	}
142 
143 	return err;
144 }
145