1 /*
2 * Copyright (c) 2015-2021, ARM Limited and Contributors. All rights reserved.
3 *
4 * SPDX-License-Identifier: BSD-3-Clause
5 */
6
7 #include <assert.h>
8 #include <string.h>
9
10 #include <platform_def.h>
11
12 #include <arch_helpers.h>
13 #include <common/bl_common.h>
14 #include <common/debug.h>
15 #include <context.h>
16 #include <drivers/arm/gicv2.h>
17 #include <drivers/arm/tzc400.h>
18 #include <drivers/generic_delay_timer.h>
19 #include <drivers/st/bsec.h>
20 #include <drivers/st/etzpc.h>
21 #include <drivers/st/stm32_console.h>
22 #include <drivers/st/stm32_gpio.h>
23 #include <drivers/st/stm32_iwdg.h>
24 #include <drivers/st/stm32mp1_clk.h>
25 #include <dt-bindings/clock/stm32mp1-clks.h>
26 #include <lib/el3_runtime/context_mgmt.h>
27 #include <lib/mmio.h>
28 #include <lib/xlat_tables/xlat_tables_v2.h>
29 #include <plat/common/platform.h>
30
31 #include <platform_sp_min.h>
32
33 /******************************************************************************
34 * Placeholder variables for copying the arguments that have been passed to
35 * BL32 from BL2.
36 ******************************************************************************/
37 static entry_point_info_t bl33_image_ep_info;
38
39 static console_t console;
40
41 /*******************************************************************************
42 * Interrupt handler for FIQ (secure IRQ)
43 ******************************************************************************/
sp_min_plat_fiq_handler(uint32_t id)44 void sp_min_plat_fiq_handler(uint32_t id)
45 {
46 switch (id & INT_ID_MASK) {
47 case STM32MP1_IRQ_TZC400:
48 tzc400_init(STM32MP1_TZC_BASE);
49 (void)tzc400_it_handler();
50 panic();
51 break;
52 case STM32MP1_IRQ_AXIERRIRQ:
53 ERROR("STM32MP1_IRQ_AXIERRIRQ generated\n");
54 panic();
55 break;
56 default:
57 ERROR("SECURE IT handler not define for it : %u", id);
58 break;
59 }
60 }
61
62 /*******************************************************************************
63 * Return a pointer to the 'entry_point_info' structure of the next image for
64 * the security state specified. BL33 corresponds to the non-secure image type
65 * while BL32 corresponds to the secure image type. A NULL pointer is returned
66 * if the image does not exist.
67 ******************************************************************************/
sp_min_plat_get_bl33_ep_info(void)68 entry_point_info_t *sp_min_plat_get_bl33_ep_info(void)
69 {
70 entry_point_info_t *next_image_info;
71
72 next_image_info = &bl33_image_ep_info;
73
74 if (next_image_info->pc == 0U) {
75 return NULL;
76 }
77
78 return next_image_info;
79 }
80
81 CASSERT((STM32MP_SEC_SYSRAM_BASE == STM32MP_SYSRAM_BASE) &&
82 ((STM32MP_SEC_SYSRAM_BASE + STM32MP_SEC_SYSRAM_SIZE) <=
83 (STM32MP_SYSRAM_BASE + STM32MP_SYSRAM_SIZE)),
84 assert_secure_sysram_fits_at_begining_of_sysram);
85
86 #ifdef STM32MP_NS_SYSRAM_BASE
87 CASSERT((STM32MP_NS_SYSRAM_BASE >= STM32MP_SEC_SYSRAM_BASE) &&
88 ((STM32MP_NS_SYSRAM_BASE + STM32MP_NS_SYSRAM_SIZE) ==
89 (STM32MP_SYSRAM_BASE + STM32MP_SYSRAM_SIZE)),
90 assert_non_secure_sysram_fits_at_end_of_sysram);
91
92 CASSERT((STM32MP_NS_SYSRAM_BASE & (PAGE_SIZE_4KB - U(1))) == 0U,
93 assert_non_secure_sysram_base_is_4kbyte_aligned);
94
95 #define TZMA1_SECURE_RANGE \
96 (((STM32MP_NS_SYSRAM_BASE - STM32MP_SYSRAM_BASE) >> FOUR_KB_SHIFT) - 1U)
97 #else
98 #define TZMA1_SECURE_RANGE STM32MP1_ETZPC_TZMA_ALL_SECURE
99 #endif /* STM32MP_NS_SYSRAM_BASE */
100 #define TZMA0_SECURE_RANGE STM32MP1_ETZPC_TZMA_ALL_SECURE
101
stm32mp1_etzpc_early_setup(void)102 static void stm32mp1_etzpc_early_setup(void)
103 {
104 if (etzpc_init() != 0) {
105 panic();
106 }
107
108 etzpc_configure_tzma(STM32MP1_ETZPC_TZMA_ROM, TZMA0_SECURE_RANGE);
109 etzpc_configure_tzma(STM32MP1_ETZPC_TZMA_SYSRAM, TZMA1_SECURE_RANGE);
110 }
111
112 /*******************************************************************************
113 * Perform any BL32 specific platform actions.
114 ******************************************************************************/
sp_min_early_platform_setup2(u_register_t arg0,u_register_t arg1,u_register_t arg2,u_register_t arg3)115 void sp_min_early_platform_setup2(u_register_t arg0, u_register_t arg1,
116 u_register_t arg2, u_register_t arg3)
117 {
118 struct dt_node_info dt_uart_info;
119 int result;
120 bl_params_t *params_from_bl2 = (bl_params_t *)arg0;
121 #if STM32MP_USE_STM32IMAGE
122 uintptr_t dt_addr = STM32MP_DTB_BASE;
123 #else
124 uintptr_t dt_addr = arg1;
125 #endif
126
127 /* Imprecise aborts can be masked in NonSecure */
128 write_scr(read_scr() | SCR_AW_BIT);
129
130 mmap_add_region(BL_CODE_BASE, BL_CODE_BASE,
131 BL_CODE_END - BL_CODE_BASE,
132 MT_CODE | MT_SECURE);
133
134 configure_mmu();
135
136 assert(params_from_bl2 != NULL);
137 assert(params_from_bl2->h.type == PARAM_BL_PARAMS);
138 assert(params_from_bl2->h.version >= VERSION_2);
139
140 bl_params_node_t *bl_params = params_from_bl2->head;
141
142 /*
143 * Copy BL33 entry point information.
144 * They are stored in Secure RAM, in BL2's address space.
145 */
146 while (bl_params != NULL) {
147 if (bl_params->image_id == BL33_IMAGE_ID) {
148 bl33_image_ep_info = *bl_params->ep_info;
149 /*
150 * Check if hw_configuration is given to BL32 and
151 * share it to BL33.
152 */
153 if (arg2 != 0U) {
154 bl33_image_ep_info.args.arg0 = 0U;
155 bl33_image_ep_info.args.arg1 = 0U;
156 bl33_image_ep_info.args.arg2 = arg2;
157 }
158
159 break;
160 }
161
162 bl_params = bl_params->next_params_info;
163 }
164
165 if (dt_open_and_check(dt_addr) < 0) {
166 panic();
167 }
168
169 if (bsec_probe() != 0) {
170 panic();
171 }
172
173 if (stm32mp1_clk_probe() < 0) {
174 panic();
175 }
176
177 result = dt_get_stdout_uart_info(&dt_uart_info);
178
179 if ((result > 0) && (dt_uart_info.status != 0U)) {
180 unsigned int console_flags;
181
182 if (console_stm32_register(dt_uart_info.base, 0,
183 STM32MP_UART_BAUDRATE, &console) ==
184 0) {
185 panic();
186 }
187
188 console_flags = CONSOLE_FLAG_BOOT | CONSOLE_FLAG_CRASH |
189 CONSOLE_FLAG_TRANSLATE_CRLF;
190 #ifdef DEBUG
191 console_flags |= CONSOLE_FLAG_RUNTIME;
192 #endif
193 console_set_scope(&console, console_flags);
194 }
195
196 stm32mp1_etzpc_early_setup();
197 }
198
199 /*******************************************************************************
200 * Initialize the MMU, security and the GIC.
201 ******************************************************************************/
sp_min_platform_setup(void)202 void sp_min_platform_setup(void)
203 {
204 generic_delay_timer_init();
205
206 stm32mp1_gic_init();
207
208 if (stm32_iwdg_init() < 0) {
209 panic();
210 }
211
212 stm32mp_lock_periph_registering();
213
214 stm32mp1_init_scmi_server();
215 }
216
sp_min_plat_arch_setup(void)217 void sp_min_plat_arch_setup(void)
218 {
219 }
220