1 /* 2 * Copyright (C) 2021, STMicroelectronics - All Rights Reserved 3 * 4 * SPDX-License-Identifier: BSD-3-Clause 5 */ 6 7 #ifndef STM32MP1_STM32IMAGE_DEF_H 8 #define STM32MP1_STM32IMAGE_DEF_H 9 10 #ifdef AARCH32_SP_OPTEE 11 #define STM32MP_DDR_S_SIZE U(0x01E00000) /* 30 MB */ 12 #define STM32MP_DDR_SHMEM_SIZE U(0x00200000) /* 2 MB */ 13 #else 14 #define STM32MP_DDR_S_SIZE U(0) 15 #define STM32MP_DDR_SHMEM_SIZE U(0) 16 #endif 17 18 #define STM32MP_BL2_SIZE U(0x0001C000) /* 112 KB for BL2 */ 19 #define STM32MP_DTB_SIZE U(0x00006000) /* 24 KB for DTB */ 20 21 #ifdef AARCH32_SP_OPTEE 22 #define STM32MP_BL32_BASE STM32MP_SEC_SYSRAM_BASE 23 24 #define STM32MP_BL2_BASE (STM32MP_SEC_SYSRAM_BASE + \ 25 STM32MP_SEC_SYSRAM_SIZE - \ 26 STM32MP_BL2_SIZE) 27 28 /* OP-TEE loads from SYSRAM base to BL2 DTB start address */ 29 #define STM32MP_OPTEE_BASE STM32MP_BL32_BASE 30 #define STM32MP_OPTEE_SIZE (STM32MP_SEC_SYSRAM_SIZE - \ 31 STM32MP_BL2_SIZE - STM32MP_DTB_SIZE) 32 #define STM32MP_BL32_SIZE STM32MP_OPTEE_SIZE 33 #else /* AARCH32_SP_OPTEE */ 34 #define STM32MP_BL32_SIZE U(0x00019000) /* 96 KB for BL32 */ 35 36 #define STM32MP_BL32_BASE (STM32MP_SEC_SYSRAM_BASE + \ 37 STM32MP_SEC_SYSRAM_SIZE - \ 38 STM32MP_BL32_SIZE) 39 40 #define STM32MP_BL2_BASE (STM32MP_BL32_BASE - \ 41 STM32MP_BL2_SIZE) 42 #endif /* AARCH32_SP_OPTEE */ 43 44 /* DTB initialization value */ 45 #define STM32MP_DTB_BASE (STM32MP_BL2_BASE - \ 46 STM32MP_DTB_SIZE) 47 48 /* 49 * MAX_MMAP_REGIONS is usually: 50 * BL stm32mp1_mmap size + mmap regions in *_plat_arch_setup 51 */ 52 #if defined(IMAGE_BL32) 53 #define MAX_MMAP_REGIONS 6 54 #endif 55 56 /******************************************************************************* 57 * STM32MP1 RAW partition offset for MTD devices 58 ******************************************************************************/ 59 #define STM32MP_NOR_BL33_OFFSET U(0x00080000) 60 #ifdef AARCH32_SP_OPTEE 61 #define STM32MP_NOR_TEEH_OFFSET U(0x00280000) 62 #define STM32MP_NOR_TEED_OFFSET U(0x002C0000) 63 #define STM32MP_NOR_TEEX_OFFSET U(0x00300000) 64 #endif 65 66 #define STM32MP_NAND_BL33_OFFSET U(0x00200000) 67 #ifdef AARCH32_SP_OPTEE 68 #define STM32MP_NAND_TEEH_OFFSET U(0x00600000) 69 #define STM32MP_NAND_TEED_OFFSET U(0x00680000) 70 #define STM32MP_NAND_TEEX_OFFSET U(0x00700000) 71 #endif 72 73 #endif /* STM32MP1_STM32IMAGE_DEF_H */ 74