1 /* 2 * Copyright (c) 2017-2018, ARM Limited and Contributors. All rights reserved. 3 * 4 * SPDX-License-Identifier: BSD-3-Clause 5 */ 6 7 #ifndef PLATFORM_DEF_H 8 #define PLATFORM_DEF_H 9 10 #include <arch.h> 11 #include <plat/common/common_def.h> 12 13 #include <board_def.h> 14 15 /******************************************************************************* 16 * Generic platform constants 17 ******************************************************************************/ 18 19 /* Size of cacheable stack */ 20 #if IMAGE_BL31 21 #define PLATFORM_STACK_SIZE 0x800 22 #else 23 #define PLATFORM_STACK_SIZE 0x1000 24 #endif 25 26 #define PLATFORM_SYSTEM_COUNT 1 27 #define PLATFORM_CORE_COUNT (K3_CLUSTER0_CORE_COUNT + \ 28 K3_CLUSTER1_CORE_COUNT + \ 29 K3_CLUSTER2_CORE_COUNT + \ 30 K3_CLUSTER3_CORE_COUNT) 31 32 #define PLATFORM_CLUSTER_COUNT ((K3_CLUSTER0_CORE_COUNT != 0) + \ 33 (K3_CLUSTER1_CORE_COUNT != 0) + \ 34 (K3_CLUSTER2_CORE_COUNT != 0) + \ 35 (K3_CLUSTER3_CORE_COUNT != 0)) 36 37 #define PLAT_NUM_PWR_DOMAINS (PLATFORM_SYSTEM_COUNT + \ 38 PLATFORM_CLUSTER_COUNT + \ 39 PLATFORM_CORE_COUNT) 40 #define PLAT_MAX_PWR_LVL MPIDR_AFFLVL2 41 42 /******************************************************************************* 43 * Memory layout constants 44 ******************************************************************************/ 45 46 /* 47 * ARM-TF lives in SRAM, partition it here 48 * 49 * BL3-1 specific defines. 50 * 51 * Put BL3-1 at the base of the Trusted SRAM. 52 */ 53 #define BL31_BASE SEC_SRAM_BASE 54 #define BL31_SIZE SEC_SRAM_SIZE 55 #define BL31_LIMIT (BL31_BASE + BL31_SIZE) 56 57 /* 58 * Defines the maximum number of translation tables that are allocated by the 59 * translation table library code. To minimize the amount of runtime memory 60 * used, choose the smallest value needed to map the required virtual addresses 61 * for each BL stage. 62 */ 63 #if USE_COHERENT_MEM 64 #define MAX_XLAT_TABLES 10 65 #else 66 #define MAX_XLAT_TABLES 9 67 #endif 68 69 /* 70 * Defines the maximum number of regions that are allocated by the translation 71 * table library code. A region consists of physical base address, virtual base 72 * address, size and attributes (Device/Memory, RO/RW, Secure/Non-Secure), as 73 * defined in the `mmap_region_t` structure. The platform defines the regions 74 * that should be mapped. Then, the translation table library will create the 75 * corresponding tables and descriptors at runtime. To minimize the amount of 76 * runtime memory used, choose the smallest value needed to register the 77 * required regions for each BL stage. 78 */ 79 #define MAX_MMAP_REGIONS 11 80 81 /* 82 * Defines the total size of the address space in bytes. For example, for a 32 83 * bit address space, this value should be `(1ull << 32)`. 84 */ 85 #define PLAT_PHY_ADDR_SPACE_SIZE (1ull << 32) 86 #define PLAT_VIRT_ADDR_SPACE_SIZE (1ull << 32) 87 88 /* 89 * Some data must be aligned on the biggest cache line size in the platform. 90 * This is known only to the platform as it might have a combination of 91 * integrated and external caches. 92 */ 93 #define CACHE_WRITEBACK_SHIFT 6 94 #define CACHE_WRITEBACK_GRANULE (1 << CACHE_WRITEBACK_SHIFT) 95 96 /* Platform default console definitions */ 97 #ifndef K3_USART_BASE 98 #define K3_USART_BASE (0x02800000 + 0x10000 * K3_USART) 99 #endif 100 101 /* USART has a default size for address space */ 102 #define K3_USART_SIZE 0x1000 103 104 #ifndef K3_USART_CLK_SPEED 105 #define K3_USART_CLK_SPEED 48000000 106 #endif 107 108 /* Crash console defaults */ 109 #define CRASH_CONSOLE_BASE K3_USART_BASE 110 #define CRASH_CONSOLE_CLK K3_USART_CLK_SPEED 111 #define CRASH_CONSOLE_BAUD_RATE K3_USART_BAUD 112 113 /* Timer frequency */ 114 #ifndef SYS_COUNTER_FREQ_IN_TICKS 115 #define SYS_COUNTER_FREQ_IN_TICKS 200000000 116 #endif 117 118 /* Interrupt numbers */ 119 #define ARM_IRQ_SEC_PHY_TIMER 29 120 121 #define ARM_IRQ_SEC_SGI_0 8 122 #define ARM_IRQ_SEC_SGI_1 9 123 #define ARM_IRQ_SEC_SGI_2 10 124 #define ARM_IRQ_SEC_SGI_3 11 125 #define ARM_IRQ_SEC_SGI_4 12 126 #define ARM_IRQ_SEC_SGI_5 13 127 #define ARM_IRQ_SEC_SGI_6 14 128 #define ARM_IRQ_SEC_SGI_7 15 129 130 /* 131 * Define properties of Group 1 Secure and Group 0 interrupts as per GICv3 132 * terminology. On a GICv2 system or mode, the lists will be merged and treated 133 * as Group 0 interrupts. 134 */ 135 #define PLAT_ARM_G1S_IRQ_PROPS(grp) \ 136 INTR_PROP_DESC(ARM_IRQ_SEC_PHY_TIMER, GIC_HIGHEST_SEC_PRIORITY, grp, \ 137 GIC_INTR_CFG_LEVEL), \ 138 INTR_PROP_DESC(ARM_IRQ_SEC_SGI_1, GIC_HIGHEST_SEC_PRIORITY, grp, \ 139 GIC_INTR_CFG_EDGE), \ 140 INTR_PROP_DESC(ARM_IRQ_SEC_SGI_2, GIC_HIGHEST_SEC_PRIORITY, grp, \ 141 GIC_INTR_CFG_EDGE), \ 142 INTR_PROP_DESC(ARM_IRQ_SEC_SGI_3, GIC_HIGHEST_SEC_PRIORITY, grp, \ 143 GIC_INTR_CFG_EDGE), \ 144 INTR_PROP_DESC(ARM_IRQ_SEC_SGI_4, GIC_HIGHEST_SEC_PRIORITY, grp, \ 145 GIC_INTR_CFG_EDGE), \ 146 INTR_PROP_DESC(ARM_IRQ_SEC_SGI_5, GIC_HIGHEST_SEC_PRIORITY, grp, \ 147 GIC_INTR_CFG_EDGE), \ 148 INTR_PROP_DESC(ARM_IRQ_SEC_SGI_7, GIC_HIGHEST_SEC_PRIORITY, grp, \ 149 GIC_INTR_CFG_EDGE) 150 151 #define PLAT_ARM_G0_IRQ_PROPS(grp) \ 152 INTR_PROP_DESC(ARM_IRQ_SEC_SGI_0, GIC_HIGHEST_SEC_PRIORITY, grp, \ 153 GIC_INTR_CFG_EDGE), \ 154 INTR_PROP_DESC(ARM_IRQ_SEC_SGI_6, GIC_HIGHEST_SEC_PRIORITY, grp, \ 155 GIC_INTR_CFG_EDGE) 156 157 158 #define K3_GTC_BASE 0x00A90000 159 /* We just need 20 byte offset, but simpler to just remap the 64K page in */ 160 #define K3_GTC_SIZE 0x10000 161 #define K3_GTC_CNTCR_OFFSET 0x00 162 #define K3_GTC_CNTCR_EN_MASK 0x01 163 #define K3_GTC_CNTCR_HDBG_MASK 0x02 164 #define K3_GTC_CNTFID0_OFFSET 0x20 165 166 #define K3_GIC_BASE 0x01800000 167 #define K3_GIC_SIZE 0x200000 168 169 #if !K3_SEC_PROXY_LITE 170 #define SEC_PROXY_DATA_BASE 0x32C00000 171 #define SEC_PROXY_DATA_SIZE 0x80000 172 #define SEC_PROXY_SCFG_BASE 0x32800000 173 #define SEC_PROXY_SCFG_SIZE 0x80000 174 #define SEC_PROXY_RT_BASE 0x32400000 175 #define SEC_PROXY_RT_SIZE 0x80000 176 #else 177 #define SEC_PROXY_DATA_BASE 0x4D000000 178 #define SEC_PROXY_DATA_SIZE 0x80000 179 #define SEC_PROXY_SCFG_BASE 0x4A400000 180 #define SEC_PROXY_SCFG_SIZE 0x80000 181 #define SEC_PROXY_RT_BASE 0x4A600000 182 #define SEC_PROXY_RT_SIZE 0x80000 183 #endif /* K3_SEC_PROXY_LITE */ 184 185 #define SEC_PROXY_TIMEOUT_US 1000000 186 #define SEC_PROXY_MAX_MESSAGE_SIZE 56 187 188 #define TI_SCI_HOST_ID 10 189 #define TI_SCI_MAX_MESSAGE_SIZE 52 190 191 #endif /* PLATFORM_DEF_H */ 192