1 /*
2 * Copyright (c) 2018-2021, ARM Limited and Contributors. All rights reserved.
3 *
4 * SPDX-License-Identifier: BSD-3-Clause
5 */
6
7 #include <assert.h>
8 #include <errno.h>
9 #include <plat_arm.h>
10 #include <plat_private.h>
11 #include <bl31/bl31.h>
12 #include <common/bl_common.h>
13 #include <common/debug.h>
14 #include <drivers/arm/dcc.h>
15 #include <drivers/arm/pl011.h>
16 #include <drivers/console.h>
17 #include <lib/mmio.h>
18 #include <lib/xlat_tables/xlat_tables.h>
19 #include <plat/common/platform.h>
20 #include <versal_def.h>
21 #include <plat_private.h>
22 #include <plat_startup.h>
23
24 static entry_point_info_t bl32_image_ep_info;
25 static entry_point_info_t bl33_image_ep_info;
26
27 /*
28 * Return a pointer to the 'entry_point_info' structure of the next image for
29 * the security state specified. BL33 corresponds to the non-secure image type
30 * while BL32 corresponds to the secure image type. A NULL pointer is returned
31 * if the image does not exist.
32 */
bl31_plat_get_next_image_ep_info(uint32_t type)33 entry_point_info_t *bl31_plat_get_next_image_ep_info(uint32_t type)
34 {
35 assert(sec_state_is_valid(type));
36
37 if (type == NON_SECURE) {
38 return &bl33_image_ep_info;
39 }
40
41 return &bl32_image_ep_info;
42 }
43
44 /*
45 * Set the build time defaults,if we can't find any config data.
46 */
bl31_set_default_config(void)47 static inline void bl31_set_default_config(void)
48 {
49 bl32_image_ep_info.pc = BL32_BASE;
50 bl32_image_ep_info.spsr = arm_get_spsr_for_bl32_entry();
51 bl33_image_ep_info.pc = plat_get_ns_image_entrypoint();
52 bl33_image_ep_info.spsr = SPSR_64(MODE_EL2, MODE_SP_ELX,
53 DISABLE_ALL_EXCEPTIONS);
54 }
55
56 /*
57 * Perform any BL31 specific platform actions. Here is an opportunity to copy
58 * parameters passed by the calling EL (S-EL1 in BL2 & S-EL3 in BL1) before they
59 * are lost (potentially). This needs to be done before the MMU is initialized
60 * so that the memory layout can be used while creating page tables.
61 */
bl31_early_platform_setup2(u_register_t arg0,u_register_t arg1,u_register_t arg2,u_register_t arg3)62 void bl31_early_platform_setup2(u_register_t arg0, u_register_t arg1,
63 u_register_t arg2, u_register_t arg3)
64 {
65 uint64_t atf_handoff_addr;
66
67 if (VERSAL_CONSOLE_IS(pl011)) {
68 static console_t versal_runtime_console;
69 /* Initialize the console to provide early debug support */
70 int rc = console_pl011_register(VERSAL_UART_BASE,
71 VERSAL_UART_CLOCK,
72 VERSAL_UART_BAUDRATE,
73 &versal_runtime_console);
74 if (rc == 0) {
75 panic();
76 }
77
78 console_set_scope(&versal_runtime_console, CONSOLE_FLAG_BOOT |
79 CONSOLE_FLAG_RUNTIME);
80 } else if (VERSAL_CONSOLE_IS(dcc)) {
81 /* Initialize the dcc console for debug */
82 int rc = console_dcc_register();
83 if (rc == 0) {
84 panic();
85 }
86 }
87 /* Initialize the platform config for future decision making */
88 versal_config_setup();
89 /* There are no parameters from BL2 if BL31 is a reset vector */
90 assert(arg0 == 0U);
91 assert(arg1 == 0U);
92
93 /*
94 * Do initial security configuration to allow DRAM/device access. On
95 * Base VERSAL only DRAM security is programmable (via TrustZone), but
96 * other platforms might have more programmable security devices
97 * present.
98 */
99
100 /* Populate common information for BL32 and BL33 */
101 SET_PARAM_HEAD(&bl32_image_ep_info, PARAM_EP, VERSION_1, 0);
102 SET_SECURITY_STATE(bl32_image_ep_info.h.attr, SECURE);
103 SET_PARAM_HEAD(&bl33_image_ep_info, PARAM_EP, VERSION_1, 0);
104 SET_SECURITY_STATE(bl33_image_ep_info.h.attr, NON_SECURE);
105
106 atf_handoff_addr = mmio_read_32(PMC_GLOBAL_GLOB_GEN_STORAGE4);
107 enum fsbl_handoff ret = fsbl_atf_handover(&bl32_image_ep_info,
108 &bl33_image_ep_info,
109 atf_handoff_addr);
110 if (ret == FSBL_HANDOFF_NO_STRUCT || ret == FSBL_HANDOFF_INVAL_STRUCT) {
111 bl31_set_default_config();
112 } else if (ret != FSBL_HANDOFF_SUCCESS) {
113 panic();
114 }
115
116 NOTICE("BL31: Secure code at 0x%lx\n", bl32_image_ep_info.pc);
117 NOTICE("BL31: Non secure code at 0x%lx\n", bl33_image_ep_info.pc);
118 }
119
120 static interrupt_type_handler_t type_el3_interrupt_handler;
121
request_intr_type_el3(uint32_t id,interrupt_type_handler_t handler)122 int request_intr_type_el3(uint32_t id, interrupt_type_handler_t handler)
123 {
124 /* Validate 'handler'*/
125 if (!handler) {
126 return -EINVAL;
127 }
128
129 type_el3_interrupt_handler = handler;
130
131 return 0;
132 }
133
rdo_el3_interrupt_handler(uint32_t id,uint32_t flags,void * handle,void * cookie)134 static uint64_t rdo_el3_interrupt_handler(uint32_t id, uint32_t flags,
135 void *handle, void *cookie)
136 {
137 uint32_t intr_id;
138 interrupt_type_handler_t handler;
139
140 intr_id = plat_ic_get_pending_interrupt_id();
141 /* Currently we support one interrupt */
142 if (intr_id != PLAT_VERSAL_IPI_IRQ) {
143 WARN("Unexpected interrupt call: 0x%x\n", intr_id);
144 return 0;
145 }
146
147 handler = type_el3_interrupt_handler;
148 if (handler) {
149 return handler(intr_id, flags, handle, cookie);
150 }
151
152 return 0;
153 }
bl31_platform_setup(void)154 void bl31_platform_setup(void)
155 {
156 /* Initialize the gic cpu and distributor interfaces */
157 plat_versal_gic_driver_init();
158 plat_versal_gic_init();
159 }
160
bl31_plat_runtime_setup(void)161 void bl31_plat_runtime_setup(void)
162 {
163 uint64_t flags = 0;
164 uint64_t rc;
165
166 set_interrupt_rm_flag(flags, NON_SECURE);
167 rc = register_interrupt_type_handler(INTR_TYPE_EL3,
168 rdo_el3_interrupt_handler, flags);
169 if (rc) {
170 panic();
171 }
172 }
173
174 /*
175 * Perform the very early platform specific architectural setup here.
176 */
bl31_plat_arch_setup(void)177 void bl31_plat_arch_setup(void)
178 {
179 plat_arm_interconnect_init();
180 plat_arm_interconnect_enter_coherency();
181
182 const mmap_region_t bl_regions[] = {
183 MAP_REGION_FLAT(BL31_BASE, BL31_END - BL31_BASE,
184 MT_MEMORY | MT_RW | MT_SECURE),
185 MAP_REGION_FLAT(BL_CODE_BASE, BL_CODE_END - BL_CODE_BASE,
186 MT_CODE | MT_SECURE),
187 MAP_REGION_FLAT(BL_RO_DATA_BASE, BL_RO_DATA_END - BL_RO_DATA_BASE,
188 MT_RO_DATA | MT_SECURE),
189 MAP_REGION_FLAT(BL_COHERENT_RAM_BASE,
190 BL_COHERENT_RAM_END - BL_COHERENT_RAM_BASE,
191 MT_DEVICE | MT_RW | MT_SECURE),
192 {0}
193 };
194
195 setup_page_tables(bl_regions, plat_versal_get_mmap());
196 enable_mmu_el3(0);
197 }
198