1 /*
2  * Copyright (c) 2013-2020, ARM Limited and Contributors. All rights reserved.
3  *
4  * SPDX-License-Identifier: BSD-3-Clause
5  */
6 
7 /* ZynqMP power management enums and defines */
8 
9 #ifndef PM_DEFS_H
10 #define PM_DEFS_H
11 
12 /*********************************************************************
13  * Macro definitions
14  ********************************************************************/
15 
16 /*
17  * Version number is a 32bit value, like:
18  * (PM_VERSION_MAJOR << 16) | PM_VERSION_MINOR
19  */
20 #define PM_VERSION_MAJOR	1
21 #define PM_VERSION_MINOR	1
22 
23 #define PM_VERSION	((PM_VERSION_MAJOR << 16) | PM_VERSION_MINOR)
24 
25 /* Capabilities for RAM */
26 #define PM_CAP_ACCESS	0x1U
27 #define PM_CAP_CONTEXT	0x2U
28 
29 #define MAX_LATENCY	(~0U)
30 #define MAX_QOS		100U
31 
32 /* State arguments of the self suspend */
33 #define PM_STATE_CPU_IDLE		0x0U
34 #define PM_STATE_SUSPEND_TO_RAM		0xFU
35 
36 #define EM_FUNID_NUM_MASK    0xF0000U
37 /*********************************************************************
38  * Enum definitions
39  ********************************************************************/
40 
41 enum pm_api_id {
42 	/* Miscellaneous API functions: */
43 	PM_GET_API_VERSION = 1, /* Do not change or move */
44 	PM_SET_CONFIGURATION,
45 	PM_GET_NODE_STATUS,
46 	PM_GET_OP_CHARACTERISTIC,
47 	PM_REGISTER_NOTIFIER,
48 	/* API for suspending of PUs: */
49 	PM_REQ_SUSPEND,
50 	PM_SELF_SUSPEND,
51 	PM_FORCE_POWERDOWN,
52 	PM_ABORT_SUSPEND,
53 	PM_REQ_WAKEUP,
54 	PM_SET_WAKEUP_SOURCE,
55 	PM_SYSTEM_SHUTDOWN,
56 	/* API for managing PM slaves: */
57 	PM_REQ_NODE,
58 	PM_RELEASE_NODE,
59 	PM_SET_REQUIREMENT,
60 	PM_SET_MAX_LATENCY,
61 	/* Direct control API functions: */
62 	PM_RESET_ASSERT,
63 	PM_RESET_GET_STATUS,
64 	PM_MMIO_WRITE,
65 	PM_MMIO_READ,
66 	PM_INIT_FINALIZE,
67 	PM_FPGA_LOAD,
68 	PM_FPGA_GET_STATUS,
69 	PM_GET_CHIPID,
70 	PM_SECURE_RSA_AES,
71 	PM_SECURE_SHA,
72 	PM_SECURE_RSA,
73 	PM_PINCTRL_REQUEST,
74 	PM_PINCTRL_RELEASE,
75 	PM_PINCTRL_GET_FUNCTION,
76 	PM_PINCTRL_SET_FUNCTION,
77 	PM_PINCTRL_CONFIG_PARAM_GET,
78 	PM_PINCTRL_CONFIG_PARAM_SET,
79 	PM_IOCTL,
80 	/* API to query information from firmware */
81 	PM_QUERY_DATA,
82 	/* Clock control API functions */
83 	PM_CLOCK_ENABLE,
84 	PM_CLOCK_DISABLE,
85 	PM_CLOCK_GETSTATE,
86 	PM_CLOCK_SETDIVIDER,
87 	PM_CLOCK_GETDIVIDER,
88 	PM_CLOCK_SETRATE,
89 	PM_CLOCK_GETRATE,
90 	PM_CLOCK_SETPARENT,
91 	PM_CLOCK_GETPARENT,
92 	PM_SECURE_IMAGE,
93 	/* FPGA PL Readback */
94 	PM_FPGA_READ,
95 	PM_SECURE_AES,
96 	/* PLL control API functions */
97 	PM_PLL_SET_PARAMETER,
98 	PM_PLL_GET_PARAMETER,
99 	PM_PLL_SET_MODE,
100 	PM_PLL_GET_MODE,
101 	/* PM Register Access API */
102 	PM_REGISTER_ACCESS,
103 	PM_EFUSE_ACCESS,
104 	PM_API_MAX
105 };
106 
107 enum pm_node_id {
108 	NODE_UNKNOWN = 0,
109 	NODE_APU,
110 	NODE_APU_0,
111 	NODE_APU_1,
112 	NODE_APU_2,
113 	NODE_APU_3,
114 	NODE_RPU,
115 	NODE_RPU_0,
116 	NODE_RPU_1,
117 	NODE_PLD,
118 	NODE_FPD,
119 	NODE_OCM_BANK_0,
120 	NODE_OCM_BANK_1,
121 	NODE_OCM_BANK_2,
122 	NODE_OCM_BANK_3,
123 	NODE_TCM_0_A,
124 	NODE_TCM_0_B,
125 	NODE_TCM_1_A,
126 	NODE_TCM_1_B,
127 	NODE_L2,
128 	NODE_GPU_PP_0,
129 	NODE_GPU_PP_1,
130 	NODE_USB_0,
131 	NODE_USB_1,
132 	NODE_TTC_0,
133 	NODE_TTC_1,
134 	NODE_TTC_2,
135 	NODE_TTC_3,
136 	NODE_SATA,
137 	NODE_ETH_0,
138 	NODE_ETH_1,
139 	NODE_ETH_2,
140 	NODE_ETH_3,
141 	NODE_UART_0,
142 	NODE_UART_1,
143 	NODE_SPI_0,
144 	NODE_SPI_1,
145 	NODE_I2C_0,
146 	NODE_I2C_1,
147 	NODE_SD_0,
148 	NODE_SD_1,
149 	NODE_DP,
150 	NODE_GDMA,
151 	NODE_ADMA,
152 	NODE_NAND,
153 	NODE_QSPI,
154 	NODE_GPIO,
155 	NODE_CAN_0,
156 	NODE_CAN_1,
157 	NODE_EXTERN,
158 	NODE_APLL,
159 	NODE_VPLL,
160 	NODE_DPLL,
161 	NODE_RPLL,
162 	NODE_IOPLL,
163 	NODE_DDR,
164 	NODE_IPI_APU,
165 	NODE_IPI_RPU_0,
166 	NODE_GPU,
167 	NODE_PCIE,
168 	NODE_PCAP,
169 	NODE_RTC,
170 	NODE_LPD,
171 	NODE_VCU,
172 	NODE_IPI_RPU_1,
173 	NODE_IPI_PL_0,
174 	NODE_IPI_PL_1,
175 	NODE_IPI_PL_2,
176 	NODE_IPI_PL_3,
177 	NODE_PL,
178 	NODE_GEM_TSU,
179 	NODE_SWDT_0,
180 	NODE_SWDT_1,
181 	NODE_CSU,
182 	NODE_PJTAG,
183 	NODE_TRACE,
184 	NODE_TESTSCAN,
185 	NODE_PMU,
186 	NODE_MAX,
187 };
188 
189 enum pm_request_ack {
190 	REQ_ACK_NO = 1,
191 	REQ_ACK_BLOCKING,
192 	REQ_ACK_NON_BLOCKING,
193 };
194 
195 enum pm_abort_reason {
196 	ABORT_REASON_WKUP_EVENT = 100,
197 	ABORT_REASON_PU_BUSY,
198 	ABORT_REASON_NO_PWRDN,
199 	ABORT_REASON_UNKNOWN,
200 };
201 
202 enum pm_suspend_reason {
203 	SUSPEND_REASON_PU_REQ = 201,
204 	SUSPEND_REASON_ALERT,
205 	SUSPEND_REASON_SYS_SHUTDOWN,
206 };
207 
208 enum pm_ram_state {
209 	PM_RAM_STATE_OFF = 1,
210 	PM_RAM_STATE_RETENTION,
211 	PM_RAM_STATE_ON,
212 };
213 
214 enum pm_opchar_type {
215 	PM_OPCHAR_TYPE_POWER = 1,
216 	PM_OPCHAR_TYPE_TEMP,
217 	PM_OPCHAR_TYPE_LATENCY,
218 };
219 
220 /**
221  * @PM_RET_SUCCESS:		success
222  * @PM_RET_ERROR_ARGS:		illegal arguments provided (deprecated)
223  * @PM_RET_ERROR_NOTSUPPORTED:	feature not supported  (deprecated)
224  * @PM_RET_ERROR_INTERNAL:	internal error
225  * @PM_RET_ERROR_CONFLICT:	conflict
226  * @PM_RET_ERROR_ACCESS:	access rights violation
227  * @PM_RET_ERROR_INVALID_NODE:	invalid node
228  * @PM_RET_ERROR_DOUBLE_REQ:	duplicate request for same node
229  * @PM_RET_ERROR_ABORT_SUSPEND:	suspend procedure has been aborted
230  * @PM_RET_ERROR_TIMEOUT:	timeout in communication with PMU
231  * @PM_RET_ERROR_NODE_USED:	node is already in use
232  */
233 enum pm_ret_status {
234 	PM_RET_SUCCESS,
235 	PM_RET_ERROR_ARGS = 1,
236 	PM_RET_ERROR_NOTSUPPORTED = 4,
237 	PM_RET_ERROR_INTERNAL = 2000,
238 	PM_RET_ERROR_CONFLICT = 2001,
239 	PM_RET_ERROR_ACCESS = 2002,
240 	PM_RET_ERROR_INVALID_NODE = 2003,
241 	PM_RET_ERROR_DOUBLE_REQ = 2004,
242 	PM_RET_ERROR_ABORT_SUSPEND = 2005,
243 	PM_RET_ERROR_TIMEOUT = 2006,
244 	PM_RET_ERROR_NODE_USED = 2007
245 };
246 
247 /**
248  * @PM_INITIAL_BOOT:	boot is a fresh system startup
249  * @PM_RESUME:		boot is a resume
250  * @PM_BOOT_ERROR:	error, boot cause cannot be identified
251  */
252 enum pm_boot_status {
253 	PM_INITIAL_BOOT,
254 	PM_RESUME,
255 	PM_BOOT_ERROR,
256 };
257 
258 /**
259  * @PMF_SHUTDOWN_TYPE_SHUTDOWN:		shutdown
260  * @PMF_SHUTDOWN_TYPE_RESET:		reset/reboot
261  * @PMF_SHUTDOWN_TYPE_SETSCOPE_ONLY:	set the shutdown/reboot scope
262  */
263 enum pm_shutdown_type {
264 	PMF_SHUTDOWN_TYPE_SHUTDOWN,
265 	PMF_SHUTDOWN_TYPE_RESET,
266 	PMF_SHUTDOWN_TYPE_SETSCOPE_ONLY,
267 };
268 
269 /**
270  * @PMF_SHUTDOWN_SUBTYPE_SUBSYSTEM:	shutdown/reboot APU subsystem only
271  * @PMF_SHUTDOWN_SUBTYPE_PS_ONLY:	shutdown/reboot entire PS (but not PL)
272  * @PMF_SHUTDOWN_SUBTYPE_SYSTEM:	shutdown/reboot entire system
273  */
274 enum pm_shutdown_subtype {
275 	PMF_SHUTDOWN_SUBTYPE_SUBSYSTEM,
276 	PMF_SHUTDOWN_SUBTYPE_PS_ONLY,
277 	PMF_SHUTDOWN_SUBTYPE_SYSTEM,
278 };
279 
280 /**
281  * @PM_PLL_PARAM_DIV2:         Enable for divide by 2 function inside the PLL
282  * @PM_PLL_PARAM_FBDIV:        Feedback divisor integer portion for the PLL
283  * @PM_PLL_PARAM_DATA:         Feedback divisor fractional portion for the PLL
284  * @PM_PLL_PARAM_PRE_SRC:      Clock source for PLL input
285  * @PM_PLL_PARAM_POST_SRC:     Clock source for PLL Bypass mode
286  * @PM_PLL_PARAM_LOCK_DLY:     Lock circuit config settings for lock windowsize
287  * @PM_PLL_PARAM_LOCK_CNT:     Lock circuit counter setting
288  * @PM_PLL_PARAM_LFHF:         PLL loop filter high frequency capacitor control
289  * @PM_PLL_PARAM_CP:           PLL charge pump control
290  * @PM_PLL_PARAM_RES:          PLL loop filter resistor control
291  */
292 enum pm_pll_param {
293 	PM_PLL_PARAM_DIV2,
294 	PM_PLL_PARAM_FBDIV,
295 	PM_PLL_PARAM_DATA,
296 	PM_PLL_PARAM_PRE_SRC,
297 	PM_PLL_PARAM_POST_SRC,
298 	PM_PLL_PARAM_LOCK_DLY,
299 	PM_PLL_PARAM_LOCK_CNT,
300 	PM_PLL_PARAM_LFHF,
301 	PM_PLL_PARAM_CP,
302 	PM_PLL_PARAM_RES,
303 	PM_PLL_PARAM_MAX,
304 };
305 
306 /**
307  * @PM_PLL_MODE_RESET:         PLL is in reset (not locked)
308  * @PM_PLL_MODE_INTEGER:       PLL is locked in integer mode
309  * @PM_PLL_MODE_FRACTIONAL:    PLL is locked in fractional mode
310  */
311 enum pm_pll_mode {
312 	PM_PLL_MODE_RESET,
313 	PM_PLL_MODE_INTEGER,
314 	PM_PLL_MODE_FRACTIONAL,
315 	PM_PLL_MODE_MAX,
316 };
317 
318 /**
319  * @PM_CLOCK_DIV0_ID:          Clock divider 0
320  * @PM_CLOCK_DIV1_ID:          Clock divider 1
321  */
322 enum pm_clock_div_id {
323 	PM_CLOCK_DIV0_ID,
324 	PM_CLOCK_DIV1_ID,
325 };
326 
327 /**
328  * EM API IDs
329  */
330 enum em_api_id {
331 	EM_SET_ACTION = 1,
332 	EM_REMOVE_ACTION,
333 	EM_SEND_ERRORS,
334 };
335 
336 #endif /* PM_DEFS_H */
337