1 /*
2 * Copyright (c) 2013-2020, ARM Limited and Contributors. All rights reserved.
3 *
4 * SPDX-License-Identifier: BSD-3-Clause
5 */
6
7 /*
8 * Top-level SMC handler for ZynqMP power management calls and
9 * IPI setup functions for communication with PMU.
10 */
11
12 #include <errno.h>
13
14 #include <common/runtime_svc.h>
15 #if ZYNQMP_WDT_RESTART
16 #include <arch_helpers.h>
17 #include <drivers/arm/gicv2.h>
18 #include <lib/mmio.h>
19 #include <lib/spinlock.h>
20 #include <plat/common/platform.h>
21 #endif
22
23 #include <plat_private.h>
24 #include "pm_api_sys.h"
25 #include "pm_client.h"
26 #include "pm_ipi.h"
27
28 #define PM_GET_CALLBACK_DATA 0xa01
29 #define PM_SET_SUSPEND_MODE 0xa02
30 #define PM_GET_TRUSTZONE_VERSION 0xa03
31
32 /* pm_up = !0 - UP, pm_up = 0 - DOWN */
33 static int32_t pm_up, ipi_irq_flag;
34
35 #if ZYNQMP_WDT_RESTART
36 static spinlock_t inc_lock;
37 static int active_cores = 0;
38 #endif
39
40
41 /**
42 * pm_context - Structure which contains data for power management
43 * @api_version version of PM API, must match with one on PMU side
44 * @payload payload array used to store received
45 * data from ipi buffer registers
46 */
47 static struct {
48 uint32_t api_version;
49 uint32_t payload[PAYLOAD_ARG_CNT];
50 } pm_ctx;
51
52 #if ZYNQMP_WDT_RESTART
53 /**
54 * trigger_wdt_restart() - Trigger warm restart event to APU cores
55 *
56 * This function triggers SGI for all active APU CPUs. SGI handler then
57 * power down CPU and call system reset.
58 */
trigger_wdt_restart(void)59 static void trigger_wdt_restart(void)
60 {
61 uint32_t core_count = 0;
62 uint32_t core_status[3];
63 uint32_t target_cpu_list = 0;
64 int i;
65
66 for (i = 0; i < 4; i++) {
67 pm_get_node_status(NODE_APU_0 + i, core_status);
68 if (core_status[0] == 1) {
69 core_count++;
70 target_cpu_list |= (1 << i);
71 }
72 }
73
74 spin_lock(&inc_lock);
75 active_cores = core_count;
76 spin_unlock(&inc_lock);
77
78 INFO("Active Cores: %d\n", active_cores);
79
80 for (i = PLATFORM_CORE_COUNT - 1; i >= 0; i--) {
81 if (target_cpu_list & (1 << i)) {
82 /* trigger SGI to active cores */
83 plat_ic_raise_el3_sgi(ARM_IRQ_SEC_SGI_7, i);
84 }
85 }
86 }
87
88 /**
89 * ttc_fiq_handler() - TTC Handler for timer event
90 * @id number of the highest priority pending interrupt of the type
91 * that this handler was registered for
92 * @flags security state, bit[0]
93 * @handler pointer to 'cpu_context' structure of the current CPU for the
94 * security state specified in the 'flags' parameter
95 * @cookie unused
96 *
97 * Function registered as INTR_TYPE_EL3 interrupt handler
98 *
99 * When WDT event is received in PMU, PMU needs to notify master to do cleanup
100 * if required. PMU sets up timer and starts timer to overflow in zero time upon
101 * WDT event. ATF handles this timer event and takes necessary action required
102 * for warm restart.
103 *
104 * In presence of non-secure software layers (EL1/2) sets the interrupt
105 * at registered entrance in GIC and informs that PMU responsed or demands
106 * action.
107 */
ttc_fiq_handler(uint32_t id,uint32_t flags,void * handle,void * cookie)108 static uint64_t ttc_fiq_handler(uint32_t id, uint32_t flags, void *handle,
109 void *cookie)
110 {
111 INFO("BL31: Got TTC FIQ\n");
112
113 plat_ic_end_of_interrupt(id);
114
115 /* Clear TTC interrupt by reading interrupt register */
116 mmio_read_32(TTC3_INTR_REGISTER_1);
117
118 /* Disable the timer interrupts */
119 mmio_write_32(TTC3_INTR_ENABLE_1, 0);
120
121 trigger_wdt_restart();
122
123 return 0;
124 }
125
126 /**
127 * zynqmp_sgi7_irq() - Handler for SGI7 IRQ
128 * @id number of the highest priority pending interrupt of the type
129 * that this handler was registered for
130 * @flags security state, bit[0]
131 * @handler pointer to 'cpu_context' structure of the current CPU for the
132 * security state specified in the 'flags' parameter
133 * @cookie unused
134 *
135 * Function registered as INTR_TYPE_EL3 interrupt handler
136 *
137 * On receiving WDT event from PMU, ATF generates SGI7 to all running CPUs.
138 * In response to SGI7 interrupt, each CPUs do clean up if required and last
139 * running CPU calls system restart.
140 */
zynqmp_sgi7_irq(uint32_t id,uint32_t flags,void * handle,void * cookie)141 static uint64_t __unused __dead2 zynqmp_sgi7_irq(uint32_t id, uint32_t flags,
142 void *handle, void *cookie)
143 {
144 int i;
145 uint32_t value;
146
147 /* enter wfi and stay there */
148 INFO("Entering wfi\n");
149
150 spin_lock(&inc_lock);
151 active_cores--;
152
153 for (i = 0; i < 4; i++) {
154 mmio_write_32(BASE_GICD_BASE + GICD_CPENDSGIR + 4 * i,
155 0xffffffff);
156 }
157
158 spin_unlock(&inc_lock);
159
160 if (active_cores == 0) {
161 pm_mmio_read(PMU_GLOBAL_GEN_STORAGE4, &value);
162 value = (value & RESTART_SCOPE_MASK) >> RESTART_SCOPE_SHIFT;
163 pm_system_shutdown(PMF_SHUTDOWN_TYPE_RESET, value);
164 }
165
166 /* enter wfi and stay there */
167 while (1)
168 wfi();
169 }
170
171 /**
172 * pm_wdt_restart_setup() - Setup warm restart interrupts
173 *
174 * This function sets up handler for SGI7 and TTC interrupts
175 * used for warm restart.
176 */
pm_wdt_restart_setup(void)177 static int pm_wdt_restart_setup(void)
178 {
179 int ret;
180
181 /* register IRQ handler for SGI7 */
182 ret = request_intr_type_el3(ARM_IRQ_SEC_SGI_7, zynqmp_sgi7_irq);
183 if (ret) {
184 WARN("BL31: registering SGI7 interrupt failed\n");
185 goto err;
186 }
187
188 ret = request_intr_type_el3(IRQ_TTC3_1, ttc_fiq_handler);
189 if (ret)
190 WARN("BL31: registering TTC3 interrupt failed\n");
191
192 err:
193 return ret;
194 }
195 #endif
196
197 /**
198 * pm_setup() - PM service setup
199 *
200 * @return On success, the initialization function must return 0.
201 * Any other return value will cause the framework to ignore
202 * the service
203 *
204 * Initialization functions for ZynqMP power management for
205 * communicaton with PMU.
206 *
207 * Called from sip_svc_setup initialization function with the
208 * rt_svc_init signature.
209 */
pm_setup(void)210 int pm_setup(void)
211 {
212 int status, ret;
213
214 status = pm_ipi_init(primary_proc);
215
216 ret = pm_get_api_version(&pm_ctx.api_version);
217 if (pm_ctx.api_version < PM_VERSION) {
218 ERROR("BL31: Platform Management API version error. Expected: "
219 "v%d.%d - Found: v%d.%d\n", PM_VERSION_MAJOR,
220 PM_VERSION_MINOR, pm_ctx.api_version >> 16,
221 pm_ctx.api_version & 0xFFFF);
222 return -EINVAL;
223 }
224
225 #if ZYNQMP_WDT_RESTART
226 status = pm_wdt_restart_setup();
227 if (status)
228 WARN("BL31: warm-restart setup failed\n");
229 #endif
230
231 if (status >= 0) {
232 INFO("BL31: PM Service Init Complete: API v%d.%d\n",
233 PM_VERSION_MAJOR, PM_VERSION_MINOR);
234 ret = 0;
235 } else {
236 INFO("BL31: PM Service Init Failed, Error Code %d!\n", status);
237 ret = status;
238 }
239
240 pm_up = !status;
241
242 return ret;
243 }
244
245 /**
246 * pm_smc_handler() - SMC handler for PM-API calls coming from EL1/EL2.
247 * @smc_fid - Function Identifier
248 * @x1 - x4 - Arguments
249 * @cookie - Unused
250 * @handler - Pointer to caller's context structure
251 *
252 * @return - Unused
253 *
254 * Determines that smc_fid is valid and supported PM SMC Function ID from the
255 * list of pm_api_ids, otherwise completes the request with
256 * the unknown SMC Function ID
257 *
258 * The SMC calls for PM service are forwarded from SIP Service SMC handler
259 * function with rt_svc_handle signature
260 */
pm_smc_handler(uint32_t smc_fid,uint64_t x1,uint64_t x2,uint64_t x3,uint64_t x4,void * cookie,void * handle,uint64_t flags)261 uint64_t pm_smc_handler(uint32_t smc_fid, uint64_t x1, uint64_t x2, uint64_t x3,
262 uint64_t x4, void *cookie, void *handle, uint64_t flags)
263 {
264 enum pm_ret_status ret;
265
266 uint32_t pm_arg[4];
267
268 /* Handle case where PM wasn't initialized properly */
269 if (!pm_up)
270 SMC_RET1(handle, SMC_UNK);
271
272 pm_arg[0] = (uint32_t)x1;
273 pm_arg[1] = (uint32_t)(x1 >> 32);
274 pm_arg[2] = (uint32_t)x2;
275 pm_arg[3] = (uint32_t)(x2 >> 32);
276
277 switch (smc_fid & FUNCID_NUM_MASK) {
278 /* PM API Functions */
279 case PM_SELF_SUSPEND:
280 ret = pm_self_suspend(pm_arg[0], pm_arg[1], pm_arg[2],
281 pm_arg[3]);
282 SMC_RET1(handle, (uint64_t)ret);
283
284 case PM_REQ_SUSPEND:
285 ret = pm_req_suspend(pm_arg[0], pm_arg[1], pm_arg[2],
286 pm_arg[3]);
287 SMC_RET1(handle, (uint64_t)ret);
288
289 case PM_REQ_WAKEUP:
290 {
291 /* Use address flag is encoded in the 1st bit of the low-word */
292 unsigned int set_addr = pm_arg[1] & 0x1;
293 uint64_t address = (uint64_t)pm_arg[2] << 32;
294
295 address |= pm_arg[1] & (~0x1);
296 ret = pm_req_wakeup(pm_arg[0], set_addr, address,
297 pm_arg[3]);
298 SMC_RET1(handle, (uint64_t)ret);
299 }
300
301 case PM_FORCE_POWERDOWN:
302 ret = pm_force_powerdown(pm_arg[0], pm_arg[1]);
303 SMC_RET1(handle, (uint64_t)ret);
304
305 case PM_ABORT_SUSPEND:
306 ret = pm_abort_suspend(pm_arg[0]);
307 SMC_RET1(handle, (uint64_t)ret);
308
309 case PM_SET_WAKEUP_SOURCE:
310 ret = pm_set_wakeup_source(pm_arg[0], pm_arg[1], pm_arg[2]);
311 SMC_RET1(handle, (uint64_t)ret);
312
313 case PM_SYSTEM_SHUTDOWN:
314 ret = pm_system_shutdown(pm_arg[0], pm_arg[1]);
315 SMC_RET1(handle, (uint64_t)ret);
316
317 case PM_REQ_NODE:
318 ret = pm_req_node(pm_arg[0], pm_arg[1], pm_arg[2], pm_arg[3]);
319 SMC_RET1(handle, (uint64_t)ret);
320
321 case PM_RELEASE_NODE:
322 ret = pm_release_node(pm_arg[0]);
323 SMC_RET1(handle, (uint64_t)ret);
324
325 case PM_SET_REQUIREMENT:
326 ret = pm_set_requirement(pm_arg[0], pm_arg[1], pm_arg[2],
327 pm_arg[3]);
328 SMC_RET1(handle, (uint64_t)ret);
329
330 case PM_SET_MAX_LATENCY:
331 ret = pm_set_max_latency(pm_arg[0], pm_arg[1]);
332 SMC_RET1(handle, (uint64_t)ret);
333
334 case PM_GET_API_VERSION:
335 /* Check is PM API version already verified */
336 if (pm_ctx.api_version >= PM_VERSION) {
337 if (!ipi_irq_flag) {
338 /*
339 * Enable IPI IRQ
340 * assume the rich OS is OK to handle callback IRQs now.
341 * Even if we were wrong, it would not enable the IRQ in
342 * the GIC.
343 */
344 pm_ipi_irq_enable(primary_proc);
345 ipi_irq_flag = 1;
346 }
347 SMC_RET1(handle, (uint64_t)PM_RET_SUCCESS |
348 ((uint64_t)pm_ctx.api_version << 32));
349 }
350
351 case PM_SET_CONFIGURATION:
352 ret = pm_set_configuration(pm_arg[0]);
353 SMC_RET1(handle, (uint64_t)ret);
354
355 case PM_INIT_FINALIZE:
356 ret = pm_init_finalize();
357 SMC_RET1(handle, (uint64_t)ret);
358
359 case PM_GET_NODE_STATUS:
360 {
361 uint32_t buff[3];
362
363 ret = pm_get_node_status(pm_arg[0], buff);
364 SMC_RET2(handle, (uint64_t)ret | ((uint64_t)buff[0] << 32),
365 (uint64_t)buff[1] | ((uint64_t)buff[2] << 32));
366 }
367
368 case PM_GET_OP_CHARACTERISTIC:
369 {
370 uint32_t result;
371
372 ret = pm_get_op_characteristic(pm_arg[0], pm_arg[1], &result);
373 SMC_RET1(handle, (uint64_t)ret | ((uint64_t)result << 32));
374 }
375
376 case PM_REGISTER_NOTIFIER:
377 ret = pm_register_notifier(pm_arg[0], pm_arg[1], pm_arg[2],
378 pm_arg[3]);
379 SMC_RET1(handle, (uint64_t)ret);
380
381 case PM_RESET_ASSERT:
382 ret = pm_reset_assert(pm_arg[0], pm_arg[1]);
383 SMC_RET1(handle, (uint64_t)ret);
384
385 case PM_RESET_GET_STATUS:
386 {
387 uint32_t reset_status;
388
389 ret = pm_reset_get_status(pm_arg[0], &reset_status);
390 SMC_RET1(handle, (uint64_t)ret |
391 ((uint64_t)reset_status << 32));
392 }
393
394 /* PM memory access functions */
395 case PM_MMIO_WRITE:
396 ret = pm_mmio_write(pm_arg[0], pm_arg[1], pm_arg[2]);
397 SMC_RET1(handle, (uint64_t)ret);
398
399 case PM_MMIO_READ:
400 {
401 uint32_t value;
402
403 ret = pm_mmio_read(pm_arg[0], &value);
404 SMC_RET1(handle, (uint64_t)ret | ((uint64_t)value) << 32);
405 }
406
407 case PM_FPGA_LOAD:
408 ret = pm_fpga_load(pm_arg[0], pm_arg[1], pm_arg[2], pm_arg[3]);
409 SMC_RET1(handle, (uint64_t)ret);
410
411 case PM_FPGA_GET_STATUS:
412 {
413 uint32_t value;
414
415 ret = pm_fpga_get_status(&value);
416 SMC_RET1(handle, (uint64_t)ret | ((uint64_t)value) << 32);
417 }
418
419 case PM_GET_CHIPID:
420 {
421 uint32_t result[2];
422
423 ret = pm_get_chipid(result);
424 SMC_RET2(handle, (uint64_t)ret | ((uint64_t)result[0] << 32),
425 result[1]);
426 }
427
428 case PM_SECURE_RSA_AES:
429 ret = pm_secure_rsaaes(pm_arg[0], pm_arg[1], pm_arg[2],
430 pm_arg[3]);
431 SMC_RET1(handle, (uint64_t)ret);
432
433 case PM_GET_CALLBACK_DATA:
434 {
435 uint32_t result[4] = {0};
436
437 pm_get_callbackdata(result, ARRAY_SIZE(result));
438 SMC_RET2(handle,
439 (uint64_t)result[0] | ((uint64_t)result[1] << 32),
440 (uint64_t)result[2] | ((uint64_t)result[3] << 32));
441 }
442
443 case PM_PINCTRL_REQUEST:
444 ret = pm_pinctrl_request(pm_arg[0]);
445 SMC_RET1(handle, (uint64_t)ret);
446
447 case PM_PINCTRL_RELEASE:
448 ret = pm_pinctrl_release(pm_arg[0]);
449 SMC_RET1(handle, (uint64_t)ret);
450
451 case PM_PINCTRL_GET_FUNCTION:
452 {
453 uint32_t value = 0;
454
455 ret = pm_pinctrl_get_function(pm_arg[0], &value);
456 SMC_RET1(handle, (uint64_t)ret | ((uint64_t)value) << 32);
457 }
458
459 case PM_PINCTRL_SET_FUNCTION:
460 ret = pm_pinctrl_set_function(pm_arg[0], pm_arg[1]);
461 SMC_RET1(handle, (uint64_t)ret);
462
463 case PM_PINCTRL_CONFIG_PARAM_GET:
464 {
465 uint32_t value;
466
467 ret = pm_pinctrl_get_config(pm_arg[0], pm_arg[1], &value);
468 SMC_RET1(handle, (uint64_t)ret | ((uint64_t)value) << 32);
469 }
470
471 case PM_PINCTRL_CONFIG_PARAM_SET:
472 ret = pm_pinctrl_set_config(pm_arg[0], pm_arg[1], pm_arg[2]);
473 SMC_RET1(handle, (uint64_t)ret);
474
475 case PM_IOCTL:
476 {
477 uint32_t value;
478
479 ret = pm_ioctl(pm_arg[0], pm_arg[1], pm_arg[2],
480 pm_arg[3], &value);
481 SMC_RET1(handle, (uint64_t)ret | ((uint64_t)value) << 32);
482 }
483
484 case PM_QUERY_DATA:
485 {
486 uint32_t data[4] = { 0 };
487
488 pm_query_data(pm_arg[0], pm_arg[1], pm_arg[2],
489 pm_arg[3], data);
490 SMC_RET2(handle, (uint64_t)data[0] | ((uint64_t)data[1] << 32),
491 (uint64_t)data[2] | ((uint64_t)data[3] << 32));
492 }
493
494 case PM_CLOCK_ENABLE:
495 ret = pm_clock_enable(pm_arg[0]);
496 SMC_RET1(handle, (uint64_t)ret);
497
498 case PM_CLOCK_DISABLE:
499 ret = pm_clock_disable(pm_arg[0]);
500 SMC_RET1(handle, (uint64_t)ret);
501
502 case PM_CLOCK_GETSTATE:
503 {
504 uint32_t value;
505
506 ret = pm_clock_getstate(pm_arg[0], &value);
507 SMC_RET1(handle, (uint64_t)ret | ((uint64_t)value) << 32);
508 }
509
510 case PM_CLOCK_SETDIVIDER:
511 ret = pm_clock_setdivider(pm_arg[0], pm_arg[1]);
512 SMC_RET1(handle, (uint64_t)ret);
513
514 case PM_CLOCK_GETDIVIDER:
515 {
516 uint32_t value;
517
518 ret = pm_clock_getdivider(pm_arg[0], &value);
519 SMC_RET1(handle, (uint64_t)ret | ((uint64_t)value) << 32);
520 }
521
522 case PM_CLOCK_SETRATE:
523 ret = pm_clock_setrate(pm_arg[0],
524 ((uint64_t)pm_arg[2]) << 32 | pm_arg[1]);
525
526 SMC_RET1(handle, (uint64_t)ret);
527
528 case PM_CLOCK_GETRATE:
529 {
530 uint64_t value;
531
532 ret = pm_clock_getrate(pm_arg[0], &value);
533 SMC_RET2(handle, (uint64_t)ret |
534 (((uint64_t)value & 0xFFFFFFFFU) << 32U),
535 (value >> 32U) & 0xFFFFFFFFU);
536
537 }
538
539 case PM_CLOCK_SETPARENT:
540 ret = pm_clock_setparent(pm_arg[0], pm_arg[1]);
541 SMC_RET1(handle, (uint64_t)ret);
542
543 case PM_CLOCK_GETPARENT:
544 {
545 uint32_t value;
546
547 ret = pm_clock_getparent(pm_arg[0], &value);
548 SMC_RET1(handle, (uint64_t)ret | ((uint64_t)value) << 32);
549 }
550
551 case PM_GET_TRUSTZONE_VERSION:
552 SMC_RET1(handle, (uint64_t)PM_RET_SUCCESS |
553 ((uint64_t)ZYNQMP_TZ_VERSION << 32));
554
555 case PM_SET_SUSPEND_MODE:
556 ret = pm_set_suspend_mode(pm_arg[0]);
557 SMC_RET1(handle, (uint64_t)ret);
558
559 case PM_SECURE_SHA:
560 ret = pm_sha_hash(pm_arg[0], pm_arg[1], pm_arg[2],
561 pm_arg[3]);
562 SMC_RET1(handle, (uint64_t)ret);
563
564 case PM_SECURE_RSA:
565 ret = pm_rsa_core(pm_arg[0], pm_arg[1], pm_arg[2],
566 pm_arg[3]);
567 SMC_RET1(handle, (uint64_t)ret);
568
569 case PM_SECURE_IMAGE:
570 {
571 uint32_t result[2];
572
573 ret = pm_secure_image(pm_arg[0], pm_arg[1], pm_arg[2],
574 pm_arg[3], &result[0]);
575 SMC_RET2(handle, (uint64_t)ret | ((uint64_t)result[0] << 32),
576 result[1]);
577 }
578
579 case PM_FPGA_READ:
580 {
581 uint32_t value;
582
583 ret = pm_fpga_read(pm_arg[0], pm_arg[1], pm_arg[2], pm_arg[3],
584 &value);
585 SMC_RET1(handle, (uint64_t)ret | ((uint64_t)value) << 32);
586 }
587
588 case PM_SECURE_AES:
589 {
590 uint32_t value;
591
592 ret = pm_aes_engine(pm_arg[0], pm_arg[1], &value);
593 SMC_RET1(handle, (uint64_t)ret | ((uint64_t)value) << 32);
594 }
595
596 case PM_PLL_SET_PARAMETER:
597 ret = pm_pll_set_parameter(pm_arg[0], pm_arg[1], pm_arg[2]);
598 SMC_RET1(handle, (uint64_t)ret);
599
600 case PM_PLL_GET_PARAMETER:
601 {
602 uint32_t value;
603
604 ret = pm_pll_get_parameter(pm_arg[0], pm_arg[1], &value);
605 SMC_RET1(handle, (uint64_t)ret | ((uint64_t)value << 32));
606 }
607
608 case PM_PLL_SET_MODE:
609 ret = pm_pll_set_mode(pm_arg[0], pm_arg[1]);
610 SMC_RET1(handle, (uint64_t)ret);
611
612 case PM_PLL_GET_MODE:
613 {
614 uint32_t mode;
615
616 ret = pm_pll_get_mode(pm_arg[0], &mode);
617 SMC_RET1(handle, (uint64_t)ret | ((uint64_t)mode << 32));
618 }
619
620 case PM_REGISTER_ACCESS:
621 {
622 uint32_t value;
623
624 ret = pm_register_access(pm_arg[0], pm_arg[1], pm_arg[2],
625 pm_arg[3], &value);
626 SMC_RET1(handle, (uint64_t)ret | ((uint64_t)value) << 32);
627 }
628
629 case PM_EFUSE_ACCESS:
630 {
631 uint32_t value;
632
633 ret = pm_efuse_access(pm_arg[0], pm_arg[1], &value);
634 SMC_RET1(handle, (uint64_t)ret | ((uint64_t)value) << 32);
635 }
636
637 default:
638 WARN("Unimplemented PM Service Call: 0x%x\n", smc_fid);
639 SMC_RET1(handle, SMC_UNK);
640 }
641 }
642
643 /**
644 * em_smc_handler() - SMC handler for EM-API calls coming from EL1/EL2.
645 * @smc_fid - Function Identifier
646 * @x1 - x4 - Arguments
647 * @cookie - Unused
648 * @handler - Pointer to caller's context structure
649 *
650 * @return - Unused
651 *
652 * Determines that smc_fid is valid and supported EM SMC Function ID from the
653 * list of em_api_ids, otherwise completes the request with
654 * the unknown SMC Function ID
655 *
656 * The SMC calls for EM service are forwarded from SIP Service SMC handler
657 * function with rt_svc_handle signature
658 */
em_smc_handler(uint32_t smc_fid,uint64_t x1,uint64_t x2,uint64_t x3,uint64_t x4,void * cookie,void * handle,uint64_t flags)659 uint64_t em_smc_handler(uint32_t smc_fid, uint64_t x1, uint64_t x2, uint64_t x3,
660 uint64_t x4, void *cookie, void *handle, uint64_t flags)
661 {
662 enum pm_ret_status ret;
663
664 switch (smc_fid & FUNCID_NUM_MASK) {
665 /* EM API Functions */
666 case EM_SET_ACTION:
667 {
668 uint32_t value;
669
670 ret = em_set_action(&value);
671 SMC_RET1(handle, (uint64_t)ret | ((uint64_t)value) << 32);
672 }
673
674 case EM_REMOVE_ACTION:
675 {
676 uint32_t value;
677
678 ret = em_remove_action(&value);
679 SMC_RET1(handle, (uint64_t)ret | ((uint64_t)value) << 32);
680 }
681
682 case EM_SEND_ERRORS:
683 {
684 uint32_t value;
685
686 ret = em_send_errors(&value);
687 SMC_RET1(handle, (uint64_t)ret | ((uint64_t)value) << 32);
688 }
689
690 default:
691 WARN("Unimplemented EM Service Call: 0x%x\n", smc_fid);
692 SMC_RET1(handle, SMC_UNK);
693 }
694 }
695