1 /*
2 * Copyright (c) 2017-2020, ARM Limited and Contributors. All rights reserved.
3 * Copyright (c) 2021, NVIDIA Corporation. All rights reserved.
4 *
5 * SPDX-License-Identifier: BSD-3-Clause
6 */
7
8 #include <assert.h>
9 #include <string.h>
10
11 #include <arch.h>
12 #include <arch_helpers.h>
13 #include <context.h>
14 #include <common/debug.h>
15 #include <lib/el3_runtime/context_mgmt.h>
16 #include <lib/xlat_tables/xlat_tables_v2.h>
17 #include <platform_def.h>
18 #include <plat/common/common_def.h>
19 #include <plat/common/platform.h>
20 #include <services/spm_mm_partition.h>
21
22 #include "spm_mm_private.h"
23 #include "spm_mm_shim_private.h"
24
25 /* Setup context of the Secure Partition */
spm_sp_setup(sp_context_t * sp_ctx)26 void spm_sp_setup(sp_context_t *sp_ctx)
27 {
28 cpu_context_t *ctx = &(sp_ctx->cpu_ctx);
29
30 /* Pointer to the MP information from the platform port. */
31 const spm_mm_boot_info_t *sp_boot_info =
32 plat_get_secure_partition_boot_info(NULL);
33
34 /*
35 * Initialize CPU context
36 * ----------------------
37 */
38
39 entry_point_info_t ep_info = {0};
40
41 SET_PARAM_HEAD(&ep_info, PARAM_EP, VERSION_1, SECURE | EP_ST_ENABLE);
42
43 /* Setup entrypoint and SPSR */
44 ep_info.pc = sp_boot_info->sp_image_base;
45 ep_info.spsr = SPSR_64(MODE_EL0, MODE_SP_EL0, DISABLE_ALL_EXCEPTIONS);
46
47 /*
48 * X0: Virtual address of a buffer shared between EL3 and Secure EL0.
49 * The buffer will be mapped in the Secure EL1 translation regime
50 * with Normal IS WBWA attributes and RO data and Execute Never
51 * instruction access permissions.
52 *
53 * X1: Size of the buffer in bytes
54 *
55 * X2: cookie value (Implementation Defined)
56 *
57 * X3: cookie value (Implementation Defined)
58 *
59 * X4 to X7 = 0
60 */
61 ep_info.args.arg0 = sp_boot_info->sp_shared_buf_base;
62 ep_info.args.arg1 = sp_boot_info->sp_shared_buf_size;
63 ep_info.args.arg2 = PLAT_SPM_COOKIE_0;
64 ep_info.args.arg3 = PLAT_SPM_COOKIE_1;
65
66 cm_setup_context(ctx, &ep_info);
67
68 /*
69 * SP_EL0: A non-zero value will indicate to the SP that the SPM has
70 * initialized the stack pointer for the current CPU through
71 * implementation defined means. The value will be 0 otherwise.
72 */
73 write_ctx_reg(get_gpregs_ctx(ctx), CTX_GPREG_SP_EL0,
74 sp_boot_info->sp_stack_base + sp_boot_info->sp_pcpu_stack_size);
75
76 /*
77 * Setup translation tables
78 * ------------------------
79 */
80
81 #if ENABLE_ASSERTIONS
82
83 /* Get max granularity supported by the platform. */
84 unsigned int max_granule = xlat_arch_get_max_supported_granule_size();
85
86 VERBOSE("Max translation granule size supported: %u KiB\n",
87 max_granule / 1024U);
88
89 unsigned int max_granule_mask = max_granule - 1U;
90
91 /* Base must be aligned to the max granularity */
92 assert((sp_boot_info->sp_ns_comm_buf_base & max_granule_mask) == 0);
93
94 /* Size must be a multiple of the max granularity */
95 assert((sp_boot_info->sp_ns_comm_buf_size & max_granule_mask) == 0);
96
97 #endif /* ENABLE_ASSERTIONS */
98
99 /* This region contains the exception vectors used at S-EL1. */
100 const mmap_region_t sel1_exception_vectors =
101 MAP_REGION_FLAT(SPM_SHIM_EXCEPTIONS_START,
102 SPM_SHIM_EXCEPTIONS_SIZE,
103 MT_CODE | MT_SECURE | MT_PRIVILEGED);
104 mmap_add_region_ctx(sp_ctx->xlat_ctx_handle,
105 &sel1_exception_vectors);
106
107 mmap_add_ctx(sp_ctx->xlat_ctx_handle,
108 plat_get_secure_partition_mmap(NULL));
109
110 init_xlat_tables_ctx(sp_ctx->xlat_ctx_handle);
111
112 /*
113 * MMU-related registers
114 * ---------------------
115 */
116 xlat_ctx_t *xlat_ctx = sp_ctx->xlat_ctx_handle;
117
118 uint64_t mmu_cfg_params[MMU_CFG_PARAM_MAX];
119
120 setup_mmu_cfg((uint64_t *)&mmu_cfg_params, 0, xlat_ctx->base_table,
121 xlat_ctx->pa_max_address, xlat_ctx->va_max_address,
122 EL1_EL0_REGIME);
123
124 write_ctx_reg(get_el1_sysregs_ctx(ctx), CTX_MAIR_EL1,
125 mmu_cfg_params[MMU_CFG_MAIR]);
126
127 write_ctx_reg(get_el1_sysregs_ctx(ctx), CTX_TCR_EL1,
128 mmu_cfg_params[MMU_CFG_TCR]);
129
130 write_ctx_reg(get_el1_sysregs_ctx(ctx), CTX_TTBR0_EL1,
131 mmu_cfg_params[MMU_CFG_TTBR0]);
132
133 /* Setup SCTLR_EL1 */
134 u_register_t sctlr_el1 = read_ctx_reg(get_el1_sysregs_ctx(ctx), CTX_SCTLR_EL1);
135
136 sctlr_el1 |=
137 /*SCTLR_EL1_RES1 |*/
138 /* Don't trap DC CVAU, DC CIVAC, DC CVAC, DC CVAP, or IC IVAU */
139 SCTLR_UCI_BIT |
140 /* RW regions at xlat regime EL1&0 are forced to be XN. */
141 SCTLR_WXN_BIT |
142 /* Don't trap to EL1 execution of WFI or WFE at EL0. */
143 SCTLR_NTWI_BIT | SCTLR_NTWE_BIT |
144 /* Don't trap to EL1 accesses to CTR_EL0 from EL0. */
145 SCTLR_UCT_BIT |
146 /* Don't trap to EL1 execution of DZ ZVA at EL0. */
147 SCTLR_DZE_BIT |
148 /* Enable SP Alignment check for EL0 */
149 SCTLR_SA0_BIT |
150 /* Don't change PSTATE.PAN on taking an exception to EL1 */
151 SCTLR_SPAN_BIT |
152 /* Allow cacheable data and instr. accesses to normal memory. */
153 SCTLR_C_BIT | SCTLR_I_BIT |
154 /* Enable MMU. */
155 SCTLR_M_BIT
156 ;
157
158 sctlr_el1 &= ~(
159 /* Explicit data accesses at EL0 are little-endian. */
160 SCTLR_E0E_BIT |
161 /*
162 * Alignment fault checking disabled when at EL1 and EL0 as
163 * the UEFI spec permits unaligned accesses.
164 */
165 SCTLR_A_BIT |
166 /* Accesses to DAIF from EL0 are trapped to EL1. */
167 SCTLR_UMA_BIT
168 );
169
170 write_ctx_reg(get_el1_sysregs_ctx(ctx), CTX_SCTLR_EL1, sctlr_el1);
171
172 /*
173 * Setup other system registers
174 * ----------------------------
175 */
176
177 /* Shim Exception Vector Base Address */
178 write_ctx_reg(get_el1_sysregs_ctx(ctx), CTX_VBAR_EL1,
179 SPM_SHIM_EXCEPTIONS_PTR);
180
181 write_ctx_reg(get_el1_sysregs_ctx(ctx), CTX_CNTKCTL_EL1,
182 EL0PTEN_BIT | EL0VTEN_BIT | EL0PCTEN_BIT | EL0VCTEN_BIT);
183
184 /*
185 * FPEN: Allow the Secure Partition to access FP/SIMD registers.
186 * Note that SPM will not do any saving/restoring of these registers on
187 * behalf of the SP. This falls under the SP's responsibility.
188 * TTA: Enable access to trace registers.
189 * ZEN (v8.2): Trap SVE instructions and access to SVE registers.
190 */
191 write_ctx_reg(get_el1_sysregs_ctx(ctx), CTX_CPACR_EL1,
192 CPACR_EL1_FPEN(CPACR_EL1_FP_TRAP_NONE));
193
194 /*
195 * Prepare information in buffer shared between EL3 and S-EL0
196 * ----------------------------------------------------------
197 */
198
199 void *shared_buf_ptr = (void *) sp_boot_info->sp_shared_buf_base;
200
201 /* Copy the boot information into the shared buffer with the SP. */
202 assert((uintptr_t)shared_buf_ptr + sizeof(spm_mm_boot_info_t)
203 <= (sp_boot_info->sp_shared_buf_base + sp_boot_info->sp_shared_buf_size));
204
205 assert(sp_boot_info->sp_shared_buf_base <=
206 (UINTPTR_MAX - sp_boot_info->sp_shared_buf_size + 1));
207
208 assert(sp_boot_info != NULL);
209
210 memcpy((void *) shared_buf_ptr, (const void *) sp_boot_info,
211 sizeof(spm_mm_boot_info_t));
212
213 /* Pointer to the MP information from the platform port. */
214 spm_mm_mp_info_t *sp_mp_info =
215 ((spm_mm_boot_info_t *) shared_buf_ptr)->mp_info;
216
217 assert(sp_mp_info != NULL);
218
219 /*
220 * Point the shared buffer MP information pointer to where the info will
221 * be populated, just after the boot info.
222 */
223 ((spm_mm_boot_info_t *) shared_buf_ptr)->mp_info =
224 (spm_mm_mp_info_t *) ((uintptr_t)shared_buf_ptr
225 + sizeof(spm_mm_boot_info_t));
226
227 /*
228 * Update the shared buffer pointer to where the MP information for the
229 * payload will be populated
230 */
231 shared_buf_ptr = ((spm_mm_boot_info_t *) shared_buf_ptr)->mp_info;
232
233 /*
234 * Copy the cpu information into the shared buffer area after the boot
235 * information.
236 */
237 assert(sp_boot_info->num_cpus <= PLATFORM_CORE_COUNT);
238
239 assert((uintptr_t)shared_buf_ptr
240 <= (sp_boot_info->sp_shared_buf_base + sp_boot_info->sp_shared_buf_size -
241 (sp_boot_info->num_cpus * sizeof(*sp_mp_info))));
242
243 memcpy(shared_buf_ptr, (const void *) sp_mp_info,
244 sp_boot_info->num_cpus * sizeof(*sp_mp_info));
245
246 /*
247 * Calculate the linear indices of cores in boot information for the
248 * secure partition and flag the primary CPU
249 */
250 sp_mp_info = (spm_mm_mp_info_t *) shared_buf_ptr;
251
252 for (unsigned int index = 0; index < sp_boot_info->num_cpus; index++) {
253 u_register_t mpidr = sp_mp_info[index].mpidr;
254
255 sp_mp_info[index].linear_id = plat_core_pos_by_mpidr(mpidr);
256 if (plat_my_core_pos() == sp_mp_info[index].linear_id)
257 sp_mp_info[index].flags |= MP_INFO_FLAG_PRIMARY_CPU;
258 }
259 }
260