1 // SPDX-License-Identifier: GPL-2.0+
2 /*
3 * (C) Copyright 2007
4 * Sascha Hauer, Pengutronix
5 *
6 * (C) Copyright 2008-2009 Freescale Semiconductor, Inc.
7 */
8
9 #include <common.h>
10 #include <init.h>
11 #include <asm/io.h>
12 #include <asm/arch/imx-regs.h>
13 #include <asm/arch/crm_regs.h>
14 #include <asm/ptrace.h>
15
16 /* General purpose timers bitfields */
17 #define GPTCR_SWR (1<<15) /* Software reset */
18 #define GPTCR_FRR (1<<9) /* Freerun / restart */
19 #define GPTCR_CLKSOURCE_32 (4<<6) /* Clock source */
20 #define GPTCR_TEN (1) /* Timer enable */
21
22 /*
23 * nothing really to do with interrupts, just starts up a counter.
24 * The 32KHz 32-bit timer overruns in 134217 seconds
25 */
timer_init(void)26 int timer_init(void)
27 {
28 int i;
29 struct gpt_regs *gpt = (struct gpt_regs *)GPT1_BASE_ADDR;
30 struct ccm_regs *ccm = (struct ccm_regs *)CCM_BASE_ADDR;
31
32 /* setup GP Timer 1 */
33 writel(GPTCR_SWR, &gpt->ctrl);
34
35 writel(readl(&ccm->cgr1) | 3 << MXC_CCM_CGR1_GPT_OFFSET, &ccm->cgr1);
36
37 for (i = 0; i < 100; i++)
38 writel(0, &gpt->ctrl); /* We have no udelay by now */
39 writel(0, &gpt->pre); /* prescaler = 1 */
40 /* Freerun Mode, 32KHz input */
41 writel(readl(&gpt->ctrl) | GPTCR_CLKSOURCE_32 | GPTCR_FRR,
42 &gpt->ctrl);
43 writel(readl(&gpt->ctrl) | GPTCR_TEN, &gpt->ctrl);
44
45 return 0;
46 }
47