1 // SPDX-License-Identifier: GPL-2.0+
2 /*
3  * Copyright (C) 2014, STMicroelectronics - All Rights Reserved
4  * Author(s): Vikas Manocha, <vikas.manocha@st.com> for STMicroelectronics.
5  */
6 
7 #include <asm/io.h>
8 #include <asm/arch/hardware.h>
9 #include <asm/arch/stv0991_cgu.h>
10 #include<asm/arch/stv0991_periph.h>
11 
12 static struct stv0991_cgu_regs *const stv0991_cgu_regs = \
13 				(struct stv0991_cgu_regs *) (CGU_BASE_ADDR);
14 
enable_pll1(void)15 void enable_pll1(void)
16 {
17 	/* pll1 already configured for 1000Mhz, just need to enable it */
18 	writel(readl(&stv0991_cgu_regs->pll1_ctrl) & ~(0x01),
19 			&stv0991_cgu_regs->pll1_ctrl);
20 }
21 
clock_setup(int peripheral)22 void clock_setup(int peripheral)
23 {
24 	switch (peripheral) {
25 	case UART_CLOCK_CFG:
26 		writel(UART_CLK_CFG, &stv0991_cgu_regs->uart_freq);
27 		break;
28 	case ETH_CLOCK_CFG:
29 		enable_pll1();
30 		writel(ETH_CLK_CFG, &stv0991_cgu_regs->eth_freq);
31 
32 		/* Clock selection for ethernet tx_clk & rx_clk*/
33 		writel((readl(&stv0991_cgu_regs->eth_ctrl) & ETH_CLK_MASK)
34 				| ETH_CLK_CTRL, &stv0991_cgu_regs->eth_ctrl);
35 		break;
36 	case QSPI_CLOCK_CFG:
37 		writel(QSPI_CLK_CTRL, &stv0991_cgu_regs->qspi_freq);
38 		break;
39 	default:
40 		break;
41 	}
42 }
43