1 // SPDX-License-Identifier: GPL-2.0+
2 /*
3 * Copyright 2014-2015 Freescale Semiconductor, Inc.
4 */
5
6 #include <common.h>
7 #include <clock_legacy.h>
8 #include <cpu_func.h>
9 #include <env.h>
10 #include <image.h>
11 #include <init.h>
12 #include <log.h>
13 #include <spl.h>
14 #include <asm/cache.h>
15 #include <asm/global_data.h>
16 #include <asm/io.h>
17 #include <fsl_ifc.h>
18 #include <i2c.h>
19 #include <fsl_csu.h>
20 #include <asm/arch/fdt.h>
21 #include <asm/arch/ppa.h>
22 #include <asm/arch/soc.h>
23
24 DECLARE_GLOBAL_DATA_PTR;
25
spl_boot_device(void)26 u32 spl_boot_device(void)
27 {
28 #ifdef CONFIG_SPL_MMC_SUPPORT
29 return BOOT_DEVICE_MMC1;
30 #endif
31 #ifdef CONFIG_SPL_NAND_SUPPORT
32 return BOOT_DEVICE_NAND;
33 #endif
34 #ifdef CONFIG_QSPI_BOOT
35 return BOOT_DEVICE_NOR;
36 #endif
37 return 0;
38 }
39
40 #ifdef CONFIG_SPL_BUILD
41
42 /* Define board data structure */
43 static struct bd_info bdata __attribute__ ((section(".data")));
44
spl_board_init(void)45 void spl_board_init(void)
46 {
47 #if defined(CONFIG_NXP_ESBC) && defined(CONFIG_FSL_LSCH2)
48 /*
49 * In case of Secure Boot, the IBR configures the SMMU
50 * to allow only Secure transactions.
51 * SMMU must be reset in bypass mode.
52 * Set the ClientPD bit and Clear the USFCFG Bit
53 */
54 u32 val;
55 val = (in_le32(SMMU_SCR0) | SCR0_CLIENTPD_MASK) & ~(SCR0_USFCFG_MASK);
56 out_le32(SMMU_SCR0, val);
57 val = (in_le32(SMMU_NSCR0) | SCR0_CLIENTPD_MASK) & ~(SCR0_USFCFG_MASK);
58 out_le32(SMMU_NSCR0, val);
59 #endif
60 #ifdef CONFIG_LAYERSCAPE_NS_ACCESS
61 enable_layerscape_ns_access();
62 #endif
63 #ifdef CONFIG_SPL_FSL_LS_PPA
64 ppa_init();
65 #endif
66 }
67
board_init_f(ulong dummy)68 void board_init_f(ulong dummy)
69 {
70 icache_enable();
71 /* Clear global data */
72 memset((void *)gd, 0, sizeof(gd_t));
73 board_early_init_f();
74 timer_init();
75 #ifdef CONFIG_ARCH_LS2080A
76 env_init();
77 #endif
78 get_clocks();
79
80 preloader_console_init();
81 gd->bd = &bdata;
82
83 #ifdef CONFIG_SYS_I2C
84 #ifdef CONFIG_SPL_I2C_SUPPORT
85 i2c_init_all();
86 #endif
87 #endif
88 #ifdef CONFIG_VID
89 init_func_vid();
90 #endif
91 dram_init();
92 #ifdef CONFIG_SPL_FSL_LS_PPA
93 #ifndef CONFIG_SYS_MEM_RESERVE_SECURE
94 #error Need secure RAM for PPA
95 #endif
96 /*
97 * Secure memory location is determined in dram_init_banksize().
98 * gd->ram_size is deducted by the size of secure ram.
99 */
100 dram_init_banksize();
101
102 /*
103 * After dram_init_bank_size(), we know U-Boot only uses the first
104 * memory bank regardless how big the memory is.
105 */
106 gd->ram_top = gd->bd->bi_dram[0].start + gd->bd->bi_dram[0].size;
107
108 /*
109 * If PPA is loaded, U-Boot will resume running at EL2.
110 * Cache and MMU will be enabled. Need a place for TLB.
111 * U-Boot will be relocated to the end of available memory
112 * in first bank. At this point, we cannot know how much
113 * memory U-Boot uses. Put TLB table lower by SPL_TLB_SETBACK
114 * to avoid overlapping. As soon as the RAM version U-Boot sets
115 * up new MMU, this space is no longer needed.
116 */
117 gd->ram_top -= SPL_TLB_SETBACK;
118 gd->arch.tlb_size = PGTABLE_SIZE;
119 gd->arch.tlb_addr = (gd->ram_top - gd->arch.tlb_size) & ~(0x10000 - 1);
120 gd->arch.tlb_allocated = gd->arch.tlb_addr;
121 #endif /* CONFIG_SPL_FSL_LS_PPA */
122 #if defined(CONFIG_QSPI_AHB_INIT) && defined(CONFIG_QSPI_BOOT)
123 qspi_ahb_init();
124 #endif
125 }
126
127 #ifdef CONFIG_SPL_OS_BOOT
128 /*
129 * Return
130 * 0 if booting into OS is selected
131 * 1 if booting into U-Boot is selected
132 */
spl_start_uboot(void)133 int spl_start_uboot(void)
134 {
135 env_init();
136 if (env_get_yesno("boot_os") != 0)
137 return 0;
138
139 return 1;
140 }
141 #endif /* CONFIG_SPL_OS_BOOT */
142 #ifdef CONFIG_SPL_LOAD_FIT
board_fit_config_name_match(const char * name)143 __weak int board_fit_config_name_match(const char *name)
144 {
145 /* Just empty function now - can't decide what to choose */
146 debug("%s: %s\n", __func__, name);
147
148 return 0;
149 }
150 #endif
151 #endif /* CONFIG_SPL_BUILD */
152