1&l4_wkup { /* 0x44c00000 */ 2 compatible = "ti,am33xx-l4-wkup", "simple-bus"; 3 reg = <0x44c00000 0x800>, 4 <0x44c00800 0x800>, 5 <0x44c01000 0x400>, 6 <0x44c01400 0x400>; 7 reg-names = "ap", "la", "ia0", "ia1"; 8 #address-cells = <1>; 9 #size-cells = <1>; 10 ranges = <0x00000000 0x44c00000 0x100000>, /* segment 0 */ 11 <0x00100000 0x44d00000 0x100000>, /* segment 1 */ 12 <0x00200000 0x44e00000 0x100000>; /* segment 2 */ 13 14 segment@0 { /* 0x44c00000 */ 15 compatible = "simple-bus"; 16 #address-cells = <1>; 17 #size-cells = <1>; 18 ranges = <0x00000000 0x00000000 0x000800>, /* ap 0 */ 19 <0x00000800 0x00000800 0x000800>, /* ap 1 */ 20 <0x00001000 0x00001000 0x000400>, /* ap 2 */ 21 <0x00001400 0x00001400 0x000400>; /* ap 3 */ 22 }; 23 24 segment@100000 { /* 0x44d00000 */ 25 compatible = "simple-bus"; 26 #address-cells = <1>; 27 #size-cells = <1>; 28 ranges = <0x00000000 0x00100000 0x004000>, /* ap 4 */ 29 <0x00004000 0x00104000 0x001000>, /* ap 5 */ 30 <0x00080000 0x00180000 0x002000>, /* ap 6 */ 31 <0x00082000 0x00182000 0x001000>; /* ap 7 */ 32 33 target-module@0 { /* 0x44d00000, ap 4 28.0 */ 34 compatible = "ti,sysc-omap4", "ti,sysc"; 35 reg = <0x0 0x4>; 36 reg-names = "rev"; 37 #address-cells = <1>; 38 #size-cells = <1>; 39 ranges = <0x0 0x0 0x4000>; 40 status = "disabled"; 41 }; 42 43 target-module@80000 { /* 0x44d80000, ap 6 10.0 */ 44 compatible = "ti,sysc"; 45 status = "disabled"; 46 #address-cells = <1>; 47 #size-cells = <1>; 48 ranges = <0x0 0x80000 0x2000>; 49 }; 50 }; 51 52 segment@200000 { /* 0x44e00000 */ 53 compatible = "simple-bus"; 54 #address-cells = <1>; 55 #size-cells = <1>; 56 ranges = <0x00000000 0x00200000 0x002000>, /* ap 8 */ 57 <0x00002000 0x00202000 0x001000>, /* ap 9 */ 58 <0x00003000 0x00203000 0x001000>, /* ap 10 */ 59 <0x00004000 0x00204000 0x001000>, /* ap 11 */ 60 <0x00005000 0x00205000 0x001000>, /* ap 12 */ 61 <0x00006000 0x00206000 0x001000>, /* ap 13 */ 62 <0x00007000 0x00207000 0x001000>, /* ap 14 */ 63 <0x00008000 0x00208000 0x001000>, /* ap 15 */ 64 <0x00009000 0x00209000 0x001000>, /* ap 16 */ 65 <0x0000a000 0x0020a000 0x001000>, /* ap 17 */ 66 <0x0000b000 0x0020b000 0x001000>, /* ap 18 */ 67 <0x0000c000 0x0020c000 0x001000>, /* ap 19 */ 68 <0x0000d000 0x0020d000 0x001000>, /* ap 20 */ 69 <0x0000f000 0x0020f000 0x001000>, /* ap 21 */ 70 <0x00010000 0x00210000 0x010000>, /* ap 22 */ 71 <0x00020000 0x00220000 0x010000>, /* ap 23 */ 72 <0x00030000 0x00230000 0x001000>, /* ap 24 */ 73 <0x00031000 0x00231000 0x001000>, /* ap 25 */ 74 <0x00032000 0x00232000 0x001000>, /* ap 26 */ 75 <0x00033000 0x00233000 0x001000>, /* ap 27 */ 76 <0x00034000 0x00234000 0x001000>, /* ap 28 */ 77 <0x00035000 0x00235000 0x001000>, /* ap 29 */ 78 <0x00036000 0x00236000 0x001000>, /* ap 30 */ 79 <0x00037000 0x00237000 0x001000>, /* ap 31 */ 80 <0x00038000 0x00238000 0x001000>, /* ap 32 */ 81 <0x00039000 0x00239000 0x001000>, /* ap 33 */ 82 <0x0003a000 0x0023a000 0x001000>, /* ap 34 */ 83 <0x0003e000 0x0023e000 0x001000>, /* ap 35 */ 84 <0x0003f000 0x0023f000 0x001000>, /* ap 36 */ 85 <0x0000e000 0x0020e000 0x001000>, /* ap 37 */ 86 <0x00040000 0x00240000 0x040000>, /* ap 38 */ 87 <0x00080000 0x00280000 0x001000>; /* ap 39 */ 88 89 target-module@0 { /* 0x44e00000, ap 8 58.0 */ 90 compatible = "ti,sysc-omap4", "ti,sysc"; 91 reg = <0 0x4>; 92 reg-names = "rev"; 93 #address-cells = <1>; 94 #size-cells = <1>; 95 ranges = <0x0 0x0 0x2000>; 96 97 prcm: prcm@0 { 98 compatible = "ti,am3-prcm", "simple-bus"; 99 reg = <0 0x2000>; 100 #address-cells = <1>; 101 #size-cells = <1>; 102 ranges = <0 0 0x2000>; 103 104 prcm_clocks: clocks { 105 #address-cells = <1>; 106 #size-cells = <0>; 107 }; 108 109 prcm_clockdomains: clockdomains { 110 }; 111 }; 112 }; 113 114 target-module@3000 { /* 0x44e03000, ap 10 0a.0 */ 115 compatible = "ti,sysc"; 116 status = "disabled"; 117 #address-cells = <1>; 118 #size-cells = <1>; 119 ranges = <0x0 0x3000 0x1000>; 120 }; 121 122 target-module@5000 { /* 0x44e05000, ap 12 30.0 */ 123 compatible = "ti,sysc"; 124 status = "disabled"; 125 #address-cells = <1>; 126 #size-cells = <1>; 127 ranges = <0x0 0x5000 0x1000>; 128 }; 129 130 gpio0_target: target-module@7000 { /* 0x44e07000, ap 14 20.0 */ 131 compatible = "ti,sysc-omap2", "ti,sysc"; 132 reg = <0x7000 0x4>, 133 <0x7010 0x4>, 134 <0x7114 0x4>; 135 reg-names = "rev", "sysc", "syss"; 136 ti,sysc-mask = <(SYSC_OMAP2_ENAWAKEUP | 137 SYSC_OMAP2_SOFTRESET | 138 SYSC_OMAP2_AUTOIDLE)>; 139 ti,sysc-sidle = <SYSC_IDLE_FORCE>, 140 <SYSC_IDLE_NO>, 141 <SYSC_IDLE_SMART>, 142 <SYSC_IDLE_SMART_WKUP>; 143 ti,syss-mask = <1>; 144 /* Domains (P, C): wkup_pwrdm, l4_wkup_clkdm */ 145 clocks = <&l4_wkup_clkctrl AM3_L4_WKUP_GPIO1_CLKCTRL 0>, 146 <&l4_wkup_clkctrl AM3_L4_WKUP_GPIO1_CLKCTRL 18>; 147 clock-names = "fck", "dbclk"; 148 #address-cells = <1>; 149 #size-cells = <1>; 150 ranges = <0x0 0x7000 0x1000>; 151 152 gpio0: gpio@0 { 153 compatible = "ti,omap4-gpio"; 154 gpio-ranges = <&am33xx_pinmux 0 82 8>, 155 <&am33xx_pinmux 8 52 4>, 156 <&am33xx_pinmux 12 94 4>, 157 <&am33xx_pinmux 16 71 2>, 158 <&am33xx_pinmux 18 135 1>, 159 <&am33xx_pinmux 19 108 2>, 160 <&am33xx_pinmux 21 73 1>, 161 <&am33xx_pinmux 22 8 2>, 162 <&am33xx_pinmux 26 10 2>, 163 <&am33xx_pinmux 28 74 1>, 164 <&am33xx_pinmux 29 81 1>, 165 <&am33xx_pinmux 30 28 2>; 166 gpio-controller; 167 #gpio-cells = <2>; 168 interrupt-controller; 169 #interrupt-cells = <2>; 170 reg = <0x0 0x1000>; 171 interrupts = <96>; 172 }; 173 }; 174 175 target-module@9000 { /* 0x44e09000, ap 16 04.0 */ 176 compatible = "ti,sysc-omap2", "ti,sysc"; 177 reg = <0x9050 0x4>, 178 <0x9054 0x4>, 179 <0x9058 0x4>; 180 reg-names = "rev", "sysc", "syss"; 181 ti,sysc-mask = <(SYSC_OMAP2_ENAWAKEUP | 182 SYSC_OMAP2_SOFTRESET | 183 SYSC_OMAP2_AUTOIDLE)>; 184 ti,sysc-sidle = <SYSC_IDLE_FORCE>, 185 <SYSC_IDLE_NO>, 186 <SYSC_IDLE_SMART>, 187 <SYSC_IDLE_SMART_WKUP>; 188 /* Domains (P, C): wkup_pwrdm, l4_wkup_clkdm */ 189 clocks = <&l4_wkup_clkctrl AM3_L4_WKUP_UART1_CLKCTRL 0>; 190 clock-names = "fck"; 191 #address-cells = <1>; 192 #size-cells = <1>; 193 ranges = <0x0 0x9000 0x1000>; 194 195 uart0: serial@0 { 196 compatible = "ti,am3352-uart", "ti,omap3-uart"; 197 clock-frequency = <48000000>; 198 reg = <0x0 0x1000>; 199 interrupts = <72>; 200 status = "disabled"; 201 dmas = <&edma 26 0>, <&edma 27 0>; 202 dma-names = "tx", "rx"; 203 }; 204 }; 205 206 target-module@b000 { /* 0x44e0b000, ap 18 48.0 */ 207 compatible = "ti,sysc-omap2", "ti,sysc"; 208 reg = <0xb000 0x8>, 209 <0xb010 0x8>, 210 <0xb090 0x8>; 211 reg-names = "rev", "sysc", "syss"; 212 ti,sysc-mask = <(SYSC_OMAP2_CLOCKACTIVITY | 213 SYSC_OMAP2_ENAWAKEUP | 214 SYSC_OMAP2_SOFTRESET | 215 SYSC_OMAP2_AUTOIDLE)>; 216 ti,sysc-sidle = <SYSC_IDLE_FORCE>, 217 <SYSC_IDLE_NO>, 218 <SYSC_IDLE_SMART>, 219 <SYSC_IDLE_SMART_WKUP>; 220 ti,syss-mask = <1>; 221 /* Domains (P, C): wkup_pwrdm, l4_wkup_clkdm */ 222 clocks = <&l4_wkup_clkctrl AM3_L4_WKUP_I2C1_CLKCTRL 0>; 223 clock-names = "fck"; 224 #address-cells = <1>; 225 #size-cells = <1>; 226 ranges = <0x0 0xb000 0x1000>; 227 }; 228 229 target-module@d000 { /* 0x44e0d000, ap 20 38.0 */ 230 compatible = "ti,sysc-omap4", "ti,sysc"; 231 reg = <0xd000 0x4>, 232 <0xd010 0x4>; 233 reg-names = "rev", "sysc"; 234 ti,sysc-sidle = <SYSC_IDLE_FORCE>, 235 <SYSC_IDLE_NO>, 236 <SYSC_IDLE_SMART>, 237 <SYSC_IDLE_SMART_WKUP>; 238 /* Domains (P, C): wkup_pwrdm, l4_wkup_clkdm */ 239 clocks = <&l4_wkup_clkctrl AM3_L4_WKUP_ADC_TSC_CLKCTRL 0>; 240 clock-names = "fck"; 241 #address-cells = <1>; 242 #size-cells = <1>; 243 ranges = <0x00000000 0x0000d000 0x00001000>, 244 <0x00001000 0x0000e000 0x00001000>; 245 246 tscadc: tscadc@0 { 247 compatible = "ti,am3359-tscadc"; 248 reg = <0x0 0x1000>; 249 interrupts = <16>; 250 status = "disabled"; 251 dmas = <&edma 53 0>, <&edma 57 0>; 252 dma-names = "fifo0", "fifo1"; 253 254 tsc { 255 compatible = "ti,am3359-tsc"; 256 }; 257 am335x_adc: adc { 258 #io-channel-cells = <1>; 259 compatible = "ti,am3359-adc"; 260 }; 261 }; 262 263 }; 264 265 target-module@10000 { /* 0x44e10000, ap 22 0c.0 */ 266 compatible = "ti,sysc-omap4", "ti,sysc"; 267 reg = <0x10000 0x4>; 268 reg-names = "rev"; 269 #address-cells = <1>; 270 #size-cells = <1>; 271 ranges = <0x00000000 0x00010000 0x00010000>, 272 <0x00010000 0x00020000 0x00010000>; 273 274 scm: scm@0 { 275 compatible = "ti,am3-scm", "simple-bus"; 276 reg = <0x0 0x2000>; 277 #address-cells = <1>; 278 #size-cells = <1>; 279 #pinctrl-cells = <1>; 280 ranges = <0 0 0x2000>; 281 282 am33xx_pinmux: pinmux@800 { 283 compatible = "pinctrl-single"; 284 reg = <0x800 0x238>; 285 #pinctrl-cells = <2>; 286 pinctrl-single,register-width = <32>; 287 pinctrl-single,function-mask = <0x7f>; 288 }; 289 290 scm_conf: scm_conf@0 { 291 compatible = "syscon", "simple-bus"; 292 reg = <0x0 0x800>; 293 #address-cells = <1>; 294 #size-cells = <1>; 295 ranges = <0 0 0x800>; 296 297 phy_gmii_sel: phy-gmii-sel { 298 compatible = "ti,am3352-phy-gmii-sel"; 299 reg = <0x650 0x4>; 300 #phy-cells = <2>; 301 }; 302 303 scm_clocks: clocks { 304 #address-cells = <1>; 305 #size-cells = <0>; 306 }; 307 }; 308 309 wkup_m3_ipc: wkup_m3_ipc@1324 { 310 compatible = "ti,am3352-wkup-m3-ipc"; 311 reg = <0x1324 0x24>; 312 interrupts = <78>; 313 ti,rproc = <&wkup_m3>; 314 mboxes = <&mailbox &mbox_wkupm3>; 315 }; 316 317 edma_xbar: dma-router@f90 { 318 compatible = "ti,am335x-edma-crossbar"; 319 reg = <0xf90 0x40>; 320 #dma-cells = <3>; 321 dma-requests = <32>; 322 dma-masters = <&edma>; 323 }; 324 325 scm_clockdomains: clockdomains { 326 }; 327 }; 328 }; 329 330 timer1_target: target-module@31000 { /* 0x44e31000, ap 25 40.0 */ 331 compatible = "ti,sysc-omap2-timer", "ti,sysc"; 332 reg = <0x31000 0x4>, 333 <0x31010 0x4>, 334 <0x31014 0x4>; 335 reg-names = "rev", "sysc", "syss"; 336 ti,sysc-mask = <(SYSC_OMAP2_CLOCKACTIVITY | 337 SYSC_OMAP2_SOFTRESET | 338 SYSC_OMAP2_AUTOIDLE)>; 339 ti,sysc-sidle = <SYSC_IDLE_FORCE>, 340 <SYSC_IDLE_NO>, 341 <SYSC_IDLE_SMART>; 342 ti,syss-mask = <1>; 343 /* Domains (P, C): wkup_pwrdm, l4_wkup_clkdm */ 344 clocks = <&l4_wkup_clkctrl AM3_L4_WKUP_TIMER1_CLKCTRL 0>; 345 clock-names = "fck"; 346 #address-cells = <1>; 347 #size-cells = <1>; 348 ranges = <0x0 0x31000 0x1000>; 349 350 timer1: timer@0 { 351 compatible = "ti,am335x-timer-1ms"; 352 reg = <0x0 0x400>; 353 interrupts = <67>; 354 ti,timer-alwon; 355 clocks = <&timer1_fck>; 356 clock-names = "fck"; 357 }; 358 }; 359 360 target-module@33000 { /* 0x44e33000, ap 27 18.0 */ 361 compatible = "ti,sysc"; 362 status = "disabled"; 363 #address-cells = <1>; 364 #size-cells = <1>; 365 ranges = <0x0 0x33000 0x1000>; 366 }; 367 368 target-module@35000 { /* 0x44e35000, ap 29 50.0 */ 369 compatible = "ti,sysc-omap2", "ti,sysc"; 370 reg = <0x35000 0x4>, 371 <0x35010 0x4>, 372 <0x35014 0x4>; 373 reg-names = "rev", "sysc", "syss"; 374 ti,sysc-mask = <(SYSC_OMAP2_EMUFREE | 375 SYSC_OMAP2_SOFTRESET)>; 376 ti,sysc-sidle = <SYSC_IDLE_FORCE>, 377 <SYSC_IDLE_NO>, 378 <SYSC_IDLE_SMART>, 379 <SYSC_IDLE_SMART_WKUP>; 380 ti,syss-mask = <1>; 381 /* Domains (P, C): wkup_pwrdm, l4_wkup_clkdm */ 382 clocks = <&l4_wkup_clkctrl AM3_L4_WKUP_WD_TIMER2_CLKCTRL 0>; 383 clock-names = "fck"; 384 #address-cells = <1>; 385 #size-cells = <1>; 386 ranges = <0x0 0x35000 0x1000>; 387 }; 388 389 target-module@37000 { /* 0x44e37000, ap 31 08.0 */ 390 compatible = "ti,sysc"; 391 status = "disabled"; 392 #address-cells = <1>; 393 #size-cells = <1>; 394 ranges = <0x0 0x37000 0x1000>; 395 }; 396 397 target-module@39000 { /* 0x44e39000, ap 33 02.0 */ 398 compatible = "ti,sysc"; 399 status = "disabled"; 400 #address-cells = <1>; 401 #size-cells = <1>; 402 ranges = <0x0 0x39000 0x1000>; 403 }; 404 405 target-module@3e000 { /* 0x44e3e000, ap 35 60.0 */ 406 compatible = "ti,sysc-omap4-simple", "ti,sysc"; 407 reg = <0x3e074 0x4>, 408 <0x3e078 0x4>; 409 reg-names = "rev", "sysc"; 410 ti,sysc-sidle = <SYSC_IDLE_FORCE>, 411 <SYSC_IDLE_NO>, 412 <SYSC_IDLE_SMART>, 413 <SYSC_IDLE_SMART_WKUP>; 414 /* Domains (P, C): rtc_pwrdm, l4_rtc_clkdm */ 415 clocks = <&l4_rtc_clkctrl AM3_L4_RTC_RTC_CLKCTRL 0>; 416 clock-names = "fck"; 417 #address-cells = <1>; 418 #size-cells = <1>; 419 ranges = <0x0 0x3e000 0x1000>; 420 421 rtc: rtc@0 { 422 compatible = "ti,am3352-rtc", "ti,da830-rtc"; 423 reg = <0x0 0x1000>; 424 interrupts = <75 76>; 425 }; 426 }; 427 428 target-module@40000 { /* 0x44e40000, ap 38 68.0 */ 429 compatible = "ti,sysc"; 430 status = "disabled"; 431 #address-cells = <1>; 432 #size-cells = <1>; 433 ranges = <0x0 0x40000 0x40000>; 434 }; 435 }; 436}; 437 438&l4_fw { /* 0x47c00000 */ 439 compatible = "ti,am33xx-l4-fw", "simple-bus"; 440 reg = <0x47c00000 0x800>, 441 <0x47c00800 0x800>, 442 <0x47c01000 0x400>; 443 reg-names = "ap", "la", "ia0"; 444 #address-cells = <1>; 445 #size-cells = <1>; 446 ranges = <0x00000000 0x47c00000 0x1000000>; /* segment 0 */ 447 448 segment@0 { /* 0x47c00000 */ 449 compatible = "simple-bus"; 450 #address-cells = <1>; 451 #size-cells = <1>; 452 ranges = <0x00000000 0x00000000 0x000800>, /* ap 0 */ 453 <0x00000800 0x00000800 0x000800>, /* ap 1 */ 454 <0x00001000 0x00001000 0x000400>, /* ap 2 */ 455 <0x0000c000 0x0000c000 0x001000>, /* ap 3 */ 456 <0x0000d000 0x0000d000 0x001000>, /* ap 4 */ 457 <0x0000e000 0x0000e000 0x001000>, /* ap 5 */ 458 <0x0000f000 0x0000f000 0x001000>, /* ap 6 */ 459 <0x00010000 0x00010000 0x001000>, /* ap 7 */ 460 <0x00011000 0x00011000 0x001000>, /* ap 8 */ 461 <0x0001a000 0x0001a000 0x001000>, /* ap 9 */ 462 <0x0001b000 0x0001b000 0x001000>, /* ap 10 */ 463 <0x00024000 0x00024000 0x001000>, /* ap 11 */ 464 <0x00025000 0x00025000 0x001000>, /* ap 12 */ 465 <0x00026000 0x00026000 0x001000>, /* ap 13 */ 466 <0x00027000 0x00027000 0x001000>, /* ap 14 */ 467 <0x00030000 0x00030000 0x001000>, /* ap 15 */ 468 <0x00031000 0x00031000 0x001000>, /* ap 16 */ 469 <0x00038000 0x00038000 0x001000>, /* ap 17 */ 470 <0x00039000 0x00039000 0x001000>, /* ap 18 */ 471 <0x0003a000 0x0003a000 0x001000>, /* ap 19 */ 472 <0x0003b000 0x0003b000 0x001000>, /* ap 20 */ 473 <0x0003e000 0x0003e000 0x001000>, /* ap 21 */ 474 <0x0003f000 0x0003f000 0x001000>, /* ap 22 */ 475 <0x0003c000 0x0003c000 0x001000>, /* ap 23 */ 476 <0x00040000 0x00040000 0x001000>, /* ap 24 */ 477 <0x00046000 0x00046000 0x001000>, /* ap 25 */ 478 <0x00047000 0x00047000 0x001000>, /* ap 26 */ 479 <0x00044000 0x00044000 0x001000>, /* ap 27 */ 480 <0x00045000 0x00045000 0x001000>, /* ap 28 */ 481 <0x00028000 0x00028000 0x001000>, /* ap 29 */ 482 <0x00029000 0x00029000 0x001000>, /* ap 30 */ 483 <0x00032000 0x00032000 0x001000>, /* ap 31 */ 484 <0x00033000 0x00033000 0x001000>, /* ap 32 */ 485 <0x0003d000 0x0003d000 0x001000>, /* ap 33 */ 486 <0x00041000 0x00041000 0x001000>, /* ap 34 */ 487 <0x00042000 0x00042000 0x001000>, /* ap 35 */ 488 <0x00043000 0x00043000 0x001000>, /* ap 36 */ 489 <0x00014000 0x00014000 0x001000>, /* ap 37 */ 490 <0x00015000 0x00015000 0x001000>; /* ap 38 */ 491 492 target-module@c000 { /* 0x47c0c000, ap 3 04.0 */ 493 compatible = "ti,sysc"; 494 status = "disabled"; 495 #address-cells = <1>; 496 #size-cells = <1>; 497 ranges = <0x0 0xc000 0x1000>; 498 }; 499 500 target-module@e000 { /* 0x47c0e000, ap 5 0c.0 */ 501 compatible = "ti,sysc"; 502 status = "disabled"; 503 #address-cells = <1>; 504 #size-cells = <1>; 505 ranges = <0x0 0xe000 0x1000>; 506 }; 507 508 target-module@10000 { /* 0x47c10000, ap 7 20.0 */ 509 compatible = "ti,sysc"; 510 status = "disabled"; 511 #address-cells = <1>; 512 #size-cells = <1>; 513 ranges = <0x0 0x10000 0x1000>; 514 }; 515 516 target-module@14000 { /* 0x47c14000, ap 37 3c.0 */ 517 compatible = "ti,sysc"; 518 status = "disabled"; 519 #address-cells = <1>; 520 #size-cells = <1>; 521 ranges = <0x0 0x14000 0x1000>; 522 }; 523 524 target-module@1a000 { /* 0x47c1a000, ap 9 08.0 */ 525 compatible = "ti,sysc"; 526 status = "disabled"; 527 #address-cells = <1>; 528 #size-cells = <1>; 529 ranges = <0x0 0x1a000 0x1000>; 530 }; 531 532 target-module@24000 { /* 0x47c24000, ap 11 28.0 */ 533 compatible = "ti,sysc"; 534 status = "disabled"; 535 #address-cells = <1>; 536 #size-cells = <1>; 537 ranges = <0x0 0x24000 0x1000>; 538 }; 539 540 target-module@26000 { /* 0x47c26000, ap 13 30.0 */ 541 compatible = "ti,sysc"; 542 status = "disabled"; 543 #address-cells = <1>; 544 #size-cells = <1>; 545 ranges = <0x0 0x26000 0x1000>; 546 }; 547 548 target-module@28000 { /* 0x47c28000, ap 29 40.0 */ 549 compatible = "ti,sysc"; 550 status = "disabled"; 551 #address-cells = <1>; 552 #size-cells = <1>; 553 ranges = <0x0 0x28000 0x1000>; 554 }; 555 556 target-module@30000 { /* 0x47c30000, ap 15 14.0 */ 557 compatible = "ti,sysc"; 558 status = "disabled"; 559 #address-cells = <1>; 560 #size-cells = <1>; 561 ranges = <0x0 0x30000 0x1000>; 562 }; 563 564 target-module@32000 { /* 0x47c32000, ap 31 06.0 */ 565 compatible = "ti,sysc"; 566 status = "disabled"; 567 #address-cells = <1>; 568 #size-cells = <1>; 569 ranges = <0x0 0x32000 0x1000>; 570 }; 571 572 target-module@38000 { /* 0x47c38000, ap 17 18.0 */ 573 compatible = "ti,sysc"; 574 status = "disabled"; 575 #address-cells = <1>; 576 #size-cells = <1>; 577 ranges = <0x0 0x38000 0x1000>; 578 }; 579 580 target-module@3a000 { /* 0x47c3a000, ap 19 1c.0 */ 581 compatible = "ti,sysc"; 582 status = "disabled"; 583 #address-cells = <1>; 584 #size-cells = <1>; 585 ranges = <0x0 0x3a000 0x1000>; 586 }; 587 588 target-module@3c000 { /* 0x47c3c000, ap 23 38.0 */ 589 compatible = "ti,sysc"; 590 status = "disabled"; 591 #address-cells = <1>; 592 #size-cells = <1>; 593 ranges = <0x0 0x3c000 0x1000>; 594 }; 595 596 target-module@3e000 { /* 0x47c3e000, ap 21 10.0 */ 597 compatible = "ti,sysc"; 598 status = "disabled"; 599 #address-cells = <1>; 600 #size-cells = <1>; 601 ranges = <0x0 0x3e000 0x1000>; 602 }; 603 604 target-module@40000 { /* 0x47c40000, ap 24 02.0 */ 605 compatible = "ti,sysc"; 606 status = "disabled"; 607 #address-cells = <1>; 608 #size-cells = <1>; 609 ranges = <0x0 0x40000 0x1000>; 610 }; 611 612 target-module@42000 { /* 0x47c42000, ap 35 34.0 */ 613 compatible = "ti,sysc"; 614 status = "disabled"; 615 #address-cells = <1>; 616 #size-cells = <1>; 617 ranges = <0x0 0x42000 0x1000>; 618 }; 619 620 target-module@44000 { /* 0x47c44000, ap 27 24.0 */ 621 compatible = "ti,sysc"; 622 status = "disabled"; 623 #address-cells = <1>; 624 #size-cells = <1>; 625 ranges = <0x0 0x44000 0x1000>; 626 }; 627 628 target-module@46000 { /* 0x47c46000, ap 25 2c.0 */ 629 compatible = "ti,sysc"; 630 status = "disabled"; 631 #address-cells = <1>; 632 #size-cells = <1>; 633 ranges = <0x0 0x46000 0x1000>; 634 }; 635 }; 636}; 637 638&l4_fast { /* 0x4a000000 */ 639 compatible = "ti,am33xx-l4-fast", "simple-bus"; 640 reg = <0x4a000000 0x800>, 641 <0x4a000800 0x800>, 642 <0x4a001000 0x400>; 643 reg-names = "ap", "la", "ia0"; 644 #address-cells = <1>; 645 #size-cells = <1>; 646 ranges = <0x00000000 0x4a000000 0x1000000>; /* segment 0 */ 647 648 segment@0 { /* 0x4a000000 */ 649 compatible = "simple-bus"; 650 #address-cells = <1>; 651 #size-cells = <1>; 652 ranges = <0x00000000 0x00000000 0x000800>, /* ap 0 */ 653 <0x00000800 0x00000800 0x000800>, /* ap 1 */ 654 <0x00001000 0x00001000 0x000400>, /* ap 2 */ 655 <0x00100000 0x00100000 0x008000>, /* ap 3 */ 656 <0x00108000 0x00108000 0x001000>, /* ap 4 */ 657 <0x00180000 0x00180000 0x020000>, /* ap 5 */ 658 <0x001a0000 0x001a0000 0x001000>, /* ap 6 */ 659 <0x00200000 0x00200000 0x080000>, /* ap 7 */ 660 <0x00280000 0x00280000 0x001000>, /* ap 8 */ 661 <0x00300000 0x00300000 0x080000>, /* ap 9 */ 662 <0x00380000 0x00380000 0x001000>; /* ap 10 */ 663 664 target-module@100000 { /* 0x4a100000, ap 3 08.0 */ 665 compatible = "ti,sysc-omap4-simple", "ti,sysc"; 666 reg = <0x101200 0x4>, 667 <0x101208 0x4>, 668 <0x101204 0x4>; 669 reg-names = "rev", "sysc", "syss"; 670 ti,sysc-mask = <0>; 671 ti,sysc-midle = <SYSC_IDLE_FORCE>, 672 <SYSC_IDLE_NO>; 673 ti,sysc-sidle = <SYSC_IDLE_FORCE>, 674 <SYSC_IDLE_NO>; 675 ti,syss-mask = <1>; 676 clocks = <&cpsw_125mhz_clkctrl AM3_CPSW_125MHZ_CPGMAC0_CLKCTRL 0>; 677 clock-names = "fck"; 678 #address-cells = <1>; 679 #size-cells = <1>; 680 ranges = <0x0 0x100000 0x8000>; 681 }; 682 683 target-module@180000 { /* 0x4a180000, ap 5 10.0 */ 684 compatible = "ti,sysc"; 685 status = "disabled"; 686 #address-cells = <1>; 687 #size-cells = <1>; 688 ranges = <0x0 0x180000 0x20000>; 689 }; 690 691 target-module@200000 { /* 0x4a200000, ap 7 02.0 */ 692 compatible = "ti,sysc"; 693 status = "disabled"; 694 #address-cells = <1>; 695 #size-cells = <1>; 696 ranges = <0x0 0x200000 0x80000>; 697 }; 698 699 pruss_tm: target-module@300000 { /* 0x4a300000, ap 9 04.0 */ 700 compatible = "ti,sysc-pruss", "ti,sysc"; 701 reg = <0x326000 0x4>, 702 <0x326004 0x4>; 703 reg-names = "rev", "sysc"; 704 ti,sysc-mask = <(SYSC_PRUSS_STANDBY_INIT | 705 SYSC_PRUSS_SUB_MWAIT)>; 706 ti,sysc-midle = <SYSC_IDLE_FORCE>, 707 <SYSC_IDLE_NO>, 708 <SYSC_IDLE_SMART>; 709 ti,sysc-sidle = <SYSC_IDLE_FORCE>, 710 <SYSC_IDLE_NO>, 711 <SYSC_IDLE_SMART>; 712 clocks = <&pruss_ocp_clkctrl AM3_PRUSS_OCP_PRUSS_CLKCTRL 0>; 713 clock-names = "fck"; 714 resets = <&prm_per 1>; 715 reset-names = "rstctrl"; 716 #address-cells = <1>; 717 #size-cells = <1>; 718 ranges = <0x0 0x300000 0x80000>; 719 status = "disabled"; 720 }; 721 }; 722}; 723 724&l4_mpuss { /* 0x4b140000 */ 725 compatible = "ti,am33xx-l4-mpuss", "simple-bus"; 726 reg = <0x4b144400 0x100>, 727 <0x4b144800 0x400>; 728 reg-names = "la", "ap"; 729 #address-cells = <1>; 730 #size-cells = <1>; 731 ranges = <0x00000000 0x4b140000 0x008000>; /* segment 0 */ 732 733 segment@0 { /* 0x4b140000 */ 734 compatible = "simple-bus"; 735 #address-cells = <1>; 736 #size-cells = <1>; 737 ranges = <0x00004800 0x00004800 0x000400>, /* ap 0 */ 738 <0x00001000 0x00001000 0x001000>, /* ap 1 */ 739 <0x00002000 0x00002000 0x001000>, /* ap 2 */ 740 <0x00004000 0x00004000 0x000400>, /* ap 3 */ 741 <0x00005000 0x00005000 0x000400>, /* ap 4 */ 742 <0x00000000 0x00000000 0x001000>, /* ap 5 */ 743 <0x00003000 0x00003000 0x001000>, /* ap 6 */ 744 <0x00000800 0x00000800 0x000800>; /* ap 7 */ 745 746 target-module@0 { /* 0x4b140000, ap 5 02.2 */ 747 compatible = "ti,sysc"; 748 status = "disabled"; 749 #address-cells = <1>; 750 #size-cells = <1>; 751 ranges = <0x00000000 0x00000000 0x00001000>, 752 <0x00001000 0x00001000 0x00001000>, 753 <0x00002000 0x00002000 0x00001000>; 754 }; 755 756 target-module@3000 { /* 0x4b143000, ap 6 04.0 */ 757 compatible = "ti,sysc"; 758 status = "disabled"; 759 #address-cells = <1>; 760 #size-cells = <1>; 761 ranges = <0x0 0x3000 0x1000>; 762 }; 763 }; 764}; 765 766&l4_per { /* 0x48000000 */ 767 compatible = "ti,am33xx-l4-per", "simple-bus"; 768 reg = <0x48000000 0x800>, 769 <0x48000800 0x800>, 770 <0x48001000 0x400>, 771 <0x48001400 0x400>, 772 <0x48001800 0x400>, 773 <0x48001c00 0x400>; 774 reg-names = "ap", "la", "ia0", "ia1", "ia2", "ia3"; 775 #address-cells = <1>; 776 #size-cells = <1>; 777 ranges = <0x00000000 0x48000000 0x100000>, /* segment 0 */ 778 <0x00100000 0x48100000 0x100000>, /* segment 1 */ 779 <0x00200000 0x48200000 0x100000>, /* segment 2 */ 780 <0x00300000 0x48300000 0x100000>, /* segment 3 */ 781 <0x46000000 0x46000000 0x400000>, /* l3 data port */ 782 <0x46400000 0x46400000 0x400000>; /* l3 data port */ 783 784 segment@0 { /* 0x48000000 */ 785 compatible = "simple-bus"; 786 #address-cells = <1>; 787 #size-cells = <1>; 788 ranges = <0x00000000 0x00000000 0x000800>, /* ap 0 */ 789 <0x00000800 0x00000800 0x000800>, /* ap 1 */ 790 <0x00001000 0x00001000 0x000400>, /* ap 2 */ 791 <0x00001400 0x00001400 0x000400>, /* ap 3 */ 792 <0x00001800 0x00001800 0x000400>, /* ap 4 */ 793 <0x00001c00 0x00001c00 0x000400>, /* ap 5 */ 794 <0x00008000 0x00008000 0x001000>, /* ap 6 */ 795 <0x00009000 0x00009000 0x001000>, /* ap 7 */ 796 <0x00016000 0x00016000 0x001000>, /* ap 8 */ 797 <0x00017000 0x00017000 0x001000>, /* ap 9 */ 798 <0x00022000 0x00022000 0x001000>, /* ap 10 */ 799 <0x00023000 0x00023000 0x001000>, /* ap 11 */ 800 <0x00024000 0x00024000 0x001000>, /* ap 12 */ 801 <0x00025000 0x00025000 0x001000>, /* ap 13 */ 802 <0x0002a000 0x0002a000 0x001000>, /* ap 14 */ 803 <0x0002b000 0x0002b000 0x001000>, /* ap 15 */ 804 <0x00038000 0x00038000 0x002000>, /* ap 16 */ 805 <0x0003a000 0x0003a000 0x001000>, /* ap 17 */ 806 <0x00014000 0x00014000 0x001000>, /* ap 18 */ 807 <0x00015000 0x00015000 0x001000>, /* ap 19 */ 808 <0x0003c000 0x0003c000 0x002000>, /* ap 20 */ 809 <0x0003e000 0x0003e000 0x001000>, /* ap 21 */ 810 <0x00040000 0x00040000 0x001000>, /* ap 22 */ 811 <0x00041000 0x00041000 0x001000>, /* ap 23 */ 812 <0x00042000 0x00042000 0x001000>, /* ap 24 */ 813 <0x00043000 0x00043000 0x001000>, /* ap 25 */ 814 <0x00044000 0x00044000 0x001000>, /* ap 26 */ 815 <0x00045000 0x00045000 0x001000>, /* ap 27 */ 816 <0x00046000 0x00046000 0x001000>, /* ap 28 */ 817 <0x00047000 0x00047000 0x001000>, /* ap 29 */ 818 <0x00048000 0x00048000 0x001000>, /* ap 30 */ 819 <0x00049000 0x00049000 0x001000>, /* ap 31 */ 820 <0x0004c000 0x0004c000 0x001000>, /* ap 32 */ 821 <0x0004d000 0x0004d000 0x001000>, /* ap 33 */ 822 <0x00050000 0x00050000 0x002000>, /* ap 34 */ 823 <0x00052000 0x00052000 0x001000>, /* ap 35 */ 824 <0x00060000 0x00060000 0x001000>, /* ap 36 */ 825 <0x00061000 0x00061000 0x001000>, /* ap 37 */ 826 <0x00080000 0x00080000 0x010000>, /* ap 38 */ 827 <0x00090000 0x00090000 0x001000>, /* ap 39 */ 828 <0x000a0000 0x000a0000 0x010000>, /* ap 40 */ 829 <0x000b0000 0x000b0000 0x001000>, /* ap 41 */ 830 <0x00030000 0x00030000 0x001000>, /* ap 77 */ 831 <0x00031000 0x00031000 0x001000>, /* ap 78 */ 832 <0x0004a000 0x0004a000 0x001000>, /* ap 85 */ 833 <0x0004b000 0x0004b000 0x001000>, /* ap 86 */ 834 <0x000c8000 0x000c8000 0x001000>, /* ap 87 */ 835 <0x000c9000 0x000c9000 0x001000>, /* ap 88 */ 836 <0x000cc000 0x000cc000 0x001000>, /* ap 89 */ 837 <0x000cd000 0x000cd000 0x001000>, /* ap 90 */ 838 <0x000ca000 0x000ca000 0x001000>, /* ap 91 */ 839 <0x000cb000 0x000cb000 0x001000>, /* ap 92 */ 840 <0x46000000 0x46000000 0x400000>, /* l3 data port */ 841 <0x46400000 0x46400000 0x400000>; /* l3 data port */ 842 843 target-module@8000 { /* 0x48008000, ap 6 10.0 */ 844 compatible = "ti,sysc"; 845 status = "disabled"; 846 #address-cells = <1>; 847 #size-cells = <1>; 848 ranges = <0x0 0x8000 0x1000>; 849 }; 850 851 target-module@14000 { /* 0x48014000, ap 18 58.0 */ 852 compatible = "ti,sysc"; 853 status = "disabled"; 854 #address-cells = <1>; 855 #size-cells = <1>; 856 ranges = <0x0 0x14000 0x1000>; 857 }; 858 859 target-module@16000 { /* 0x48016000, ap 8 3c.0 */ 860 compatible = "ti,sysc"; 861 status = "disabled"; 862 #address-cells = <1>; 863 #size-cells = <1>; 864 ranges = <0x0 0x16000 0x1000>; 865 }; 866 867 target-module@22000 { /* 0x48022000, ap 10 12.0 */ 868 compatible = "ti,sysc-omap2", "ti,sysc"; 869 reg = <0x22050 0x4>, 870 <0x22054 0x4>, 871 <0x22058 0x4>; 872 reg-names = "rev", "sysc", "syss"; 873 ti,sysc-mask = <(SYSC_OMAP2_ENAWAKEUP | 874 SYSC_OMAP2_SOFTRESET | 875 SYSC_OMAP2_AUTOIDLE)>; 876 ti,sysc-sidle = <SYSC_IDLE_FORCE>, 877 <SYSC_IDLE_NO>, 878 <SYSC_IDLE_SMART>, 879 <SYSC_IDLE_SMART_WKUP>; 880 /* Domains (P, C): per_pwrdm, l4ls_clkdm */ 881 clocks = <&l4ls_clkctrl AM3_L4LS_UART2_CLKCTRL 0>; 882 clock-names = "fck"; 883 #address-cells = <1>; 884 #size-cells = <1>; 885 ranges = <0x0 0x22000 0x1000>; 886 887 uart1: serial@0 { 888 compatible = "ti,am3352-uart", "ti,omap3-uart"; 889 clock-frequency = <48000000>; 890 reg = <0x0 0x1000>; 891 interrupts = <73>; 892 status = "disabled"; 893 dmas = <&edma 28 0>, <&edma 29 0>; 894 dma-names = "tx", "rx"; 895 }; 896 }; 897 898 target-module@24000 { /* 0x48024000, ap 12 14.0 */ 899 compatible = "ti,sysc-omap2", "ti,sysc"; 900 reg = <0x24050 0x4>, 901 <0x24054 0x4>, 902 <0x24058 0x4>; 903 reg-names = "rev", "sysc", "syss"; 904 ti,sysc-mask = <(SYSC_OMAP2_ENAWAKEUP | 905 SYSC_OMAP2_SOFTRESET | 906 SYSC_OMAP2_AUTOIDLE)>; 907 ti,sysc-sidle = <SYSC_IDLE_FORCE>, 908 <SYSC_IDLE_NO>, 909 <SYSC_IDLE_SMART>, 910 <SYSC_IDLE_SMART_WKUP>; 911 /* Domains (P, C): per_pwrdm, l4ls_clkdm */ 912 clocks = <&l4ls_clkctrl AM3_L4LS_UART3_CLKCTRL 0>; 913 clock-names = "fck"; 914 #address-cells = <1>; 915 #size-cells = <1>; 916 ranges = <0x0 0x24000 0x1000>; 917 918 uart2: serial@0 { 919 compatible = "ti,am3352-uart", "ti,omap3-uart"; 920 clock-frequency = <48000000>; 921 reg = <0x0 0x1000>; 922 interrupts = <74>; 923 status = "disabled"; 924 dmas = <&edma 30 0>, <&edma 31 0>; 925 dma-names = "tx", "rx"; 926 }; 927 }; 928 929 target-module@2a000 { /* 0x4802a000, ap 14 2a.0 */ 930 compatible = "ti,sysc-omap2", "ti,sysc"; 931 reg = <0x2a000 0x8>, 932 <0x2a010 0x8>, 933 <0x2a090 0x8>; 934 reg-names = "rev", "sysc", "syss"; 935 ti,sysc-mask = <(SYSC_OMAP2_CLOCKACTIVITY | 936 SYSC_OMAP2_ENAWAKEUP | 937 SYSC_OMAP2_SOFTRESET | 938 SYSC_OMAP2_AUTOIDLE)>; 939 ti,sysc-sidle = <SYSC_IDLE_FORCE>, 940 <SYSC_IDLE_NO>, 941 <SYSC_IDLE_SMART>, 942 <SYSC_IDLE_SMART_WKUP>; 943 ti,syss-mask = <1>; 944 /* Domains (P, C): per_pwrdm, l4ls_clkdm */ 945 clocks = <&l4ls_clkctrl AM3_L4LS_I2C2_CLKCTRL 0>; 946 clock-names = "fck"; 947 #address-cells = <1>; 948 #size-cells = <1>; 949 ranges = <0x0 0x2a000 0x1000>; 950 }; 951 952 target-module@30000 { /* 0x48030000, ap 77 08.0 */ 953 compatible = "ti,sysc-omap2", "ti,sysc"; 954 reg = <0x30000 0x4>, 955 <0x30110 0x4>, 956 <0x30114 0x4>; 957 reg-names = "rev", "sysc", "syss"; 958 ti,sysc-mask = <(SYSC_OMAP2_CLOCKACTIVITY | 959 SYSC_OMAP2_SOFTRESET | 960 SYSC_OMAP2_AUTOIDLE)>; 961 ti,sysc-sidle = <SYSC_IDLE_FORCE>, 962 <SYSC_IDLE_NO>, 963 <SYSC_IDLE_SMART>; 964 ti,syss-mask = <1>; 965 /* Domains (P, C): per_pwrdm, l4ls_clkdm */ 966 clocks = <&l4ls_clkctrl AM3_L4LS_SPI0_CLKCTRL 0>; 967 clock-names = "fck"; 968 #address-cells = <1>; 969 #size-cells = <1>; 970 ranges = <0x0 0x30000 0x1000>; 971 972 spi0: spi@0 { 973 compatible = "ti,omap4-mcspi"; 974 #address-cells = <1>; 975 #size-cells = <0>; 976 reg = <0x0 0x400>; 977 interrupts = <65>; 978 ti,spi-num-cs = <2>; 979 dmas = <&edma 16 0 980 &edma 17 0 981 &edma 18 0 982 &edma 19 0>; 983 dma-names = "tx0", "rx0", "tx1", "rx1"; 984 status = "disabled"; 985 }; 986 }; 987 988 target-module@38000 { /* 0x48038000, ap 16 02.0 */ 989 compatible = "ti,sysc-omap4-simple", "ti,sysc"; 990 reg = <0x38000 0x4>, 991 <0x38004 0x4>; 992 reg-names = "rev", "sysc"; 993 ti,sysc-sidle = <SYSC_IDLE_FORCE>, 994 <SYSC_IDLE_NO>, 995 <SYSC_IDLE_SMART>; 996 /* Domains (P, C): per_pwrdm, l3s_clkdm */ 997 clocks = <&l3s_clkctrl AM3_L3S_MCASP0_CLKCTRL 0>; 998 clock-names = "fck"; 999 #address-cells = <1>; 1000 #size-cells = <1>; 1001 ranges = <0x0 0x38000 0x2000>, 1002 <0x46000000 0x46000000 0x400000>; 1003 1004 mcasp0: mcasp@0 { 1005 compatible = "ti,am33xx-mcasp-audio"; 1006 reg = <0x0 0x2000>, 1007 <0x46000000 0x400000>; 1008 reg-names = "mpu", "dat"; 1009 interrupts = <80>, <81>; 1010 interrupt-names = "tx", "rx"; 1011 status = "disabled"; 1012 dmas = <&edma 8 2>, 1013 <&edma 9 2>; 1014 dma-names = "tx", "rx"; 1015 }; 1016 }; 1017 1018 target-module@3c000 { /* 0x4803c000, ap 20 32.0 */ 1019 compatible = "ti,sysc-omap4-simple", "ti,sysc"; 1020 reg = <0x3c000 0x4>, 1021 <0x3c004 0x4>; 1022 reg-names = "rev", "sysc"; 1023 ti,sysc-sidle = <SYSC_IDLE_FORCE>, 1024 <SYSC_IDLE_NO>, 1025 <SYSC_IDLE_SMART>; 1026 /* Domains (P, C): per_pwrdm, l3s_clkdm */ 1027 clocks = <&l3s_clkctrl AM3_L3S_MCASP1_CLKCTRL 0>; 1028 clock-names = "fck"; 1029 #address-cells = <1>; 1030 #size-cells = <1>; 1031 ranges = <0x0 0x3c000 0x2000>, 1032 <0x46400000 0x46400000 0x400000>; 1033 1034 mcasp1: mcasp@0 { 1035 compatible = "ti,am33xx-mcasp-audio"; 1036 reg = <0x0 0x2000>, 1037 <0x46400000 0x400000>; 1038 reg-names = "mpu", "dat"; 1039 interrupts = <82>, <83>; 1040 interrupt-names = "tx", "rx"; 1041 status = "disabled"; 1042 dmas = <&edma 10 2>, 1043 <&edma 11 2>; 1044 dma-names = "tx", "rx"; 1045 }; 1046 }; 1047 1048 timer2_target: target-module@40000 { /* 0x48040000, ap 22 1e.0 */ 1049 compatible = "ti,sysc-omap4-timer", "ti,sysc"; 1050 reg = <0x40000 0x4>, 1051 <0x40010 0x4>, 1052 <0x40014 0x4>; 1053 reg-names = "rev", "sysc", "syss"; 1054 ti,sysc-mask = <SYSC_OMAP4_SOFTRESET>; 1055 ti,sysc-sidle = <SYSC_IDLE_FORCE>, 1056 <SYSC_IDLE_NO>, 1057 <SYSC_IDLE_SMART>, 1058 <SYSC_IDLE_SMART_WKUP>; 1059 /* Domains (P, C): per_pwrdm, l4ls_clkdm */ 1060 clocks = <&l4ls_clkctrl AM3_L4LS_TIMER2_CLKCTRL 0>; 1061 clock-names = "fck"; 1062 #address-cells = <1>; 1063 #size-cells = <1>; 1064 ranges = <0x0 0x40000 0x1000>; 1065 1066 timer2: timer@0 { 1067 compatible = "ti,am335x-timer"; 1068 reg = <0x0 0x400>; 1069 interrupts = <68>; 1070 clocks = <&timer2_fck>; 1071 clock-names = "fck"; 1072 }; 1073 }; 1074 1075 target-module@42000 { /* 0x48042000, ap 24 1c.0 */ 1076 compatible = "ti,sysc-omap4-timer", "ti,sysc"; 1077 reg = <0x42000 0x4>, 1078 <0x42010 0x4>, 1079 <0x42014 0x4>; 1080 reg-names = "rev", "sysc", "syss"; 1081 ti,sysc-mask = <SYSC_OMAP4_SOFTRESET>; 1082 ti,sysc-sidle = <SYSC_IDLE_FORCE>, 1083 <SYSC_IDLE_NO>, 1084 <SYSC_IDLE_SMART>, 1085 <SYSC_IDLE_SMART_WKUP>; 1086 /* Domains (P, C): per_pwrdm, l4ls_clkdm */ 1087 clocks = <&l4ls_clkctrl AM3_L4LS_TIMER3_CLKCTRL 0>; 1088 clock-names = "fck"; 1089 #address-cells = <1>; 1090 #size-cells = <1>; 1091 ranges = <0x0 0x42000 0x1000>; 1092 1093 timer3: timer@0 { 1094 compatible = "ti,am335x-timer"; 1095 reg = <0x0 0x400>; 1096 interrupts = <69>; 1097 }; 1098 }; 1099 1100 target-module@44000 { /* 0x48044000, ap 26 26.0 */ 1101 compatible = "ti,sysc-omap4-timer", "ti,sysc"; 1102 reg = <0x44000 0x4>, 1103 <0x44010 0x4>, 1104 <0x44014 0x4>; 1105 reg-names = "rev", "sysc", "syss"; 1106 ti,sysc-mask = <SYSC_OMAP4_SOFTRESET>; 1107 ti,sysc-sidle = <SYSC_IDLE_FORCE>, 1108 <SYSC_IDLE_NO>, 1109 <SYSC_IDLE_SMART>, 1110 <SYSC_IDLE_SMART_WKUP>; 1111 /* Domains (P, C): per_pwrdm, l4ls_clkdm */ 1112 clocks = <&l4ls_clkctrl AM3_L4LS_TIMER4_CLKCTRL 0>; 1113 clock-names = "fck"; 1114 #address-cells = <1>; 1115 #size-cells = <1>; 1116 ranges = <0x0 0x44000 0x1000>; 1117 1118 timer4: timer@0 { 1119 compatible = "ti,am335x-timer"; 1120 reg = <0x0 0x400>; 1121 interrupts = <92>; 1122 ti,timer-pwm; 1123 }; 1124 }; 1125 1126 target-module@46000 { /* 0x48046000, ap 28 28.0 */ 1127 compatible = "ti,sysc-omap4-timer", "ti,sysc"; 1128 reg = <0x46000 0x4>, 1129 <0x46010 0x4>, 1130 <0x46014 0x4>; 1131 reg-names = "rev", "sysc", "syss"; 1132 ti,sysc-mask = <SYSC_OMAP4_SOFTRESET>; 1133 ti,sysc-sidle = <SYSC_IDLE_FORCE>, 1134 <SYSC_IDLE_NO>, 1135 <SYSC_IDLE_SMART>, 1136 <SYSC_IDLE_SMART_WKUP>; 1137 /* Domains (P, C): per_pwrdm, l4ls_clkdm */ 1138 clocks = <&l4ls_clkctrl AM3_L4LS_TIMER5_CLKCTRL 0>; 1139 clock-names = "fck"; 1140 #address-cells = <1>; 1141 #size-cells = <1>; 1142 ranges = <0x0 0x46000 0x1000>; 1143 1144 timer5: timer@0 { 1145 compatible = "ti,am335x-timer"; 1146 reg = <0x0 0x400>; 1147 interrupts = <93>; 1148 ti,timer-pwm; 1149 }; 1150 }; 1151 1152 target-module@48000 { /* 0x48048000, ap 30 22.0 */ 1153 compatible = "ti,sysc-omap4-timer", "ti,sysc"; 1154 reg = <0x48000 0x4>, 1155 <0x48010 0x4>, 1156 <0x48014 0x4>; 1157 reg-names = "rev", "sysc", "syss"; 1158 ti,sysc-mask = <SYSC_OMAP4_SOFTRESET>; 1159 ti,sysc-sidle = <SYSC_IDLE_FORCE>, 1160 <SYSC_IDLE_NO>, 1161 <SYSC_IDLE_SMART>, 1162 <SYSC_IDLE_SMART_WKUP>; 1163 /* Domains (P, C): per_pwrdm, l4ls_clkdm */ 1164 clocks = <&l4ls_clkctrl AM3_L4LS_TIMER6_CLKCTRL 0>; 1165 clock-names = "fck"; 1166 #address-cells = <1>; 1167 #size-cells = <1>; 1168 ranges = <0x0 0x48000 0x1000>; 1169 1170 timer6: timer@0 { 1171 compatible = "ti,am335x-timer"; 1172 reg = <0x0 0x400>; 1173 interrupts = <94>; 1174 ti,timer-pwm; 1175 }; 1176 }; 1177 1178 target-module@4a000 { /* 0x4804a000, ap 85 60.0 */ 1179 compatible = "ti,sysc-omap4-timer", "ti,sysc"; 1180 reg = <0x4a000 0x4>, 1181 <0x4a010 0x4>, 1182 <0x4a014 0x4>; 1183 reg-names = "rev", "sysc", "syss"; 1184 ti,sysc-mask = <SYSC_OMAP4_SOFTRESET>; 1185 ti,sysc-sidle = <SYSC_IDLE_FORCE>, 1186 <SYSC_IDLE_NO>, 1187 <SYSC_IDLE_SMART>, 1188 <SYSC_IDLE_SMART_WKUP>; 1189 /* Domains (P, C): per_pwrdm, l4ls_clkdm */ 1190 clocks = <&l4ls_clkctrl AM3_L4LS_TIMER7_CLKCTRL 0>; 1191 clock-names = "fck"; 1192 #address-cells = <1>; 1193 #size-cells = <1>; 1194 ranges = <0x0 0x4a000 0x1000>; 1195 1196 timer7: timer@0 { 1197 compatible = "ti,am335x-timer"; 1198 reg = <0x0 0x400>; 1199 interrupts = <95>; 1200 ti,timer-pwm; 1201 }; 1202 }; 1203 1204 target-module@4c000 { /* 0x4804c000, ap 32 36.0 */ 1205 compatible = "ti,sysc-omap2", "ti,sysc"; 1206 reg = <0x4c000 0x4>, 1207 <0x4c010 0x4>, 1208 <0x4c114 0x4>; 1209 reg-names = "rev", "sysc", "syss"; 1210 ti,sysc-mask = <(SYSC_OMAP2_ENAWAKEUP | 1211 SYSC_OMAP2_SOFTRESET | 1212 SYSC_OMAP2_AUTOIDLE)>; 1213 ti,sysc-sidle = <SYSC_IDLE_FORCE>, 1214 <SYSC_IDLE_NO>, 1215 <SYSC_IDLE_SMART>, 1216 <SYSC_IDLE_SMART_WKUP>; 1217 ti,syss-mask = <1>; 1218 /* Domains (P, C): per_pwrdm, l4ls_clkdm */ 1219 clocks = <&l4ls_clkctrl AM3_L4LS_GPIO2_CLKCTRL 0>, 1220 <&l4ls_clkctrl AM3_L4LS_GPIO2_CLKCTRL 18>; 1221 clock-names = "fck", "dbclk"; 1222 #address-cells = <1>; 1223 #size-cells = <1>; 1224 ranges = <0x0 0x4c000 0x1000>; 1225 1226 gpio1: gpio@0 { 1227 compatible = "ti,omap4-gpio"; 1228 gpio-ranges = <&am33xx_pinmux 0 0 8>, 1229 <&am33xx_pinmux 8 90 4>, 1230 <&am33xx_pinmux 12 12 16>, 1231 <&am33xx_pinmux 28 30 4>; 1232 gpio-controller; 1233 #gpio-cells = <2>; 1234 interrupt-controller; 1235 #interrupt-cells = <2>; 1236 reg = <0x0 0x1000>; 1237 interrupts = <98>; 1238 }; 1239 }; 1240 1241 target-module@50000 { /* 0x48050000, ap 34 2c.0 */ 1242 compatible = "ti,sysc"; 1243 status = "disabled"; 1244 #address-cells = <1>; 1245 #size-cells = <1>; 1246 ranges = <0x0 0x50000 0x2000>; 1247 }; 1248 1249 target-module@60000 { /* 0x48060000, ap 36 0c.0 */ 1250 compatible = "ti,sysc-omap2", "ti,sysc"; 1251 reg = <0x602fc 0x4>, 1252 <0x60110 0x4>, 1253 <0x60114 0x4>; 1254 reg-names = "rev", "sysc", "syss"; 1255 ti,sysc-mask = <(SYSC_OMAP2_CLOCKACTIVITY | 1256 SYSC_OMAP2_ENAWAKEUP | 1257 SYSC_OMAP2_SOFTRESET | 1258 SYSC_OMAP2_AUTOIDLE)>; 1259 ti,sysc-sidle = <SYSC_IDLE_FORCE>, 1260 <SYSC_IDLE_NO>, 1261 <SYSC_IDLE_SMART>; 1262 ti,syss-mask = <1>; 1263 /* Domains (P, C): per_pwrdm, l4ls_clkdm */ 1264 clocks = <&l4ls_clkctrl AM3_L4LS_MMC1_CLKCTRL 0>; 1265 clock-names = "fck"; 1266 #address-cells = <1>; 1267 #size-cells = <1>; 1268 ranges = <0x0 0x60000 0x1000>; 1269 }; 1270 1271 target-module@80000 { /* 0x48080000, ap 38 18.0 */ 1272 compatible = "ti,sysc-omap2", "ti,sysc"; 1273 reg = <0x80000 0x4>, 1274 <0x80010 0x4>, 1275 <0x80014 0x4>; 1276 reg-names = "rev", "sysc", "syss"; 1277 ti,sysc-mask = <(SYSC_OMAP2_CLOCKACTIVITY | 1278 SYSC_OMAP2_SOFTRESET | 1279 SYSC_OMAP2_AUTOIDLE)>; 1280 ti,sysc-sidle = <SYSC_IDLE_FORCE>, 1281 <SYSC_IDLE_NO>, 1282 <SYSC_IDLE_SMART>; 1283 ti,syss-mask = <1>; 1284 /* Domains (P, C): per_pwrdm, l4ls_clkdm */ 1285 clocks = <&l4ls_clkctrl AM3_L4LS_ELM_CLKCTRL 0>; 1286 clock-names = "fck"; 1287 #address-cells = <1>; 1288 #size-cells = <1>; 1289 ranges = <0x0 0x80000 0x10000>; 1290 1291 elm: elm@0 { 1292 compatible = "ti,am3352-elm"; 1293 reg = <0x0 0x2000>; 1294 interrupts = <4>; 1295 status = "disabled"; 1296 }; 1297 }; 1298 1299 target-module@a0000 { /* 0x480a0000, ap 40 5e.0 */ 1300 compatible = "ti,sysc"; 1301 status = "disabled"; 1302 #address-cells = <1>; 1303 #size-cells = <1>; 1304 ranges = <0x0 0xa0000 0x10000>; 1305 }; 1306 1307 target-module@c8000 { /* 0x480c8000, ap 87 06.0 */ 1308 compatible = "ti,sysc-omap4", "ti,sysc"; 1309 reg = <0xc8000 0x4>, 1310 <0xc8010 0x4>; 1311 reg-names = "rev", "sysc"; 1312 ti,sysc-mask = <SYSC_OMAP4_SOFTRESET>; 1313 ti,sysc-sidle = <SYSC_IDLE_FORCE>, 1314 <SYSC_IDLE_NO>, 1315 <SYSC_IDLE_SMART>; 1316 /* Domains (P, C): per_pwrdm, l4ls_clkdm */ 1317 clocks = <&l4ls_clkctrl AM3_L4LS_MAILBOX_CLKCTRL 0>; 1318 clock-names = "fck"; 1319 #address-cells = <1>; 1320 #size-cells = <1>; 1321 ranges = <0x0 0xc8000 0x1000>; 1322 1323 mailbox: mailbox@0 { 1324 compatible = "ti,omap4-mailbox"; 1325 reg = <0x0 0x200>; 1326 interrupts = <77>; 1327 #mbox-cells = <1>; 1328 ti,mbox-num-users = <4>; 1329 ti,mbox-num-fifos = <8>; 1330 mbox_wkupm3: wkup_m3 { 1331 ti,mbox-send-noirq; 1332 ti,mbox-tx = <0 0 0>; 1333 ti,mbox-rx = <0 0 3>; 1334 }; 1335 }; 1336 }; 1337 1338 target-module@ca000 { /* 0x480ca000, ap 91 40.0 */ 1339 compatible = "ti,sysc-omap2", "ti,sysc"; 1340 reg = <0xca000 0x4>, 1341 <0xca010 0x4>, 1342 <0xca014 0x4>; 1343 reg-names = "rev", "sysc", "syss"; 1344 ti,sysc-mask = <(SYSC_OMAP2_CLOCKACTIVITY | 1345 SYSC_OMAP2_ENAWAKEUP | 1346 SYSC_OMAP2_SOFTRESET | 1347 SYSC_OMAP2_AUTOIDLE)>; 1348 ti,sysc-sidle = <SYSC_IDLE_FORCE>, 1349 <SYSC_IDLE_NO>, 1350 <SYSC_IDLE_SMART>; 1351 ti,syss-mask = <1>; 1352 /* Domains (P, C): per_pwrdm, l4ls_clkdm */ 1353 clocks = <&l4ls_clkctrl AM3_L4LS_SPINLOCK_CLKCTRL 0>; 1354 clock-names = "fck"; 1355 #address-cells = <1>; 1356 #size-cells = <1>; 1357 ranges = <0x0 0xca000 0x1000>; 1358 1359 hwspinlock: spinlock@0 { 1360 compatible = "ti,omap4-hwspinlock"; 1361 reg = <0x0 0x1000>; 1362 #hwlock-cells = <1>; 1363 }; 1364 }; 1365 1366 target-module@cc000 { /* 0x480cc000, ap 89 0e.0 */ 1367 compatible = "ti,sysc"; 1368 status = "disabled"; 1369 #address-cells = <1>; 1370 #size-cells = <1>; 1371 ranges = <0x0 0xcc000 0x1000>; 1372 }; 1373 }; 1374 1375 segment@100000 { /* 0x48100000 */ 1376 compatible = "simple-bus"; 1377 #address-cells = <1>; 1378 #size-cells = <1>; 1379 ranges = <0x0008c000 0x0018c000 0x001000>, /* ap 42 */ 1380 <0x0008d000 0x0018d000 0x001000>, /* ap 43 */ 1381 <0x0008e000 0x0018e000 0x001000>, /* ap 44 */ 1382 <0x0008f000 0x0018f000 0x001000>, /* ap 45 */ 1383 <0x0009c000 0x0019c000 0x001000>, /* ap 46 */ 1384 <0x0009d000 0x0019d000 0x001000>, /* ap 47 */ 1385 <0x000a6000 0x001a6000 0x001000>, /* ap 48 */ 1386 <0x000a7000 0x001a7000 0x001000>, /* ap 49 */ 1387 <0x000a8000 0x001a8000 0x001000>, /* ap 50 */ 1388 <0x000a9000 0x001a9000 0x001000>, /* ap 51 */ 1389 <0x000aa000 0x001aa000 0x001000>, /* ap 52 */ 1390 <0x000ab000 0x001ab000 0x001000>, /* ap 53 */ 1391 <0x000ac000 0x001ac000 0x001000>, /* ap 54 */ 1392 <0x000ad000 0x001ad000 0x001000>, /* ap 55 */ 1393 <0x000ae000 0x001ae000 0x001000>, /* ap 56 */ 1394 <0x000af000 0x001af000 0x001000>, /* ap 57 */ 1395 <0x000b0000 0x001b0000 0x010000>, /* ap 58 */ 1396 <0x000c0000 0x001c0000 0x001000>, /* ap 59 */ 1397 <0x000cc000 0x001cc000 0x002000>, /* ap 60 */ 1398 <0x000ce000 0x001ce000 0x002000>, /* ap 61 */ 1399 <0x000d0000 0x001d0000 0x002000>, /* ap 62 */ 1400 <0x000d2000 0x001d2000 0x002000>, /* ap 63 */ 1401 <0x000d8000 0x001d8000 0x001000>, /* ap 64 */ 1402 <0x000d9000 0x001d9000 0x001000>, /* ap 65 */ 1403 <0x000a0000 0x001a0000 0x001000>, /* ap 79 */ 1404 <0x000a1000 0x001a1000 0x001000>, /* ap 80 */ 1405 <0x000a2000 0x001a2000 0x001000>, /* ap 81 */ 1406 <0x000a3000 0x001a3000 0x001000>, /* ap 82 */ 1407 <0x000a4000 0x001a4000 0x001000>, /* ap 83 */ 1408 <0x000a5000 0x001a5000 0x001000>; /* ap 84 */ 1409 1410 target-module@8c000 { /* 0x4818c000, ap 42 04.0 */ 1411 compatible = "ti,sysc"; 1412 status = "disabled"; 1413 #address-cells = <1>; 1414 #size-cells = <1>; 1415 ranges = <0x0 0x8c000 0x1000>; 1416 }; 1417 1418 target-module@8e000 { /* 0x4818e000, ap 44 0a.0 */ 1419 compatible = "ti,sysc"; 1420 status = "disabled"; 1421 #address-cells = <1>; 1422 #size-cells = <1>; 1423 ranges = <0x0 0x8e000 0x1000>; 1424 }; 1425 1426 target-module@9c000 { /* 0x4819c000, ap 46 5a.0 */ 1427 compatible = "ti,sysc-omap2", "ti,sysc"; 1428 reg = <0x9c000 0x8>, 1429 <0x9c010 0x8>, 1430 <0x9c090 0x8>; 1431 reg-names = "rev", "sysc", "syss"; 1432 ti,sysc-mask = <(SYSC_OMAP2_CLOCKACTIVITY | 1433 SYSC_OMAP2_ENAWAKEUP | 1434 SYSC_OMAP2_SOFTRESET | 1435 SYSC_OMAP2_AUTOIDLE)>; 1436 ti,sysc-sidle = <SYSC_IDLE_FORCE>, 1437 <SYSC_IDLE_NO>, 1438 <SYSC_IDLE_SMART>, 1439 <SYSC_IDLE_SMART_WKUP>; 1440 ti,syss-mask = <1>; 1441 /* Domains (P, C): per_pwrdm, l4ls_clkdm */ 1442 clocks = <&l4ls_clkctrl AM3_L4LS_I2C3_CLKCTRL 0>; 1443 clock-names = "fck"; 1444 #address-cells = <1>; 1445 #size-cells = <1>; 1446 ranges = <0x0 0x9c000 0x1000>; 1447 }; 1448 1449 target-module@a0000 { /* 0x481a0000, ap 79 24.0 */ 1450 compatible = "ti,sysc-omap2", "ti,sysc"; 1451 reg = <0xa0000 0x4>, 1452 <0xa0110 0x4>, 1453 <0xa0114 0x4>; 1454 reg-names = "rev", "sysc", "syss"; 1455 ti,sysc-mask = <(SYSC_OMAP2_CLOCKACTIVITY | 1456 SYSC_OMAP2_SOFTRESET | 1457 SYSC_OMAP2_AUTOIDLE)>; 1458 ti,sysc-sidle = <SYSC_IDLE_FORCE>, 1459 <SYSC_IDLE_NO>, 1460 <SYSC_IDLE_SMART>; 1461 ti,syss-mask = <1>; 1462 /* Domains (P, C): per_pwrdm, l4ls_clkdm */ 1463 clocks = <&l4ls_clkctrl AM3_L4LS_SPI1_CLKCTRL 0>; 1464 clock-names = "fck"; 1465 #address-cells = <1>; 1466 #size-cells = <1>; 1467 ranges = <0x0 0xa0000 0x1000>; 1468 1469 spi1: spi@0 { 1470 compatible = "ti,omap4-mcspi"; 1471 #address-cells = <1>; 1472 #size-cells = <0>; 1473 reg = <0x0 0x400>; 1474 interrupts = <125>; 1475 ti,spi-num-cs = <2>; 1476 dmas = <&edma 42 0 1477 &edma 43 0 1478 &edma 44 0 1479 &edma 45 0>; 1480 dma-names = "tx0", "rx0", "tx1", "rx1"; 1481 status = "disabled"; 1482 }; 1483 }; 1484 1485 target-module@a2000 { /* 0x481a2000, ap 81 2e.0 */ 1486 compatible = "ti,sysc"; 1487 status = "disabled"; 1488 #address-cells = <1>; 1489 #size-cells = <1>; 1490 ranges = <0x0 0xa2000 0x1000>; 1491 }; 1492 1493 target-module@a4000 { /* 0x481a4000, ap 83 30.0 */ 1494 compatible = "ti,sysc"; 1495 status = "disabled"; 1496 #address-cells = <1>; 1497 #size-cells = <1>; 1498 ranges = <0x0 0xa4000 0x1000>; 1499 }; 1500 1501 target-module@a6000 { /* 0x481a6000, ap 48 16.0 */ 1502 compatible = "ti,sysc-omap2", "ti,sysc"; 1503 reg = <0xa6050 0x4>, 1504 <0xa6054 0x4>, 1505 <0xa6058 0x4>; 1506 reg-names = "rev", "sysc", "syss"; 1507 ti,sysc-mask = <(SYSC_OMAP2_ENAWAKEUP | 1508 SYSC_OMAP2_SOFTRESET | 1509 SYSC_OMAP2_AUTOIDLE)>; 1510 ti,sysc-sidle = <SYSC_IDLE_FORCE>, 1511 <SYSC_IDLE_NO>, 1512 <SYSC_IDLE_SMART>, 1513 <SYSC_IDLE_SMART_WKUP>; 1514 /* Domains (P, C): per_pwrdm, l4ls_clkdm */ 1515 clocks = <&l4ls_clkctrl AM3_L4LS_UART4_CLKCTRL 0>; 1516 clock-names = "fck"; 1517 #address-cells = <1>; 1518 #size-cells = <1>; 1519 ranges = <0x0 0xa6000 0x1000>; 1520 1521 uart3: serial@0 { 1522 compatible = "ti,am3352-uart", "ti,omap3-uart"; 1523 clock-frequency = <48000000>; 1524 reg = <0x0 0x1000>; 1525 interrupts = <44>; 1526 status = "disabled"; 1527 }; 1528 }; 1529 1530 target-module@a8000 { /* 0x481a8000, ap 50 20.0 */ 1531 compatible = "ti,sysc-omap2", "ti,sysc"; 1532 reg = <0xa8050 0x4>, 1533 <0xa8054 0x4>, 1534 <0xa8058 0x4>; 1535 reg-names = "rev", "sysc", "syss"; 1536 ti,sysc-mask = <(SYSC_OMAP2_ENAWAKEUP | 1537 SYSC_OMAP2_SOFTRESET | 1538 SYSC_OMAP2_AUTOIDLE)>; 1539 ti,sysc-sidle = <SYSC_IDLE_FORCE>, 1540 <SYSC_IDLE_NO>, 1541 <SYSC_IDLE_SMART>, 1542 <SYSC_IDLE_SMART_WKUP>; 1543 /* Domains (P, C): per_pwrdm, l4ls_clkdm */ 1544 clocks = <&l4ls_clkctrl AM3_L4LS_UART5_CLKCTRL 0>; 1545 clock-names = "fck"; 1546 #address-cells = <1>; 1547 #size-cells = <1>; 1548 ranges = <0x0 0xa8000 0x1000>; 1549 1550 uart4: serial@0 { 1551 compatible = "ti,am3352-uart", "ti,omap3-uart"; 1552 clock-frequency = <48000000>; 1553 reg = <0x0 0x1000>; 1554 interrupts = <45>; 1555 status = "disabled"; 1556 }; 1557 }; 1558 1559 target-module@aa000 { /* 0x481aa000, ap 52 1a.0 */ 1560 compatible = "ti,sysc-omap2", "ti,sysc"; 1561 reg = <0xaa050 0x4>, 1562 <0xaa054 0x4>, 1563 <0xaa058 0x4>; 1564 reg-names = "rev", "sysc", "syss"; 1565 ti,sysc-mask = <(SYSC_OMAP2_ENAWAKEUP | 1566 SYSC_OMAP2_SOFTRESET | 1567 SYSC_OMAP2_AUTOIDLE)>; 1568 ti,sysc-sidle = <SYSC_IDLE_FORCE>, 1569 <SYSC_IDLE_NO>, 1570 <SYSC_IDLE_SMART>, 1571 <SYSC_IDLE_SMART_WKUP>; 1572 /* Domains (P, C): per_pwrdm, l4ls_clkdm */ 1573 clocks = <&l4ls_clkctrl AM3_L4LS_UART6_CLKCTRL 0>; 1574 clock-names = "fck"; 1575 #address-cells = <1>; 1576 #size-cells = <1>; 1577 ranges = <0x0 0xaa000 0x1000>; 1578 1579 uart5: serial@0 { 1580 compatible = "ti,am3352-uart", "ti,omap3-uart"; 1581 clock-frequency = <48000000>; 1582 reg = <0x0 0x1000>; 1583 interrupts = <46>; 1584 status = "disabled"; 1585 }; 1586 }; 1587 1588 target-module@ac000 { /* 0x481ac000, ap 54 38.0 */ 1589 compatible = "ti,sysc-omap2", "ti,sysc"; 1590 reg = <0xac000 0x4>, 1591 <0xac010 0x4>, 1592 <0xac114 0x4>; 1593 reg-names = "rev", "sysc", "syss"; 1594 ti,sysc-mask = <(SYSC_OMAP2_ENAWAKEUP | 1595 SYSC_OMAP2_SOFTRESET | 1596 SYSC_OMAP2_AUTOIDLE)>; 1597 ti,sysc-sidle = <SYSC_IDLE_FORCE>, 1598 <SYSC_IDLE_NO>, 1599 <SYSC_IDLE_SMART>, 1600 <SYSC_IDLE_SMART_WKUP>; 1601 ti,syss-mask = <1>; 1602 /* Domains (P, C): per_pwrdm, l4ls_clkdm */ 1603 clocks = <&l4ls_clkctrl AM3_L4LS_GPIO3_CLKCTRL 0>, 1604 <&l4ls_clkctrl AM3_L4LS_GPIO3_CLKCTRL 18>; 1605 clock-names = "fck", "dbclk"; 1606 #address-cells = <1>; 1607 #size-cells = <1>; 1608 ranges = <0x0 0xac000 0x1000>; 1609 1610 gpio2: gpio@0 { 1611 compatible = "ti,omap4-gpio"; 1612 gpio-ranges = <&am33xx_pinmux 0 34 18>, 1613 <&am33xx_pinmux 18 77 4>, 1614 <&am33xx_pinmux 22 56 10>; 1615 gpio-controller; 1616 #gpio-cells = <2>; 1617 interrupt-controller; 1618 #interrupt-cells = <2>; 1619 reg = <0x0 0x1000>; 1620 interrupts = <32>; 1621 }; 1622 }; 1623 1624 target-module@ae000 { /* 0x481ae000, ap 56 3a.0 */ 1625 compatible = "ti,sysc-omap2", "ti,sysc"; 1626 reg = <0xae000 0x4>, 1627 <0xae010 0x4>, 1628 <0xae114 0x4>; 1629 reg-names = "rev", "sysc", "syss"; 1630 ti,sysc-mask = <(SYSC_OMAP2_ENAWAKEUP | 1631 SYSC_OMAP2_SOFTRESET | 1632 SYSC_OMAP2_AUTOIDLE)>; 1633 ti,sysc-sidle = <SYSC_IDLE_FORCE>, 1634 <SYSC_IDLE_NO>, 1635 <SYSC_IDLE_SMART>, 1636 <SYSC_IDLE_SMART_WKUP>; 1637 ti,syss-mask = <1>; 1638 /* Domains (P, C): per_pwrdm, l4ls_clkdm */ 1639 clocks = <&l4ls_clkctrl AM3_L4LS_GPIO4_CLKCTRL 0>, 1640 <&l4ls_clkctrl AM3_L4LS_GPIO4_CLKCTRL 18>; 1641 clock-names = "fck", "dbclk"; 1642 #address-cells = <1>; 1643 #size-cells = <1>; 1644 ranges = <0x0 0xae000 0x1000>; 1645 1646 gpio3: gpio@0 { 1647 compatible = "ti,omap4-gpio"; 1648 gpio-ranges = <&am33xx_pinmux 0 66 5>, 1649 <&am33xx_pinmux 5 98 2>, 1650 <&am33xx_pinmux 7 75 2>, 1651 <&am33xx_pinmux 13 141 1>, 1652 <&am33xx_pinmux 14 100 8>; 1653 gpio-controller; 1654 #gpio-cells = <2>; 1655 interrupt-controller; 1656 #interrupt-cells = <2>; 1657 reg = <0x0 0x1000>; 1658 interrupts = <62>; 1659 }; 1660 }; 1661 1662 target-module@b0000 { /* 0x481b0000, ap 58 50.0 */ 1663 compatible = "ti,sysc"; 1664 status = "disabled"; 1665 #address-cells = <1>; 1666 #size-cells = <1>; 1667 ranges = <0x0 0xb0000 0x10000>; 1668 }; 1669 1670 target-module@cc000 { /* 0x481cc000, ap 60 46.0 */ 1671 compatible = "ti,sysc-omap4", "ti,sysc"; 1672 reg = <0xcc020 0x4>; 1673 reg-names = "rev"; 1674 /* Domains (P, C): per_pwrdm, l4ls_clkdm */ 1675 clocks = <&l4ls_clkctrl AM3_L4LS_D_CAN0_CLKCTRL 0>, 1676 <&dcan0_fck>; 1677 clock-names = "fck", "osc"; 1678 #address-cells = <1>; 1679 #size-cells = <1>; 1680 ranges = <0x0 0xcc000 0x2000>; 1681 1682 dcan0: can@0 { 1683 compatible = "ti,am3352-d_can"; 1684 reg = <0x0 0x2000>; 1685 clocks = <&dcan0_fck>; 1686 clock-names = "fck"; 1687 syscon-raminit = <&scm_conf 0x644 0>; 1688 interrupts = <52>; 1689 status = "disabled"; 1690 }; 1691 }; 1692 1693 target-module@d0000 { /* 0x481d0000, ap 62 42.0 */ 1694 compatible = "ti,sysc-omap4", "ti,sysc"; 1695 reg = <0xd0020 0x4>; 1696 reg-names = "rev"; 1697 /* Domains (P, C): per_pwrdm, l4ls_clkdm */ 1698 clocks = <&l4ls_clkctrl AM3_L4LS_D_CAN1_CLKCTRL 0>, 1699 <&dcan1_fck>; 1700 clock-names = "fck", "osc"; 1701 #address-cells = <1>; 1702 #size-cells = <1>; 1703 ranges = <0x0 0xd0000 0x2000>; 1704 1705 dcan1: can@0 { 1706 compatible = "ti,am3352-d_can"; 1707 reg = <0x0 0x2000>; 1708 clocks = <&dcan1_fck>; 1709 clock-names = "fck"; 1710 syscon-raminit = <&scm_conf 0x644 1>; 1711 interrupts = <55>; 1712 status = "disabled"; 1713 }; 1714 }; 1715 1716 target-module@d8000 { /* 0x481d8000, ap 64 66.0 */ 1717 compatible = "ti,sysc-omap2", "ti,sysc"; 1718 reg = <0xd82fc 0x4>, 1719 <0xd8110 0x4>, 1720 <0xd8114 0x4>; 1721 reg-names = "rev", "sysc", "syss"; 1722 ti,sysc-mask = <(SYSC_OMAP2_CLOCKACTIVITY | 1723 SYSC_OMAP2_ENAWAKEUP | 1724 SYSC_OMAP2_SOFTRESET | 1725 SYSC_OMAP2_AUTOIDLE)>; 1726 ti,sysc-sidle = <SYSC_IDLE_FORCE>, 1727 <SYSC_IDLE_NO>, 1728 <SYSC_IDLE_SMART>; 1729 ti,syss-mask = <1>; 1730 /* Domains (P, C): per_pwrdm, l4ls_clkdm */ 1731 clocks = <&l4ls_clkctrl AM3_L4LS_MMC2_CLKCTRL 0>; 1732 clock-names = "fck"; 1733 #address-cells = <1>; 1734 #size-cells = <1>; 1735 ranges = <0x0 0xd8000 0x1000>; 1736 }; 1737 }; 1738 1739 segment@200000 { /* 0x48200000 */ 1740 compatible = "simple-bus"; 1741 #address-cells = <1>; 1742 #size-cells = <1>; 1743 }; 1744 1745 segment@300000 { /* 0x48300000 */ 1746 compatible = "simple-bus"; 1747 #address-cells = <1>; 1748 #size-cells = <1>; 1749 ranges = <0x00000000 0x00300000 0x001000>, /* ap 66 */ 1750 <0x00001000 0x00301000 0x001000>, /* ap 67 */ 1751 <0x00002000 0x00302000 0x001000>, /* ap 68 */ 1752 <0x00003000 0x00303000 0x001000>, /* ap 69 */ 1753 <0x00004000 0x00304000 0x001000>, /* ap 70 */ 1754 <0x00005000 0x00305000 0x001000>, /* ap 71 */ 1755 <0x0000e000 0x0030e000 0x001000>, /* ap 72 */ 1756 <0x0000f000 0x0030f000 0x001000>, /* ap 73 */ 1757 <0x00018000 0x00318000 0x004000>, /* ap 74 */ 1758 <0x0001c000 0x0031c000 0x001000>, /* ap 75 */ 1759 <0x00010000 0x00310000 0x002000>, /* ap 76 */ 1760 <0x00012000 0x00312000 0x001000>, /* ap 93 */ 1761 <0x00015000 0x00315000 0x001000>, /* ap 94 */ 1762 <0x00016000 0x00316000 0x001000>, /* ap 95 */ 1763 <0x00017000 0x00317000 0x001000>, /* ap 96 */ 1764 <0x00013000 0x00313000 0x001000>, /* ap 97 */ 1765 <0x00014000 0x00314000 0x001000>, /* ap 98 */ 1766 <0x00020000 0x00320000 0x001000>, /* ap 99 */ 1767 <0x00021000 0x00321000 0x001000>, /* ap 100 */ 1768 <0x00022000 0x00322000 0x001000>, /* ap 101 */ 1769 <0x00023000 0x00323000 0x001000>, /* ap 102 */ 1770 <0x00024000 0x00324000 0x001000>, /* ap 103 */ 1771 <0x00025000 0x00325000 0x001000>; /* ap 104 */ 1772 1773 target-module@0 { /* 0x48300000, ap 66 48.0 */ 1774 compatible = "ti,sysc-omap4", "ti,sysc"; 1775 reg = <0x0 0x4>, 1776 <0x4 0x4>; 1777 reg-names = "rev", "sysc"; 1778 ti,sysc-midle = <SYSC_IDLE_FORCE>, 1779 <SYSC_IDLE_NO>, 1780 <SYSC_IDLE_SMART>, 1781 <SYSC_IDLE_SMART_WKUP>; 1782 ti,sysc-sidle = <SYSC_IDLE_FORCE>, 1783 <SYSC_IDLE_NO>, 1784 <SYSC_IDLE_SMART>, 1785 <SYSC_IDLE_SMART_WKUP>; 1786 /* Domains (P, C): per_pwrdm, l4ls_clkdm */ 1787 clocks = <&l4ls_clkctrl AM3_L4LS_EPWMSS0_CLKCTRL 0>; 1788 clock-names = "fck"; 1789 #address-cells = <1>; 1790 #size-cells = <1>; 1791 ranges = <0x0 0x0 0x1000>; 1792 1793 epwmss0: epwmss@0 { 1794 compatible = "ti,am33xx-pwmss"; 1795 reg = <0x0 0x10>; 1796 #address-cells = <1>; 1797 #size-cells = <1>; 1798 status = "disabled"; 1799 ranges = <0 0 0x1000>; 1800 1801 ecap0: ecap@100 { 1802 compatible = "ti,am3352-ecap", 1803 "ti,am33xx-ecap"; 1804 #pwm-cells = <3>; 1805 reg = <0x100 0x80>; 1806 clocks = <&l4ls_gclk>; 1807 clock-names = "fck"; 1808 interrupts = <31>; 1809 interrupt-names = "ecap0"; 1810 status = "disabled"; 1811 }; 1812 1813 ehrpwm0: pwm@200 { 1814 compatible = "ti,am3352-ehrpwm", 1815 "ti,am33xx-ehrpwm"; 1816 #pwm-cells = <3>; 1817 reg = <0x200 0x80>; 1818 clocks = <&ehrpwm0_tbclk>, <&l4ls_gclk>; 1819 clock-names = "tbclk", "fck"; 1820 status = "disabled"; 1821 }; 1822 }; 1823 }; 1824 1825 target-module@2000 { /* 0x48302000, ap 68 52.0 */ 1826 compatible = "ti,sysc-omap4", "ti,sysc"; 1827 reg = <0x2000 0x4>, 1828 <0x2004 0x4>; 1829 reg-names = "rev", "sysc"; 1830 ti,sysc-midle = <SYSC_IDLE_FORCE>, 1831 <SYSC_IDLE_NO>, 1832 <SYSC_IDLE_SMART>, 1833 <SYSC_IDLE_SMART_WKUP>; 1834 ti,sysc-sidle = <SYSC_IDLE_FORCE>, 1835 <SYSC_IDLE_NO>, 1836 <SYSC_IDLE_SMART>, 1837 <SYSC_IDLE_SMART_WKUP>; 1838 /* Domains (P, C): per_pwrdm, l4ls_clkdm */ 1839 clocks = <&l4ls_clkctrl AM3_L4LS_EPWMSS1_CLKCTRL 0>; 1840 clock-names = "fck"; 1841 #address-cells = <1>; 1842 #size-cells = <1>; 1843 ranges = <0x0 0x2000 0x1000>; 1844 1845 epwmss1: epwmss@0 { 1846 compatible = "ti,am33xx-pwmss"; 1847 reg = <0x0 0x10>; 1848 #address-cells = <1>; 1849 #size-cells = <1>; 1850 status = "disabled"; 1851 ranges = <0 0 0x1000>; 1852 1853 ecap1: ecap@100 { 1854 compatible = "ti,am3352-ecap", 1855 "ti,am33xx-ecap"; 1856 #pwm-cells = <3>; 1857 reg = <0x100 0x80>; 1858 clocks = <&l4ls_gclk>; 1859 clock-names = "fck"; 1860 interrupts = <47>; 1861 interrupt-names = "ecap1"; 1862 status = "disabled"; 1863 }; 1864 1865 ehrpwm1: pwm@200 { 1866 compatible = "ti,am3352-ehrpwm", 1867 "ti,am33xx-ehrpwm"; 1868 #pwm-cells = <3>; 1869 reg = <0x200 0x80>; 1870 clocks = <&ehrpwm1_tbclk>, <&l4ls_gclk>; 1871 clock-names = "tbclk", "fck"; 1872 status = "disabled"; 1873 }; 1874 }; 1875 }; 1876 1877 target-module@4000 { /* 0x48304000, ap 70 44.0 */ 1878 compatible = "ti,sysc-omap4", "ti,sysc"; 1879 reg = <0x4000 0x4>, 1880 <0x4004 0x4>; 1881 reg-names = "rev", "sysc"; 1882 ti,sysc-midle = <SYSC_IDLE_FORCE>, 1883 <SYSC_IDLE_NO>, 1884 <SYSC_IDLE_SMART>, 1885 <SYSC_IDLE_SMART_WKUP>; 1886 ti,sysc-sidle = <SYSC_IDLE_FORCE>, 1887 <SYSC_IDLE_NO>, 1888 <SYSC_IDLE_SMART>, 1889 <SYSC_IDLE_SMART_WKUP>; 1890 /* Domains (P, C): per_pwrdm, l4ls_clkdm */ 1891 clocks = <&l4ls_clkctrl AM3_L4LS_EPWMSS2_CLKCTRL 0>; 1892 clock-names = "fck"; 1893 #address-cells = <1>; 1894 #size-cells = <1>; 1895 ranges = <0x0 0x4000 0x1000>; 1896 1897 epwmss2: epwmss@0 { 1898 compatible = "ti,am33xx-pwmss"; 1899 reg = <0x0 0x10>; 1900 #address-cells = <1>; 1901 #size-cells = <1>; 1902 status = "disabled"; 1903 ranges = <0 0 0x1000>; 1904 1905 ecap2: ecap@100 { 1906 compatible = "ti,am3352-ecap", 1907 "ti,am33xx-ecap"; 1908 #pwm-cells = <3>; 1909 reg = <0x100 0x80>; 1910 clocks = <&l4ls_gclk>; 1911 clock-names = "fck"; 1912 interrupts = <61>; 1913 interrupt-names = "ecap2"; 1914 status = "disabled"; 1915 }; 1916 1917 ehrpwm2: pwm@200 { 1918 compatible = "ti,am3352-ehrpwm", 1919 "ti,am33xx-ehrpwm"; 1920 #pwm-cells = <3>; 1921 reg = <0x200 0x80>; 1922 clocks = <&ehrpwm2_tbclk>, <&l4ls_gclk>; 1923 clock-names = "tbclk", "fck"; 1924 status = "disabled"; 1925 }; 1926 }; 1927 }; 1928 1929 target-module@e000 { /* 0x4830e000, ap 72 4a.0 */ 1930 compatible = "ti,sysc-omap4", "ti,sysc"; 1931 reg = <0xe000 0x4>, 1932 <0xe054 0x4>; 1933 reg-names = "rev", "sysc"; 1934 ti,sysc-midle = <SYSC_IDLE_FORCE>, 1935 <SYSC_IDLE_NO>, 1936 <SYSC_IDLE_SMART>; 1937 ti,sysc-sidle = <SYSC_IDLE_FORCE>, 1938 <SYSC_IDLE_NO>, 1939 <SYSC_IDLE_SMART>; 1940 /* Domains (P, C): per_pwrdm, lcdc_clkdm */ 1941 clocks = <&lcdc_clkctrl AM3_LCDC_LCDC_CLKCTRL 0>; 1942 clock-names = "fck"; 1943 #address-cells = <1>; 1944 #size-cells = <1>; 1945 ranges = <0x0 0xe000 0x1000>; 1946 1947 lcdc: lcdc@0 { 1948 compatible = "ti,am33xx-tilcdc"; 1949 reg = <0x0 0x1000>; 1950 interrupts = <36>; 1951 status = "disabled"; 1952 }; 1953 }; 1954 1955 target-module@10000 { /* 0x48310000, ap 76 4e.1 */ 1956 compatible = "ti,sysc-omap2", "ti,sysc"; 1957 reg = <0x11fe0 0x4>, 1958 <0x11fe4 0x4>; 1959 reg-names = "rev", "sysc"; 1960 ti,sysc-mask = <SYSC_OMAP2_AUTOIDLE>; 1961 ti,sysc-sidle = <SYSC_IDLE_FORCE>, 1962 <SYSC_IDLE_NO>; 1963 /* Domains (P, C): per_pwrdm, l4ls_clkdm */ 1964 clocks = <&l4ls_clkctrl AM3_L4LS_RNG_CLKCTRL 0>; 1965 clock-names = "fck"; 1966 #address-cells = <1>; 1967 #size-cells = <1>; 1968 ranges = <0x0 0x10000 0x2000>; 1969 1970 rng: rng@0 { 1971 compatible = "ti,omap4-rng"; 1972 reg = <0x0 0x2000>; 1973 interrupts = <111>; 1974 }; 1975 }; 1976 1977 target-module@13000 { /* 0x48313000, ap 97 62.0 */ 1978 compatible = "ti,sysc"; 1979 status = "disabled"; 1980 #address-cells = <1>; 1981 #size-cells = <1>; 1982 ranges = <0x0 0x13000 0x1000>; 1983 }; 1984 1985 target-module@15000 { /* 0x48315000, ap 94 56.0 */ 1986 compatible = "ti,sysc"; 1987 status = "disabled"; 1988 #address-cells = <1>; 1989 #size-cells = <1>; 1990 ranges = <0x00000000 0x00015000 0x00001000>, 1991 <0x00001000 0x00016000 0x00001000>; 1992 }; 1993 1994 target-module@18000 { /* 0x48318000, ap 74 4c.0 */ 1995 compatible = "ti,sysc"; 1996 status = "disabled"; 1997 #address-cells = <1>; 1998 #size-cells = <1>; 1999 ranges = <0x0 0x18000 0x4000>; 2000 }; 2001 2002 target-module@20000 { /* 0x48320000, ap 99 34.0 */ 2003 compatible = "ti,sysc"; 2004 status = "disabled"; 2005 #address-cells = <1>; 2006 #size-cells = <1>; 2007 ranges = <0x0 0x20000 0x1000>; 2008 }; 2009 2010 target-module@22000 { /* 0x48322000, ap 101 3e.0 */ 2011 compatible = "ti,sysc"; 2012 status = "disabled"; 2013 #address-cells = <1>; 2014 #size-cells = <1>; 2015 ranges = <0x0 0x22000 0x1000>; 2016 }; 2017 2018 target-module@24000 { /* 0x48324000, ap 103 68.0 */ 2019 compatible = "ti,sysc"; 2020 status = "disabled"; 2021 #address-cells = <1>; 2022 #size-cells = <1>; 2023 ranges = <0x0 0x24000 0x1000>; 2024 }; 2025 }; 2026}; 2027