1// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
2/*
3 * Device Tree file for CRS305-1G-4S board
4 *
5 * Copyright (C) 2016 Allied Telesis Labs
6 * Copyright (C) 2020 Sartura Ltd.
7 *
8 * Based on armada-xp-db.dts
9 *
10 * Note: this Device Tree assumes that the bootloader has remapped the
11 * internal registers to 0xf1000000 (instead of the default
12 * 0xd0000000). The 0xf1000000 is the default used by the recent,
13 * DT-capable, U-Boot bootloaders provided by Marvell. Some earlier
14 * boards were delivered with an older version of the bootloader that
15 * left internal registers mapped at 0xd0000000. If you are in this
16 * situation, you should either update your bootloader (preferred
17 * solution) or the below Device Tree should be adjusted.
18 */
19
20/dts-v1/;
21#include "armada-xp-98dx3236.dtsi"
22#include "armada-xp-crs305-1g-4s-u-boot.dtsi"
23
24/ {
25	model = "CRS305-1G-4S+";
26	compatible = "marvell,armadaxp-98dx3236", "marvell,armadaxp-mv78260", "marvell,armadaxp", "marvell,armada-370-xp";
27
28	chosen {
29		stdout-path = "serial0:115200n8";
30		bootargs = "console=ttyS0,115200 earlyprintk";
31	};
32
33	aliases {
34		spi0 = &spi0;
35	};
36
37	memory {
38		device_type = "memory";
39		reg = <0 0x00000000 0 0x20000000>; /* 512 MB */
40	};
41};
42
43&L2 {
44	arm,parity-enable;
45	marvell,ecc-enable;
46};
47
48&devbus_bootcs {
49	status = "okay";
50
51	/* Device Bus parameters are required */
52
53	/* Read parameters */
54	devbus,bus-width    = <16>;
55	devbus,turn-off-ps  = <60000>;
56	devbus,badr-skew-ps = <0>;
57	devbus,acc-first-ps = <124000>;
58	devbus,acc-next-ps  = <248000>;
59	devbus,rd-setup-ps  = <0>;
60	devbus,rd-hold-ps   = <0>;
61
62	/* Write parameters */
63	devbus,sync-enable = <0>;
64	devbus,wr-high-ps  = <60000>;
65	devbus,wr-low-ps   = <60000>;
66	devbus,ale-wr-ps   = <60000>;
67};
68
69&uart0 {
70	status = "okay";
71};
72
73&uart1 {
74	status = "okay";
75};
76
77&i2c0 {
78	clock-frequency = <100000>;
79	status = "okay";
80};
81
82&usb0 {
83	status = "okay";
84};
85
86&spi0 {
87	status = "okay";
88
89	spi-flash@0 {
90		#address-cells = <1>;
91		#size-cells = <1>;
92		compatible = "spi-flash", "jedec,spi-nor";
93		reg = <0>; /* Chip select 0 */
94		spi-max-frequency = <108000000>;
95		m25p,fast-read;
96
97		partition@u-boot {
98			reg = <0x00000000 0x001f0000>;
99			label = "u-boot";
100		};
101		partition@u-boot-env {
102			reg = <0x001f0000 0x00010000>;
103			label = "u-boot-env";
104		};
105		partition@ubi1 {
106			reg = <0x00200000 0x00e00000>;
107			label = "ubi1";
108		};
109
110	};
111};
112