1// SPDX-License-Identifier: GPL-2.0+
2/*
3 * Copyright 2019 NXP
4 */
5
6/ {
7	wdt-reboot {
8		compatible = "wdt-reboot";
9		wdt = <&wdog1>;
10		u-boot,dm-spl;
11	};
12};
13
14&{/soc@0} {
15	u-boot,dm-pre-reloc;
16	u-boot,dm-spl;
17};
18
19&clk {
20	u-boot,dm-spl;
21	u-boot,dm-pre-reloc;
22};
23
24&osc_32k {
25	u-boot,dm-spl;
26	u-boot,dm-pre-reloc;
27};
28
29&osc_24m {
30	u-boot,dm-spl;
31	u-boot,dm-pre-reloc;
32};
33
34&aips1 {
35	u-boot,dm-spl;
36	u-boot,dm-pre-reloc;
37};
38
39&aips2 {
40	u-boot,dm-spl;
41};
42
43&aips3 {
44	u-boot,dm-spl;
45};
46
47&iomuxc {
48	u-boot,dm-spl;
49};
50
51&reg_usdhc2_vmmc {
52	u-boot,off-on-delay-us = <20000>;
53};
54
55&reg_usdhc2_vmmc {
56	u-boot,dm-spl;
57};
58
59&pinctrl_uart2 {
60	u-boot,dm-spl;
61};
62
63&pinctrl_usdhc2_gpio {
64	u-boot,dm-spl;
65};
66
67&pinctrl_usdhc2 {
68	u-boot,dm-spl;
69};
70
71&pinctrl_usdhc3 {
72	u-boot,dm-spl;
73};
74
75&gpio1 {
76	u-boot,dm-spl;
77};
78
79&gpio2 {
80	u-boot,dm-spl;
81};
82
83&gpio3 {
84	u-boot,dm-spl;
85};
86
87&gpio4 {
88	u-boot,dm-spl;
89};
90
91&gpio5 {
92	u-boot,dm-spl;
93};
94
95&uart2 {
96	u-boot,dm-spl;
97};
98
99&i2c1 {
100	u-boot,dm-spl;
101};
102
103&i2c2 {
104	u-boot,dm-spl;
105};
106
107&i2c3 {
108	u-boot,dm-spl;
109};
110
111&i2c4 {
112	u-boot,dm-spl;
113};
114
115&i2c5 {
116	u-boot,dm-spl;
117};
118
119&i2c6 {
120	u-boot,dm-spl;
121};
122
123&usdhc1 {
124	u-boot,dm-spl;
125};
126
127&usdhc2 {
128	u-boot,dm-spl;
129	sd-uhs-sdr104;
130	sd-uhs-ddr50;
131};
132
133&usdhc3 {
134	u-boot,dm-spl;
135	mmc-hs400-1_8v;
136	mmc-hs400-enhanced-strobe;
137};
138
139&wdog1 {
140	u-boot,dm-spl;
141};
142
143&fec {
144	phy-reset-gpios = <&gpio4 2 GPIO_ACTIVE_LOW>;
145	phy-reset-duration = <15>;
146	phy-reset-post-delay = <100>;
147};
148