1// SPDX-License-Identifier: GPL-2.0+
2/*
3 * Copyright 2017 NXP
4 *
5 * Copyright 2019 Siemens AG
6 *
7 */
8
9/dts-v1/;
10
11#include "fsl-imx8qxp.dtsi"
12#include "imx8qxp-capricorn-u-boot.dtsi"
13
14/ {
15	model = "Siemens Giedi";
16	compatible = "siemens,capricorn", "fsl,imx8qxp";
17
18	chosen {
19		bootargs = "console=ttyLP2,115200 earlycon=lpuart32,0x5a080000,115200";
20		stdout-path = &lpuart2;
21	};
22
23	leds {
24		compatible = "gpio-leds";
25		pinctrl-names = "default";
26		pinctrl-0 = <&pinctrl_gpio_leds>;
27
28		run {
29			label = "run";
30			gpios = <&gpio5 0 GPIO_ACTIVE_HIGH>;
31			default-state = "on";
32		};
33
34		flt {
35			label = "flt";
36			gpios = <&gpio3 18 GPIO_ACTIVE_HIGH>;
37			default-state = "on";
38		};
39
40		svc {
41			label = "svc";
42			gpios = <&gpio5 1 GPIO_ACTIVE_HIGH>;
43			default-state = "on";
44		};
45
46		com1_tx {
47			label = "com1-tx";
48			gpios = <&gpio1 17 GPIO_ACTIVE_HIGH>;
49			default-state = "on";
50		};
51
52		com1_rx {
53			label = "com1-rx";
54			gpios = <&gpio1 18 GPIO_ACTIVE_HIGH>;
55			default-state = "on";
56		};
57
58		com2_tx {
59			label = "com2-tx";
60			gpios = <&gpio0 26 GPIO_ACTIVE_HIGH>;
61			default-state = "on";
62		};
63
64		com2_rx {
65			label = "com2-rx";
66			gpios = <&gpio0 29 GPIO_ACTIVE_HIGH>;
67			default-state = "on";
68		};
69
70		cloud {
71			label = "cloud";
72			gpios = <&gpio3 19 GPIO_ACTIVE_HIGH>;
73			default-state = "on";
74		};
75
76		wlan {
77			label = "wlan";
78			gpios = <&gpio0 4 GPIO_ACTIVE_HIGH>;
79			default-state = "on";
80		};
81
82		dbg1 {
83			label = "dbg1";
84			gpios = <&gpio0 1 GPIO_ACTIVE_HIGH>;
85			default-state = "on";
86		};
87
88		dbg2 {
89			label = "dbg2";
90			gpios = <&gpio3 17 GPIO_ACTIVE_HIGH>;
91			default-state = "on";
92		};
93
94		dbg3 {
95			label = "dbg3";
96			gpios = <&gpio4 3 GPIO_ACTIVE_HIGH>;
97			default-state = "on";
98		};
99
100		dbg4 {
101			label = "dbg4";
102			gpios = <&gpio5 9 GPIO_ACTIVE_HIGH>;
103			default-state = "on";
104		};
105	};
106};
107
108&iomuxc {
109	pinctrl-names = "default";
110
111	muxcgrp: imx8qxp-som {
112		pinctrl_gpio_leds: gpioledsgrp {
113			fsl,pins = <
114			SC_P_ESAI0_FST_LSIO_GPIO0_IO01		0x06000021
115			SC_P_ESAI0_TX0_LSIO_GPIO0_IO04		0x06000021
116			SC_P_SAI0_TXC_LSIO_GPIO0_IO26		0x06000021
117			SC_P_SAI1_RXD_LSIO_GPIO0_IO29		0x06000021
118			SC_P_FLEXCAN1_RX_LSIO_GPIO1_IO17	0x06000021
119			SC_P_FLEXCAN1_TX_LSIO_GPIO1_IO18	0x06000021
120			SC_P_QSPI0B_SCLK_LSIO_GPIO3_IO17	0x06000021
121			SC_P_QSPI0B_DATA0_LSIO_GPIO3_IO18	0x06000021
122			SC_P_QSPI0B_DATA1_LSIO_GPIO3_IO19	0x06000021
123			SC_P_USB_SS3_TC0_LSIO_GPIO4_IO03	0x06000021
124			SC_P_ENET0_RGMII_TXD1_LSIO_GPIO5_IO00	0x06000021
125			SC_P_ENET0_RGMII_TXD2_LSIO_GPIO5_IO01	0x06000021
126			SC_P_ENET0_REFCLK_125M_25M_LSIO_GPIO5_IO09	0x06000021
127			>;
128		};
129
130		pinctrl_lpi2c0: lpi2c0grp {
131			fsl,pins = <
132			SC_P_MIPI_CSI0_GPIO0_00_ADMA_I2C0_SCL	0x0C000020
133			SC_P_MIPI_CSI0_GPIO0_01_ADMA_I2C0_SDA	0x0C000020
134			>;
135		};
136
137		pinctrl_lpi2c1: lpi2c1grp {
138			fsl,pins = <
139			SC_P_MIPI_DSI0_GPIO0_00_ADMA_I2C1_SCL	0x0C000020
140			SC_P_MIPI_DSI0_GPIO0_01_ADMA_I2C1_SDA	0x0C000020
141			>;
142		};
143
144		pinctrl_lpuart2: lpuart2grp {
145			fsl,pins = <
146				SC_P_UART2_RX_ADMA_UART2_RX	0x06000020
147				SC_P_UART2_TX_ADMA_UART2_TX	0x06000020
148			>;
149		};
150
151		pinctrl_usdhc1: usdhc1grp {
152			fsl,pins = <
153				SC_P_EMMC0_CLK_CONN_EMMC0_CLK		0x06000041
154				SC_P_EMMC0_CMD_CONN_EMMC0_CMD		0x00000021
155				SC_P_EMMC0_DATA0_CONN_EMMC0_DATA0	0x00000021
156				SC_P_EMMC0_DATA1_CONN_EMMC0_DATA1	0x00000021
157				SC_P_EMMC0_DATA2_CONN_EMMC0_DATA2	0x00000021
158				SC_P_EMMC0_DATA3_CONN_EMMC0_DATA3	0x00000021
159				SC_P_EMMC0_DATA4_CONN_EMMC0_DATA4	0x00000021
160				SC_P_EMMC0_DATA5_CONN_EMMC0_DATA5	0x00000021
161				SC_P_EMMC0_DATA6_CONN_EMMC0_DATA6	0x00000021
162				SC_P_EMMC0_DATA7_CONN_EMMC0_DATA7	0x00000021
163				SC_P_EMMC0_STROBE_CONN_EMMC0_STROBE	0x06000041
164				SC_P_EMMC0_RESET_B_CONN_EMMC0_RESET_B	0x00000021
165				SC_P_ENET0_RGMII_TXC_LSIO_GPIO4_IO29	0x06000021
166			>;
167		};
168
169		pinctrl_usdhc2: usdhc2grp {
170			fsl,pins = <
171				SC_P_ENET0_RGMII_RXC_CONN_USDHC1_CLK	0x06000041
172				SC_P_ENET0_RGMII_RX_CTL_CONN_USDHC1_CMD	0x00000021
173				SC_P_ENET0_RGMII_RXD0_CONN_USDHC1_DATA0	0x00000021
174				SC_P_ENET0_RGMII_RXD1_CONN_USDHC1_DATA1	0x00000021
175				SC_P_ENET0_RGMII_RXD2_CONN_USDHC1_DATA2	0x00000021
176				SC_P_ENET0_RGMII_RXD3_CONN_USDHC1_DATA3	0x00000021
177				SC_P_ENET0_RGMII_TXD2_CONN_USDHC1_CD_B	0x06000021
178				//SC_P_ENET0_RGMII_TXD2_LSIO_GPIO5_IO01	0x06000021
179				SC_P_ENET0_RGMII_TX_CTL_LSIO_GPIO4_IO30	0x06000021
180			>;
181		};
182
183		pinctrl_fec2: fec2grp {
184			fsl,pins = <
185				SC_P_COMP_CTL_GPIO_1V8_3V3_ENET_ENETB0_PAD	0x000014a0
186				SC_P_COMP_CTL_GPIO_1V8_3V3_ENET_ENETB1_PAD	0x000014a0
187				SC_P_COMP_CTL_GPIO_1V8_3V3_GPIORHB_PAD		0x000514a0
188
189				SC_P_ENET0_MDC_CONN_ENET1_MDC                   0x00000060
190				SC_P_ENET0_MDIO_CONN_ENET1_MDIO                 0x00000060
191
192				SC_P_ESAI0_FSR_CONN_ENET1_RCLK50M_IN            0x00000060
193				SC_P_SPDIF0_RX_CONN_ENET1_RGMII_RXD0            0x00000060
194				SC_P_ESAI0_TX3_RX2_CONN_ENET1_RGMII_RXD1        0x00000060
195				SC_P_ESAI0_TX2_RX3_CONN_ENET1_RMII_RX_ER        0x00000060
196				SC_P_SPDIF0_TX_CONN_ENET1_RGMII_RX_CTL          0x00000060
197				SC_P_ESAI0_TX4_RX1_CONN_ENET1_RGMII_TXD0        0x00000060
198				SC_P_ESAI0_TX5_RX0_CONN_ENET1_RGMII_TXD1        0x00000060
199				SC_P_ESAI0_SCKR_CONN_ENET1_RGMII_TX_CTL         0x00000060	/* ERST: Reset pin */
200			>;
201		};
202	};
203};
204
205&i2c0 {
206	clock-frequency = <100000>;
207	pinctrl-names = "default";
208	pinctrl-0 = <&pinctrl_lpi2c0>;
209	status = "okay";
210};
211
212&i2c1 {
213	clock-frequency = <100000>;
214	pinctrl-names = "default";
215	pinctrl-0 = <&pinctrl_lpi2c1>;
216	status = "okay";
217};
218
219&lpuart2 {
220	pinctrl-names = "default";
221	pinctrl-0 = <&pinctrl_lpuart2>;
222	status = "okay";
223};
224
225&usdhc1 {
226	pinctrl-names = "default";
227	pinctrl-0 = <&pinctrl_usdhc1>;
228	clock-frequency=<52000000>;
229	no-1-8-v;
230	bus-width = <8>;
231	non-removable;
232	status = "okay";
233};
234
235&gpio0 {
236	status = "okay";
237};
238
239&gpio1 {
240	status = "okay";
241};
242
243&gpio2 {
244	status = "okay";
245};
246
247&gpio3 {
248	status = "okay";
249};
250
251&gpio4 {
252	status = "okay";
253};
254
255&gpio5 {
256	status = "okay";
257};
258
259&fec1 {
260	status ="disabled";
261};
262
263&fec2 {
264	pinctrl-names = "default";
265	pinctrl-0 = <&pinctrl_fec2>;
266	phy-mode = "rmii";
267
268	phy-handle = <&ethphy1>;
269	fsl,magic-packet;
270	status = "okay";
271
272	mdio {
273		#address-cells = <1>;
274		#size-cells = <0>;
275
276		ethphy0: ethernet-phy@0 {
277			compatible = "ethernet-phy-ieee802.3-c22";
278			reg = <0>;
279		};
280		ethphy1: ethernet-phy@1 {
281			compatible = "ethernet-phy-ieee802.3-c22";
282			reg = <1>;
283		};
284	};
285};
286