1// SPDX-License-Identifier: (GPL-2.0 OR MIT)
2/*
3 * Copyright (C) 2019 MediaTek Inc.
4 * Author: Mingming Lee <mingming.lee@mediatek.com>
5 *
6 */
7
8#include <dt-bindings/clock/mt8512-clk.h>
9#include <dt-bindings/gpio/gpio.h>
10#include <dt-bindings/interrupt-controller/irq.h>
11#include <dt-bindings/interrupt-controller/arm-gic.h>
12#include <dt-bindings/phy/phy.h>
13
14/ {
15	compatible = "mediatek,mt8512";
16	interrupt-parent = <&sysirq>;
17	#address-cells = <1>;
18	#size-cells = <1>;
19
20	gic: interrupt-controller@c000000 {
21		 compatible = "arm,gic-v3";
22		#interrupt-cells = <3>;
23		interrupt-parent = <&gic>;
24		interrupt-controller;
25		reg = <0xc000000 0x40000>,	/* GICD */
26			  <0xc080000 0x200000>; /* GICR */
27		interrupts = <GIC_PPI 9
28			(GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>;
29	};
30
31	topckgen: clock-controller@10000000 {
32		compatible = "mediatek,mt8512-topckgen";
33		reg = <0x10000000 0x1000>;
34		#clock-cells = <1>;
35	};
36
37	topckgen_cg: clock-controller-cg@10000000 {
38		compatible = "mediatek,mt8512-topckgen-cg";
39		reg = <0x10000000 0x1000>;
40		#clock-cells = <1>;
41	};
42
43	infracfg: clock-controller@10001000 {
44		compatible = "mediatek,mt8512-infracfg";
45		reg = <0x10001000 0x1000>;
46		#clock-cells = <1>;
47	};
48
49	pinctrl: pinctrl@10005000 {
50		compatible = "mediatek,mt8512-pinctrl";
51		reg = <0x10005000 0x1000>;
52		gpio: gpio-controller {
53			gpio-controller;
54			#gpio-cells = <2>;
55		};
56	};
57
58	watchdog0: watchdog@10007000 {
59		compatible = "mediatek,wdt";
60		reg = <0x10007000 0x1000>;
61		interrupts = <GIC_SPI 190 IRQ_TYPE_EDGE_FALLING>;
62		#reset-cells = <1>;
63		status = "disabled";
64		timeout-sec = <60>;
65		reset-on-timeout;
66	};
67
68	timer0: apxgpt@10008000 {
69		compatible = "mediatek,timer";
70		reg = <0x10008000 0x1000>;
71		interrupts = <GIC_SPI 138 IRQ_TYPE_LEVEL_LOW>;
72		clocks = <&topckgen CLK_TOP_SYS_26M_D2>,
73			 <&topckgen CLK_TOP_CLK32K>,
74			 <&infracfg CLK_INFRA_APXGPT>;
75		clock-names = "clk13m",
76			 "clk32k",
77			 "bus";
78	};
79
80	apmixedsys: clock-controller@1000c000 {
81		compatible = "mediatek,mt8512-apmixedsys";
82		reg = <0x1000c000 0x1000>;
83		#clock-cells = <1>;
84	};
85
86	sysirq: interrupt-controller@10200a80 {
87		compatible = "mediatek,sysirq";
88		interrupt-controller;
89		#interrupt-cells = <3>;
90		interrupt-parent = <&gic>;
91		reg = <0x10200a80 0x50>;
92	};
93
94	uart0: serial@11002000 {
95		compatible = "mediatek,hsuart";
96		reg = <0x11002000 0x1000>;
97		interrupts = <GIC_SPI 24 IRQ_TYPE_LEVEL_LOW>;
98		clocks = <&topckgen CLK_TOP_CLK26M>,
99			<&infracfg CLK_INFRA_UART0>;
100		clock-names = "baud", "bus";
101		status = "disabled";
102	};
103
104	usb3: usb@11213e00 {
105		compatible = "mediatek,mt8512-mtu3", "mediatek,mtu3";
106		reg = <0x11213e00 0x0100>;
107		reg-names = "ippc";
108		phys = <&u2port0 PHY_TYPE_USB2>, <&u2port1 PHY_TYPE_USB2>;
109		clocks = <&infracfg CLK_INFRA_USB_SYS>,
110			 <&topckgen CLK_TOP_SSUSB_TOP_CK_EN>,
111			 <&infracfg CLK_INFRA_ICUSB>;
112		clock-names = "sys_ck", "ref_ck", "mcu_ck";
113		#address-cells = <1>;
114		#size-cells = <1>;
115		ranges;
116		status = "disabled";
117
118		ssusb: usb@11210000 {
119			compatible = "mediatek,ssusb";
120			reg = <0x11210000 0x3e00>;
121			interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_LOW>;
122			reg-names = "mac";
123			status = "disabled";
124		};
125	};
126
127	u3phy: usb-phy@11cc0000 {
128		compatible = "mediatek,mt8512-tphy",
129			     "mediatek,generic-tphy-v2";
130		#address-cells = <1>;
131		#size-cells = <1>;
132		ranges;
133		status = "disabled";
134
135		u2port0: usb-phy@11cc0000 {
136			reg = <0x11cc0000 0x400>;
137			clocks = <&topckgen CLK_TOP_USB20_48M_EN>;
138			clock-names = "ref";
139			#phy-cells = <1>;
140			status = "okay";
141		};
142
143		u2port1: usb-phy@11c40000 {
144			reg = <0x11c40000 0x400>;
145			#phy-cells = <1>;
146			status = "okay";
147		};
148	};
149
150	mmc0: mmc@11230000 {
151		compatible = "mediatek,mt8512-mmc";
152		reg = <0x11230000 0x1000>,
153		      <0x11cd0000 0x1000>;
154		interrupts = <GIC_SPI 78 IRQ_TYPE_LEVEL_LOW>;
155		clocks = <&topckgen CLK_TOP_MSDC50_0_SEL>,
156			 <&infracfg CLK_INFRA_MSDC0>,
157			 <&infracfg CLK_INFRA_MSDC0_SRC>;
158		clock-names = "source", "hclk", "source_cg";
159		status = "disabled";
160	};
161
162};
163