1// SPDX-License-Identifier: GPL-2.0+ OR X11
2/*
3 * (C) Copyright 2017 Theobroma Systems Design und Consulting GmbH
4 */
5/ {
6	chosen {
7		u-boot,spl-boot-order = &emmc;
8	};
9};
10
11&dmc {
12	u-boot,dm-pre-reloc;
13
14	/*
15	 * PX5-evb(2GB) need to use CBRD mode, or else the dram is not correct
16	 * See doc/device-tree-bindings/clock/rockchip,rk3368-dmc.txt for
17	 * details on the 'rockchip,memory-schedule' property and how it
18	 * affects the physical-address to device-address mapping.
19	 */
20	rockchip,memory-schedule = <DMC_MSCH_CBRD>;
21	rockchip,ddr-frequency = <800000000>;
22	rockchip,ddr-speed-bin = <DDR3_1600K>;
23
24	status = "okay";
25};
26
27&pinctrl {
28	u-boot,dm-pre-reloc;
29};
30
31&service_msch {
32	u-boot,dm-pre-reloc;
33};
34
35&dmc {
36	u-boot,dm-pre-reloc;
37	status = "okay";
38};
39
40&pmugrf {
41	u-boot,dm-pre-reloc;
42};
43
44&sgrf {
45	u-boot,dm-pre-reloc;
46};
47
48&cru {
49	u-boot,dm-pre-reloc;
50};
51
52&grf {
53	u-boot,dm-pre-reloc;
54};
55
56&uart4 {
57	u-boot,dm-pre-reloc;
58};
59
60&emmc {
61	/* mmc to sram can't do dma, prevent aborts transferring TF-A parts */
62	u-boot,spl-fifo-mode;
63	u-boot,dm-pre-reloc;
64};
65
66&timer0 {
67	u-boot,dm-pre-reloc;
68	clock-frequency = <24000000>;
69	status = "okay";
70};
71