1// SPDX-License-Identifier: GPL-2.0+ 2 3#include <dt-bindings/memory/stm32-sdram.h> 4 5/{ 6 clocks { 7 u-boot,dm-pre-reloc; 8 }; 9 10 aliases { 11 gpio0 = &gpioa; 12 gpio1 = &gpiob; 13 gpio2 = &gpioc; 14 gpio3 = &gpiod; 15 gpio4 = &gpioe; 16 gpio5 = &gpiof; 17 gpio6 = &gpiog; 18 gpio7 = &gpioh; 19 gpio8 = &gpioi; 20 gpio9 = &gpioj; 21 gpio10 = &gpiok; 22 mmc0 = &sdmmc1; 23 }; 24 25 soc { 26 u-boot,dm-pre-reloc; 27 pin-controller { 28 u-boot,dm-pre-reloc; 29 }; 30 31 fmc: fmc@52004000 { 32 compatible = "st,stm32h7-fmc"; 33 reg = <0x52004000 0x1000>; 34 clocks = <&rcc FMC_CK>; 35 36 pinctrl-0 = <&fmc_pins>; 37 pinctrl-names = "default"; 38 status = "okay"; 39 40 /* 41 * Memory configuration from sdram datasheet IS42S32800G-6BLI 42 * first bank is bank@0 43 * second bank is bank@1 44 */ 45 bank1: bank@1 { 46 st,sdram-control = /bits/ 8 <NO_COL_9 47 NO_ROW_12 48 MWIDTH_32 49 BANKS_4 50 CAS_2 51 SDCLK_3 52 RD_BURST_EN 53 RD_PIPE_DL_0>; 54 st,sdram-timing = /bits/ 8 <TMRD_1 55 TXSR_1 56 TRAS_1 57 TRC_6 58 TRP_2 59 TWR_1 60 TRCD_1>; 61 st,sdram-refcount = <1539>; 62 }; 63 }; 64 }; 65}; 66 67&clk_hse { 68 u-boot,dm-pre-reloc; 69}; 70 71&clk_i2s { 72 u-boot,dm-pre-reloc; 73}; 74 75&clk_lse { 76 u-boot,dm-pre-reloc; 77}; 78 79 80&fmc { 81 u-boot,dm-pre-reloc; 82}; 83 84&gpioa { 85 u-boot,dm-pre-reloc; 86 compatible = "st,stm32-gpio"; 87}; 88 89&gpiob { 90 u-boot,dm-pre-reloc; 91 compatible = "st,stm32-gpio"; 92}; 93 94&gpioc { 95 u-boot,dm-pre-reloc; 96 compatible = "st,stm32-gpio"; 97}; 98 99&gpiod { 100 u-boot,dm-pre-reloc; 101 compatible = "st,stm32-gpio"; 102}; 103 104&gpioe { 105 u-boot,dm-pre-reloc; 106 compatible = "st,stm32-gpio"; 107}; 108 109&gpiof { 110 u-boot,dm-pre-reloc; 111 compatible = "st,stm32-gpio"; 112}; 113 114&gpiog { 115 u-boot,dm-pre-reloc; 116 compatible = "st,stm32-gpio"; 117}; 118 119&gpioh { 120 u-boot,dm-pre-reloc; 121 compatible = "st,stm32-gpio"; 122}; 123 124&gpioi { 125 u-boot,dm-pre-reloc; 126 compatible = "st,stm32-gpio"; 127}; 128 129&gpioj { 130 u-boot,dm-pre-reloc; 131 compatible = "st,stm32-gpio"; 132}; 133 134&gpiok { 135 u-boot,dm-pre-reloc; 136 compatible = "st,stm32-gpio"; 137}; 138 139&pinctrl { 140 fmc_pins: fmc@0 { 141 pins { 142 pinmux = <STM32_PINMUX('D', 0, AF12)>, 143 <STM32_PINMUX('D', 1, AF12)>, 144 <STM32_PINMUX('D', 8, AF12)>, 145 <STM32_PINMUX('D', 9, AF12)>, 146 <STM32_PINMUX('D',10, AF12)>, 147 <STM32_PINMUX('D',14, AF12)>, 148 <STM32_PINMUX('D',15, AF12)>, 149 150 <STM32_PINMUX('E', 0, AF12)>, 151 <STM32_PINMUX('E', 1, AF12)>, 152 <STM32_PINMUX('E', 7, AF12)>, 153 <STM32_PINMUX('E', 8, AF12)>, 154 <STM32_PINMUX('E', 9, AF12)>, 155 <STM32_PINMUX('E',10, AF12)>, 156 <STM32_PINMUX('E',11, AF12)>, 157 <STM32_PINMUX('E',12, AF12)>, 158 <STM32_PINMUX('E',13, AF12)>, 159 <STM32_PINMUX('E',14, AF12)>, 160 <STM32_PINMUX('E',15, AF12)>, 161 162 <STM32_PINMUX('F', 0, AF12)>, 163 <STM32_PINMUX('F', 1, AF12)>, 164 <STM32_PINMUX('F', 2, AF12)>, 165 <STM32_PINMUX('F', 3, AF12)>, 166 <STM32_PINMUX('F', 4, AF12)>, 167 <STM32_PINMUX('F', 5, AF12)>, 168 <STM32_PINMUX('F',11, AF12)>, 169 <STM32_PINMUX('F',12, AF12)>, 170 <STM32_PINMUX('F',13, AF12)>, 171 <STM32_PINMUX('F',14, AF12)>, 172 <STM32_PINMUX('F',15, AF12)>, 173 174 <STM32_PINMUX('G', 0, AF12)>, 175 <STM32_PINMUX('G', 1, AF12)>, 176 <STM32_PINMUX('G', 2, AF12)>, 177 <STM32_PINMUX('G', 4, AF12)>, 178 <STM32_PINMUX('G', 5, AF12)>, 179 <STM32_PINMUX('G', 8, AF12)>, 180 <STM32_PINMUX('G',15, AF12)>, 181 182 <STM32_PINMUX('H', 5, AF12)>, 183 <STM32_PINMUX('H', 6, AF12)>, 184 <STM32_PINMUX('H', 7, AF12)>, 185 <STM32_PINMUX('H', 8, AF12)>, 186 <STM32_PINMUX('H', 9, AF12)>, 187 <STM32_PINMUX('H',10, AF12)>, 188 <STM32_PINMUX('H',11, AF12)>, 189 <STM32_PINMUX('H',12, AF12)>, 190 <STM32_PINMUX('H',13, AF12)>, 191 <STM32_PINMUX('H',14, AF12)>, 192 <STM32_PINMUX('H',15, AF12)>, 193 194 <STM32_PINMUX('I', 0, AF12)>, 195 <STM32_PINMUX('I', 1, AF12)>, 196 <STM32_PINMUX('I', 2, AF12)>, 197 <STM32_PINMUX('I', 3, AF12)>, 198 <STM32_PINMUX('I', 4, AF12)>, 199 <STM32_PINMUX('I', 5, AF12)>, 200 <STM32_PINMUX('I', 6, AF12)>, 201 <STM32_PINMUX('I', 7, AF12)>, 202 <STM32_PINMUX('I', 9, AF12)>, 203 <STM32_PINMUX('I',10, AF12)>; 204 205 slew-rate = <3>; 206 }; 207 }; 208}; 209 210&pwrcfg { 211 u-boot,dm-pre-reloc; 212}; 213 214&rcc { 215 u-boot,dm-pre-reloc; 216}; 217 218&sdmmc1 { 219 compatible = "st,stm32-sdmmc2", "arm,pl18x", "arm,primecell"; 220}; 221 222&timer5 { 223 u-boot,dm-pre-reloc; 224}; 225