1// SPDX-License-Identifier: GPL-2.0+ OR X11
2/*
3 * Copyright 2017 - Alexandre Torgue <alexandre.torgue@st.com>
4 *
5 */
6
7#include "armv7-m.dtsi"
8#include <dt-bindings/clock/stm32h7-clks.h>
9#include <dt-bindings/mfd/stm32h7-rcc.h>
10#include <dt-bindings/interrupt-controller/irq.h>
11
12/ {
13	#address-cells = <1>;
14	#size-cells = <1>;
15
16	clocks {
17		clk_hse: clk-hse {
18			#clock-cells = <0>;
19			compatible = "fixed-clock";
20			clock-frequency = <0>;
21		};
22
23		clk_lse: clk-lse {
24			#clock-cells = <0>;
25			compatible = "fixed-clock";
26			clock-frequency = <32768>;
27		};
28
29		clk_i2s: i2s_ckin {
30			#clock-cells = <0>;
31			compatible = "fixed-clock";
32			clock-frequency = <0>;
33		};
34	};
35
36	soc {
37		timer5: timer@40000c00 {
38			compatible = "st,stm32-timer";
39			reg = <0x40000c00 0x400>;
40			interrupts = <50>;
41			clocks = <&rcc TIM5_CK>;
42		};
43
44		lptimer1: timer@40002400 {
45			#address-cells = <1>;
46			#size-cells = <0>;
47			compatible = "st,stm32-lptimer";
48			reg = <0x40002400 0x400>;
49			clocks = <&rcc LPTIM1_CK>;
50			clock-names = "mux";
51			status = "disabled";
52
53			pwm {
54				compatible = "st,stm32-pwm-lp";
55				#pwm-cells = <3>;
56				status = "disabled";
57			};
58
59			trigger@0 {
60				compatible = "st,stm32-lptimer-trigger";
61				reg = <0>;
62				status = "disabled";
63			};
64
65			counter {
66				compatible = "st,stm32-lptimer-counter";
67				status = "disabled";
68			};
69		};
70
71		spi2: spi@40003800 {
72			#address-cells = <1>;
73			#size-cells = <0>;
74			compatible = "st,stm32h7-spi";
75			reg = <0x40003800 0x400>;
76			interrupts = <36>;
77			resets = <&rcc STM32H7_APB1L_RESET(SPI2)>;
78			clocks = <&rcc SPI2_CK>;
79			status = "disabled";
80
81		};
82
83		spi3: spi@40003c00 {
84			#address-cells = <1>;
85			#size-cells = <0>;
86			compatible = "st,stm32h7-spi";
87			reg = <0x40003c00 0x400>;
88			interrupts = <51>;
89			resets = <&rcc STM32H7_APB1L_RESET(SPI3)>;
90			clocks = <&rcc SPI3_CK>;
91			status = "disabled";
92		};
93
94		usart2: serial@40004400 {
95			compatible = "st,stm32h7-uart";
96			reg = <0x40004400 0x400>;
97			interrupts = <38>;
98			status = "disabled";
99			clocks = <&rcc USART2_CK>;
100		};
101
102		i2c1: i2c@40005400 {
103			compatible = "st,stm32f7-i2c";
104			#address-cells = <1>;
105			#size-cells = <0>;
106			reg = <0x40005400 0x400>;
107			interrupts = <31>,
108				     <32>;
109			resets = <&rcc STM32H7_APB1L_RESET(I2C1)>;
110			clocks = <&rcc I2C1_CK>;
111			status = "disabled";
112		};
113
114		i2c2: i2c@40005800 {
115			compatible = "st,stm32f7-i2c";
116			#address-cells = <1>;
117			#size-cells = <0>;
118			reg = <0x40005800 0x400>;
119			interrupts = <33>,
120				     <34>;
121			resets = <&rcc STM32H7_APB1L_RESET(I2C2)>;
122			clocks = <&rcc I2C2_CK>;
123			status = "disabled";
124		};
125
126		i2c3: i2c@40005C00 {
127			compatible = "st,stm32f7-i2c";
128			#address-cells = <1>;
129			#size-cells = <0>;
130			reg = <0x40005C00 0x400>;
131			interrupts = <72>,
132				     <73>;
133			resets = <&rcc STM32H7_APB1L_RESET(I2C3)>;
134			clocks = <&rcc I2C3_CK>;
135			status = "disabled";
136		};
137
138		dac: dac@40007400 {
139			compatible = "st,stm32h7-dac-core";
140			reg = <0x40007400 0x400>;
141			clocks = <&rcc DAC12_CK>;
142			clock-names = "pclk";
143			#address-cells = <1>;
144			#size-cells = <0>;
145			status = "disabled";
146
147			dac1: dac@1 {
148				compatible = "st,stm32-dac";
149				#io-channel-cells = <1>;
150				reg = <1>;
151				status = "disabled";
152			};
153
154			dac2: dac@2 {
155				compatible = "st,stm32-dac";
156				#io-channel-cells = <1>;
157				reg = <2>;
158				status = "disabled";
159			};
160		};
161
162		usart1: serial@40011000 {
163			compatible = "st,stm32h7-uart";
164			reg = <0x40011000 0x400>;
165			interrupts = <37>;
166			status = "disabled";
167			clocks = <&rcc USART1_CK>;
168		};
169
170		spi1: spi@40013000 {
171			#address-cells = <1>;
172			#size-cells = <0>;
173			compatible = "st,stm32h7-spi";
174			reg = <0x40013000 0x400>;
175			interrupts = <35>;
176			resets = <&rcc STM32H7_APB2_RESET(SPI1)>;
177			clocks = <&rcc SPI1_CK>;
178			status = "disabled";
179		};
180
181		spi4: spi@40013400 {
182			#address-cells = <1>;
183			#size-cells = <0>;
184			compatible = "st,stm32h7-spi";
185			reg = <0x40013400 0x400>;
186			interrupts = <84>;
187			resets = <&rcc STM32H7_APB2_RESET(SPI4)>;
188			clocks = <&rcc SPI4_CK>;
189			status = "disabled";
190		};
191
192		spi5: spi@40015000 {
193			#address-cells = <1>;
194			#size-cells = <0>;
195			compatible = "st,stm32h7-spi";
196			reg = <0x40015000 0x400>;
197			interrupts = <85>;
198			resets = <&rcc STM32H7_APB2_RESET(SPI5)>;
199			clocks = <&rcc SPI5_CK>;
200			status = "disabled";
201		};
202
203		dma1: dma-controller@40020000 {
204			compatible = "st,stm32-dma";
205			reg = <0x40020000 0x400>;
206			interrupts = <11>,
207				     <12>,
208				     <13>,
209				     <14>,
210				     <15>,
211				     <16>,
212				     <17>,
213				     <47>;
214			clocks = <&rcc DMA1_CK>;
215			#dma-cells = <4>;
216			st,mem2mem;
217			dma-requests = <8>;
218			status = "disabled";
219		};
220
221		dma2: dma-controller@40020400 {
222			compatible = "st,stm32-dma";
223			reg = <0x40020400 0x400>;
224			interrupts = <56>,
225				     <57>,
226				     <58>,
227				     <59>,
228				     <60>,
229				     <68>,
230				     <69>,
231				     <70>;
232			clocks = <&rcc DMA2_CK>;
233			#dma-cells = <4>;
234			st,mem2mem;
235			dma-requests = <8>;
236			status = "disabled";
237		};
238
239		dmamux1: dma-router@40020800 {
240			compatible = "st,stm32h7-dmamux";
241			reg = <0x40020800 0x1c>;
242			#dma-cells = <3>;
243			dma-channels = <16>;
244			dma-requests = <128>;
245			dma-masters = <&dma1 &dma2>;
246			clocks = <&rcc DMA1_CK>;
247		};
248
249		adc_12: adc@40022000 {
250			compatible = "st,stm32h7-adc-core";
251			reg = <0x40022000 0x400>;
252			interrupts = <18>;
253			clocks = <&rcc ADC12_CK>;
254			clock-names = "bus";
255			interrupt-controller;
256			#interrupt-cells = <1>;
257			#address-cells = <1>;
258			#size-cells = <0>;
259			status = "disabled";
260
261			adc1: adc@0 {
262				compatible = "st,stm32h7-adc";
263				#io-channel-cells = <1>;
264				reg = <0x0>;
265				interrupt-parent = <&adc_12>;
266				interrupts = <0>;
267				status = "disabled";
268			};
269
270			adc2: adc@100 {
271				compatible = "st,stm32h7-adc";
272				#io-channel-cells = <1>;
273				reg = <0x100>;
274				interrupt-parent = <&adc_12>;
275				interrupts = <1>;
276				status = "disabled";
277			};
278		};
279
280		usbotg_hs: usb@40040000 {
281			compatible = "st,stm32f7-hsotg";
282			reg = <0x40040000 0x40000>;
283			interrupts = <77>;
284			clocks = <&rcc USB1OTG_CK>;
285			clock-names = "otg";
286			g-rx-fifo-size = <256>;
287			g-np-tx-fifo-size = <32>;
288			g-tx-fifo-size = <128 128 64 64 64 64 32 32>;
289			status = "disabled";
290		};
291
292		usbotg_fs: usb@40080000 {
293			compatible = "st,stm32f4x9-fsotg";
294			reg = <0x40080000 0x40000>;
295			interrupts = <101>;
296			clocks = <&rcc USB2OTG_CK>;
297			clock-names = "otg";
298			status = "disabled";
299		};
300
301		ltdc: display-controller@50001000 {
302			compatible = "st,stm32-ltdc";
303			reg = <0x50001000 0x200>;
304			interrupts = <88>, <89>;
305			resets = <&rcc STM32H7_APB3_RESET(LTDC)>;
306			clocks = <&rcc LTDC_CK>;
307			clock-names = "lcd";
308			status = "disabled";
309		};
310
311		mdma1: dma-controller@52000000 {
312			compatible = "st,stm32h7-mdma";
313			reg = <0x52000000 0x1000>;
314			interrupts = <122>;
315			clocks = <&rcc MDMA_CK>;
316			#dma-cells = <5>;
317			dma-channels = <16>;
318			dma-requests = <32>;
319		};
320
321		sdmmc1: sdmmc@52007000 {
322			compatible = "arm,pl18x", "arm,primecell";
323			arm,primecell-periphid = <0x10153180>;
324			reg = <0x52007000 0x1000>;
325			interrupts = <49>;
326			interrupt-names	= "cmd_irq";
327			clocks = <&rcc SDMMC1_CK>;
328			clock-names = "apb_pclk";
329			resets = <&rcc STM32H7_AHB3_RESET(SDMMC1)>;
330			cap-sd-highspeed;
331			cap-mmc-highspeed;
332			max-frequency = <120000000>;
333		};
334
335		exti: interrupt-controller@58000000 {
336			compatible = "st,stm32h7-exti";
337			interrupt-controller;
338			#interrupt-cells = <2>;
339			reg = <0x58000000 0x400>;
340			interrupts = <1>, <2>, <3>, <6>, <7>, <8>, <9>, <10>, <23>, <40>, <41>, <62>, <76>;
341		};
342
343		syscfg: syscon@58000400 {
344			compatible = "st,stm32-syscfg", "syscon";
345			reg = <0x58000400 0x400>;
346		};
347
348		spi6: spi@58001400 {
349			#address-cells = <1>;
350			#size-cells = <0>;
351			compatible = "st,stm32h7-spi";
352			reg = <0x58001400 0x400>;
353			interrupts = <86>;
354			resets = <&rcc STM32H7_APB4_RESET(SPI6)>;
355			clocks = <&rcc SPI6_CK>;
356			status = "disabled";
357		};
358
359		i2c4: i2c@58001C00 {
360			compatible = "st,stm32f7-i2c";
361			#address-cells = <1>;
362			#size-cells = <0>;
363			reg = <0x58001C00 0x400>;
364			interrupts = <95>,
365				     <96>;
366			resets = <&rcc STM32H7_APB4_RESET(I2C4)>;
367			clocks = <&rcc I2C4_CK>;
368			status = "disabled";
369		};
370
371		lptimer2: timer@58002400 {
372			#address-cells = <1>;
373			#size-cells = <0>;
374			compatible = "st,stm32-lptimer";
375			reg = <0x58002400 0x400>;
376			clocks = <&rcc LPTIM2_CK>;
377			clock-names = "mux";
378			status = "disabled";
379
380			pwm {
381				compatible = "st,stm32-pwm-lp";
382				#pwm-cells = <3>;
383				status = "disabled";
384			};
385
386			trigger@1 {
387				compatible = "st,stm32-lptimer-trigger";
388				reg = <1>;
389				status = "disabled";
390			};
391
392			counter {
393				compatible = "st,stm32-lptimer-counter";
394				status = "disabled";
395			};
396		};
397
398		lptimer3: timer@58002800 {
399			#address-cells = <1>;
400			#size-cells = <0>;
401			compatible = "st,stm32-lptimer";
402			reg = <0x58002800 0x400>;
403			clocks = <&rcc LPTIM3_CK>;
404			clock-names = "mux";
405			status = "disabled";
406
407			pwm {
408				compatible = "st,stm32-pwm-lp";
409				#pwm-cells = <3>;
410				status = "disabled";
411			};
412
413			trigger@2 {
414				compatible = "st,stm32-lptimer-trigger";
415				reg = <2>;
416				status = "disabled";
417			};
418		};
419
420		lptimer4: timer@58002c00 {
421			#address-cells = <1>;
422			#size-cells = <0>;
423			compatible = "st,stm32-lptimer";
424			reg = <0x58002c00 0x400>;
425			clocks = <&rcc LPTIM4_CK>;
426			clock-names = "mux";
427			status = "disabled";
428
429			pwm {
430				compatible = "st,stm32-pwm-lp";
431				#pwm-cells = <3>;
432				status = "disabled";
433			};
434		};
435
436		lptimer5: timer@58003000 {
437			#address-cells = <1>;
438			#size-cells = <0>;
439			compatible = "st,stm32-lptimer";
440			reg = <0x58003000 0x400>;
441			clocks = <&rcc LPTIM5_CK>;
442			clock-names = "mux";
443			status = "disabled";
444
445			pwm {
446				compatible = "st,stm32-pwm-lp";
447				#pwm-cells = <3>;
448				status = "disabled";
449			};
450		};
451
452		vrefbuf: regulator@58003c00 {
453			compatible = "st,stm32-vrefbuf";
454			reg = <0x58003C00 0x8>;
455			clocks = <&rcc VREF_CK>;
456			regulator-min-microvolt = <1500000>;
457			regulator-max-microvolt = <2500000>;
458			status = "disabled";
459		};
460
461		rtc: rtc@58004000 {
462			compatible = "st,stm32h7-rtc";
463			reg = <0x58004000 0x400>;
464			clocks = <&rcc RTCAPB_CK>, <&rcc RTC_CK>;
465			clock-names = "pclk", "rtc_ck";
466			assigned-clocks = <&rcc RTC_CK>;
467			assigned-clock-parents = <&rcc LSE_CK>;
468			interrupt-parent = <&exti>;
469			interrupts = <17 IRQ_TYPE_EDGE_RISING>;
470			st,syscfg = <&pwrcfg 0x00 0x100>;
471			status = "disabled";
472		};
473
474		rcc: reset-clock-controller@58024400 {
475			compatible = "st,stm32h743-rcc", "st,stm32-rcc";
476			reg = <0x58024400 0x400>;
477			#clock-cells = <1>;
478			#reset-cells = <1>;
479			clocks = <&clk_hse>, <&clk_lse>, <&clk_i2s>;
480			st,syscfg = <&pwrcfg>;
481		};
482
483		pwrcfg: power-config@58024800 {
484			compatible = "st,stm32-power-config", "syscon";
485			reg = <0x58024800 0x400>;
486		};
487
488		adc_3: adc@58026000 {
489			compatible = "st,stm32h7-adc-core";
490			reg = <0x58026000 0x400>;
491			interrupts = <127>;
492			clocks = <&rcc ADC3_CK>;
493			clock-names = "bus";
494			interrupt-controller;
495			#interrupt-cells = <1>;
496			#address-cells = <1>;
497			#size-cells = <0>;
498			status = "disabled";
499
500			adc3: adc@0 {
501				compatible = "st,stm32h7-adc";
502				#io-channel-cells = <1>;
503				reg = <0x0>;
504				interrupt-parent = <&adc_3>;
505				interrupts = <0>;
506				status = "disabled";
507			};
508		};
509
510		mac: ethernet@40028000 {
511			compatible = "st,stm32-dwmac", "snps,dwmac-4.10a";
512			reg = <0x40028000 0x8000>;
513			reg-names = "stmmaceth";
514			interrupts = <61>;
515			interrupt-names = "macirq";
516			clock-names = "stmmaceth", "mac-clk-tx", "mac-clk-rx";
517			clocks = <&rcc ETH1MAC_CK>, <&rcc ETH1TX_CK>, <&rcc ETH1RX_CK>;
518			st,syscon = <&syscfg 0x4>;
519			snps,pbl = <8>;
520			status = "disabled";
521		};
522	};
523};
524
525&systick {
526	clock-frequency = <250000000>;
527	status = "okay";
528};
529