1// SPDX-License-Identifier: (GPL-2.0+ OR MIT) 2// Copyright (C) 2020 Arm Ltd. 3// based on the H6 dtsi, which is: 4// Copyright (C) 2017 Icenowy Zheng <icenowy@aosc.io> 5 6#include <dt-bindings/interrupt-controller/arm-gic.h> 7#include <dt-bindings/clock/sun50i-h616-ccu.h> 8#include <dt-bindings/clock/sun50i-h6-r-ccu.h> 9#include <dt-bindings/reset/sun50i-h616-ccu.h> 10#include <dt-bindings/reset/sun50i-h6-r-ccu.h> 11 12/ { 13 interrupt-parent = <&gic>; 14 #address-cells = <2>; 15 #size-cells = <2>; 16 17 cpus { 18 #address-cells = <1>; 19 #size-cells = <0>; 20 21 cpu0: cpu@0 { 22 compatible = "arm,cortex-a53"; 23 device_type = "cpu"; 24 reg = <0>; 25 enable-method = "psci"; 26 clocks = <&ccu CLK_CPUX>; 27 }; 28 29 cpu1: cpu@1 { 30 compatible = "arm,cortex-a53"; 31 device_type = "cpu"; 32 reg = <1>; 33 enable-method = "psci"; 34 clocks = <&ccu CLK_CPUX>; 35 }; 36 37 cpu2: cpu@2 { 38 compatible = "arm,cortex-a53"; 39 device_type = "cpu"; 40 reg = <2>; 41 enable-method = "psci"; 42 clocks = <&ccu CLK_CPUX>; 43 }; 44 45 cpu3: cpu@3 { 46 compatible = "arm,cortex-a53"; 47 device_type = "cpu"; 48 reg = <3>; 49 enable-method = "psci"; 50 clocks = <&ccu CLK_CPUX>; 51 }; 52 }; 53 54 osc24M: osc24M_clk { 55 #clock-cells = <0>; 56 compatible = "fixed-clock"; 57 clock-frequency = <24000000>; 58 clock-output-names = "osc24M"; 59 }; 60 61 pmu { 62 compatible = "arm,cortex-a53-pmu"; 63 interrupts = <GIC_SPI 140 IRQ_TYPE_LEVEL_HIGH>, 64 <GIC_SPI 141 IRQ_TYPE_LEVEL_HIGH>, 65 <GIC_SPI 142 IRQ_TYPE_LEVEL_HIGH>, 66 <GIC_SPI 143 IRQ_TYPE_LEVEL_HIGH>; 67 interrupt-affinity = <&cpu0>, <&cpu1>, <&cpu2>, <&cpu3>; 68 }; 69 70 psci { 71 compatible = "arm,psci-0.2"; 72 method = "smc"; 73 }; 74 75 timer { 76 compatible = "arm,armv8-timer"; 77 arm,no-tick-in-suspend; 78 interrupts = <GIC_PPI 13 79 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>, 80 <GIC_PPI 14 81 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>, 82 <GIC_PPI 11 83 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>, 84 <GIC_PPI 10 85 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>; 86 }; 87 88 soc { 89 compatible = "simple-bus"; 90 #address-cells = <1>; 91 #size-cells = <1>; 92 ranges = <0x0 0x0 0x0 0x40000000>; 93 94 syscon: syscon@3000000 { 95 compatible = "allwinner,sun50i-h616-system-control"; 96 reg = <0x03000000 0x1000>; 97 #address-cells = <1>; 98 #size-cells = <1>; 99 ranges; 100 101 sram_c: sram@28000 { 102 compatible = "mmio-sram"; 103 reg = <0x00028000 0x30000>; 104 #address-cells = <1>; 105 #size-cells = <1>; 106 ranges = <0 0x00028000 0x30000>; 107 }; 108 }; 109 110 ccu: clock@3001000 { 111 compatible = "allwinner,sun50i-h616-ccu"; 112 reg = <0x03001000 0x1000>; 113 clocks = <&osc24M>, <&rtc 0>, <&rtc 2>; 114 clock-names = "hosc", "losc", "iosc"; 115 #clock-cells = <1>; 116 #reset-cells = <1>; 117 }; 118 119 watchdog: watchdog@30090a0 { 120 compatible = "allwinner,sun50i-h616-wdt", 121 "allwinner,sun6i-a31-wdt"; 122 reg = <0x030090a0 0x20>; 123 interrupts = <GIC_SPI 50 IRQ_TYPE_LEVEL_HIGH>; 124 clocks = <&osc24M>; 125 status = "disabled"; 126 }; 127 128 pio: pinctrl@300b000 { 129 compatible = "allwinner,sun50i-h616-pinctrl"; 130 reg = <0x0300b000 0x400>; 131 interrupts = <GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH>, 132 <GIC_SPI 52 IRQ_TYPE_LEVEL_HIGH>, 133 <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>, 134 <GIC_SPI 43 IRQ_TYPE_LEVEL_HIGH>, 135 <GIC_SPI 54 IRQ_TYPE_LEVEL_HIGH>, 136 <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>, 137 <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>, 138 <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>; 139 clocks = <&ccu CLK_APB1>, <&osc24M>, <&rtc 0>; 140 clock-names = "apb", "hosc", "losc"; 141 gpio-controller; 142 #gpio-cells = <3>; 143 interrupt-controller; 144 #interrupt-cells = <3>; 145 146 ext_rgmii_pins: rgmii-pins { 147 pins = "PI0", "PI1", "PI2", "PI3", "PI4", 148 "PI5", "PI7", "PI8", "PI9", "PI10", 149 "PI11", "PI12", "PI13", "PI14", "PI15", 150 "PI16"; 151 function = "emac0"; 152 drive-strength = <40>; 153 }; 154 155 i2c0_pins: i2c0-pins { 156 pins = "PI6", "PI7"; 157 function = "i2c0"; 158 }; 159 160 i2c3_ph_pins: i2c3-ph-pins { 161 pins = "PH4", "PH5"; 162 function = "i2c3"; 163 }; 164 165 ir_rx_pin: ir_rx_pin { 166 pins = "PH10"; 167 function = "ir_rx"; 168 }; 169 170 mmc0_pins: mmc0-pins { 171 pins = "PF0", "PF1", "PF2", "PF3", 172 "PF4", "PF5"; 173 function = "mmc0"; 174 drive-strength = <30>; 175 bias-pull-up; 176 }; 177 178 mmc1_pins: mmc1-pins { 179 pins = "PG0", "PG1", "PG2", "PG3", 180 "PG4", "PG5"; 181 function = "mmc1"; 182 drive-strength = <30>; 183 bias-pull-up; 184 }; 185 186 mmc2_pins: mmc2-pins { 187 pins = "PC0", "PC1", "PC5", "PC6", 188 "PC8", "PC9", "PC10", "PC11", 189 "PC13", "PC14", "PC15", "PC16"; 190 function = "mmc2"; 191 drive-strength = <30>; 192 bias-pull-up; 193 }; 194 195 spi0_pins: spi0-pins { 196 pins = "PC0", "PC2", "PC3", "PC4"; 197 function = "spi0"; 198 }; 199 200 spi1_pins: spi1-pins { 201 pins = "PH6", "PH7", "PH8"; 202 function = "spi1"; 203 }; 204 205 spi1_cs_pin: spi1-cs-pin { 206 pins = "PH5"; 207 function = "spi1"; 208 }; 209 210 uart0_ph_pins: uart0-ph-pins { 211 pins = "PH0", "PH1"; 212 function = "uart0"; 213 }; 214 215 uart1_pins: uart1-pins { 216 pins = "PG6", "PG7"; 217 function = "uart1"; 218 }; 219 220 uart1_rts_cts_pins: uart1-rts-cts-pins { 221 pins = "PG8", "PG9"; 222 function = "uart1"; 223 }; 224 }; 225 226 gic: interrupt-controller@3021000 { 227 compatible = "arm,gic-400"; 228 reg = <0x03021000 0x1000>, 229 <0x03022000 0x2000>, 230 <0x03024000 0x2000>, 231 <0x03026000 0x2000>; 232 interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>; 233 interrupt-controller; 234 #interrupt-cells = <3>; 235 }; 236 237 mmc0: mmc@4020000 { 238 compatible = "allwinner,sun50i-h616-mmc", 239 "allwinner,sun50i-a100-mmc"; 240 reg = <0x04020000 0x1000>; 241 clocks = <&ccu CLK_BUS_MMC0>, <&ccu CLK_MMC0>; 242 clock-names = "ahb", "mmc"; 243 resets = <&ccu RST_BUS_MMC0>; 244 reset-names = "ahb"; 245 interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>; 246 pinctrl-names = "default"; 247 pinctrl-0 = <&mmc0_pins>; 248 status = "disabled"; 249 cap-sd-highspeed; 250 cap-mmc-highspeed; 251 mmc-ddr-3_3v; 252 mmc-ddr-1_8v; 253 cap-sdio-irq; 254 #address-cells = <1>; 255 #size-cells = <0>; 256 }; 257 258 mmc1: mmc@4021000 { 259 compatible = "allwinner,sun50i-h616-mmc", 260 "allwinner,sun50i-a100-mmc"; 261 reg = <0x04021000 0x1000>; 262 clocks = <&ccu CLK_BUS_MMC1>, <&ccu CLK_MMC1>; 263 clock-names = "ahb", "mmc"; 264 resets = <&ccu RST_BUS_MMC1>; 265 reset-names = "ahb"; 266 interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>; 267 pinctrl-names = "default"; 268 pinctrl-0 = <&mmc1_pins>; 269 status = "disabled"; 270 cap-sd-highspeed; 271 cap-mmc-highspeed; 272 mmc-ddr-3_3v; 273 mmc-ddr-1_8v; 274 cap-sdio-irq; 275 #address-cells = <1>; 276 #size-cells = <0>; 277 }; 278 279 mmc2: mmc@4022000 { 280 compatible = "allwinner,sun50i-h616-emmc", 281 "allwinner,sun50i-a100-emmc"; 282 reg = <0x04022000 0x1000>; 283 clocks = <&ccu CLK_BUS_MMC2>, <&ccu CLK_MMC2>; 284 clock-names = "ahb", "mmc"; 285 resets = <&ccu RST_BUS_MMC2>; 286 reset-names = "ahb"; 287 interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>; 288 pinctrl-names = "default"; 289 pinctrl-0 = <&mmc2_pins>; 290 status = "disabled"; 291 cap-sd-highspeed; 292 cap-mmc-highspeed; 293 mmc-ddr-3_3v; 294 mmc-ddr-1_8v; 295 cap-sdio-irq; 296 #address-cells = <1>; 297 #size-cells = <0>; 298 }; 299 300 uart0: serial@5000000 { 301 compatible = "snps,dw-apb-uart"; 302 reg = <0x05000000 0x400>; 303 interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>; 304 reg-shift = <2>; 305 reg-io-width = <4>; 306 clocks = <&ccu CLK_BUS_UART0>; 307 resets = <&ccu RST_BUS_UART0>; 308 status = "disabled"; 309 }; 310 311 uart1: serial@5000400 { 312 compatible = "snps,dw-apb-uart"; 313 reg = <0x05000400 0x400>; 314 interrupts = <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>; 315 reg-shift = <2>; 316 reg-io-width = <4>; 317 clocks = <&ccu CLK_BUS_UART1>; 318 resets = <&ccu RST_BUS_UART1>; 319 status = "disabled"; 320 }; 321 322 uart2: serial@5000800 { 323 compatible = "snps,dw-apb-uart"; 324 reg = <0x05000800 0x400>; 325 interrupts = <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>; 326 reg-shift = <2>; 327 reg-io-width = <4>; 328 clocks = <&ccu CLK_BUS_UART2>; 329 resets = <&ccu RST_BUS_UART2>; 330 status = "disabled"; 331 }; 332 333 uart3: serial@5000c00 { 334 compatible = "snps,dw-apb-uart"; 335 reg = <0x05000c00 0x400>; 336 interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>; 337 reg-shift = <2>; 338 reg-io-width = <4>; 339 clocks = <&ccu CLK_BUS_UART3>; 340 resets = <&ccu RST_BUS_UART3>; 341 status = "disabled"; 342 }; 343 344 uart4: serial@5001000 { 345 compatible = "snps,dw-apb-uart"; 346 reg = <0x05001000 0x400>; 347 interrupts = <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>; 348 reg-shift = <2>; 349 reg-io-width = <4>; 350 clocks = <&ccu CLK_BUS_UART4>; 351 resets = <&ccu RST_BUS_UART4>; 352 status = "disabled"; 353 }; 354 355 uart5: serial@5001400 { 356 compatible = "snps,dw-apb-uart"; 357 reg = <0x05001400 0x400>; 358 interrupts = <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>; 359 reg-shift = <2>; 360 reg-io-width = <4>; 361 clocks = <&ccu CLK_BUS_UART5>; 362 resets = <&ccu RST_BUS_UART5>; 363 status = "disabled"; 364 }; 365 366 i2c0: i2c@5002000 { 367 compatible = "allwinner,sun50i-h616-i2c", 368 "allwinner,sun6i-a31-i2c"; 369 reg = <0x05002000 0x400>; 370 interrupts = <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>; 371 clocks = <&ccu CLK_BUS_I2C0>; 372 resets = <&ccu RST_BUS_I2C0>; 373 pinctrl-names = "default"; 374 pinctrl-0 = <&i2c0_pins>; 375 status = "disabled"; 376 #address-cells = <1>; 377 #size-cells = <0>; 378 }; 379 380 i2c1: i2c@5002400 { 381 compatible = "allwinner,sun50i-h616-i2c", 382 "allwinner,sun6i-a31-i2c"; 383 reg = <0x05002400 0x400>; 384 interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>; 385 clocks = <&ccu CLK_BUS_I2C1>; 386 resets = <&ccu RST_BUS_I2C1>; 387 status = "disabled"; 388 #address-cells = <1>; 389 #size-cells = <0>; 390 }; 391 392 i2c2: i2c@5002800 { 393 compatible = "allwinner,sun50i-h616-i2c", 394 "allwinner,sun6i-a31-i2c"; 395 reg = <0x05002800 0x400>; 396 interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>; 397 clocks = <&ccu CLK_BUS_I2C2>; 398 resets = <&ccu RST_BUS_I2C2>; 399 status = "disabled"; 400 #address-cells = <1>; 401 #size-cells = <0>; 402 }; 403 404 i2c3: i2c@5002c00 { 405 compatible = "allwinner,sun50i-h616-i2c", 406 "allwinner,sun6i-a31-i2c"; 407 reg = <0x05002c00 0x400>; 408 interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>; 409 clocks = <&ccu CLK_BUS_I2C3>; 410 resets = <&ccu RST_BUS_I2C3>; 411 status = "disabled"; 412 #address-cells = <1>; 413 #size-cells = <0>; 414 }; 415 416 i2c4: i2c@5003000 { 417 compatible = "allwinner,sun50i-h616-i2c", 418 "allwinner,sun6i-a31-i2c"; 419 reg = <0x05003000 0x400>; 420 interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>; 421 clocks = <&ccu CLK_BUS_I2C4>; 422 resets = <&ccu RST_BUS_I2C4>; 423 status = "disabled"; 424 #address-cells = <1>; 425 #size-cells = <0>; 426 }; 427 428 spi0: spi@5010000 { 429 compatible = "allwinner,sun50i-h616-spi", 430 "allwinner,sun8i-h3-spi"; 431 reg = <0x05010000 0x1000>; 432 interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>; 433 clocks = <&ccu CLK_BUS_SPI0>, <&ccu CLK_SPI0>; 434 clock-names = "ahb", "mod"; 435 resets = <&ccu RST_BUS_SPI0>; 436 pinctrl-names = "default"; 437 pinctrl-0 = <&spi0_pins>; 438 status = "disabled"; 439 #address-cells = <1>; 440 #size-cells = <0>; 441 }; 442 443 spi1: spi@5011000 { 444 compatible = "allwinner,sun50i-h616-spi", 445 "allwinner,sun8i-h3-spi"; 446 reg = <0x05011000 0x1000>; 447 interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>; 448 clocks = <&ccu CLK_BUS_SPI1>, <&ccu CLK_SPI1>; 449 clock-names = "ahb", "mod"; 450 resets = <&ccu RST_BUS_SPI1>; 451 pinctrl-names = "default"; 452 pinctrl-0 = <&spi1_pins>; 453 status = "disabled"; 454 #address-cells = <1>; 455 #size-cells = <0>; 456 }; 457 458 emac0: ethernet@5020000 { 459 compatible = "allwinner,sun50i-h616-emac", 460 "allwinner,sun50i-a64-emac"; 461 syscon = <&syscon>; 462 reg = <0x05020000 0x10000>; 463 interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>; 464 interrupt-names = "macirq"; 465 resets = <&ccu RST_BUS_EMAC0>; 466 reset-names = "stmmaceth"; 467 clocks = <&ccu CLK_BUS_EMAC0>; 468 clock-names = "stmmaceth"; 469 status = "disabled"; 470 471 mdio0: mdio { 472 compatible = "snps,dwmac-mdio"; 473 #address-cells = <1>; 474 #size-cells = <0>; 475 }; 476 }; 477 478 emac1: ethernet@5030000 { 479 compatible = "allwinner,sun50i-h616-emac"; 480 syscon = <&syscon 1>; 481 reg = <0x05030000 0x10000>; 482 interrupts = <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>; 483 interrupt-names = "macirq"; 484 resets = <&ccu RST_BUS_EMAC1>; 485 reset-names = "stmmaceth"; 486 clocks = <&ccu CLK_BUS_EMAC1>; 487 clock-names = "stmmaceth"; 488 status = "disabled"; 489 490 mdio1: mdio { 491 compatible = "snps,dwmac-mdio"; 492 #address-cells = <1>; 493 #size-cells = <0>; 494 }; 495 }; 496 497 usbotg: usb@5100000 { 498 compatible = "allwinner,sun50i-h616-musb", 499 "allwinner,sun8i-h3-musb"; 500 reg = <0x05100000 0x0400>; 501 clocks = <&ccu CLK_BUS_OTG>; 502 resets = <&ccu RST_BUS_OTG>; 503 interrupts = <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>; 504 interrupt-names = "mc"; 505 phys = <&usbphy 0>; 506 phy-names = "usb"; 507 extcon = <&usbphy 0>; 508 status = "disabled"; 509 }; 510 511 usbphy: phy@5100400 { 512 compatible = "allwinner,sun50i-h616-usb-phy"; 513 reg = <0x05100400 0x24>, 514 <0x05101800 0x14>, 515 <0x05200800 0x14>, 516 <0x05310800 0x14>, 517 <0x05311800 0x14>; 518 reg-names = "phy_ctrl", 519 "pmu0", 520 "pmu1", 521 "pmu2", 522 "pmu3"; 523 clocks = <&ccu CLK_USB_PHY0>, 524 <&ccu CLK_USB_PHY1>, 525 <&ccu CLK_USB_PHY2>, 526 <&ccu CLK_USB_PHY3>; 527 clock-names = "usb0_phy", 528 "usb1_phy", 529 "usb2_phy", 530 "usb3_phy"; 531 resets = <&ccu RST_USB_PHY0>, 532 <&ccu RST_USB_PHY1>, 533 <&ccu RST_USB_PHY2>, 534 <&ccu RST_USB_PHY3>; 535 reset-names = "usb0_reset", 536 "usb1_reset", 537 "usb2_reset", 538 "usb3_reset"; 539 status = "disabled"; 540 #phy-cells = <1>; 541 }; 542 543 ehci0: usb@5101000 { 544 compatible = "allwinner,sun50i-h616-ehci", 545 "generic-ehci"; 546 reg = <0x05101000 0x100>; 547 interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>; 548 clocks = <&ccu CLK_BUS_OHCI0>, 549 <&ccu CLK_BUS_EHCI0>, 550 <&ccu CLK_USB_OHCI0>; 551 resets = <&ccu RST_BUS_OHCI0>, 552 <&ccu RST_BUS_EHCI0>; 553 phys = <&usbphy 0>; 554 phy-names = "usb"; 555 status = "disabled"; 556 }; 557 558 ohci0: usb@5101400 { 559 compatible = "allwinner,sun50i-h616-ohci", 560 "generic-ohci"; 561 reg = <0x05101400 0x100>; 562 interrupts = <GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH>; 563 clocks = <&ccu CLK_BUS_OHCI0>, 564 <&ccu CLK_USB_OHCI0>; 565 resets = <&ccu RST_BUS_OHCI0>; 566 phys = <&usbphy 0>; 567 phy-names = "usb"; 568 status = "disabled"; 569 }; 570 571 ehci1: usb@5200000 { 572 compatible = "allwinner,sun50i-h616-ehci", 573 "generic-ehci"; 574 reg = <0x05200000 0x100>; 575 interrupts = <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>; 576 clocks = <&ccu CLK_BUS_OHCI1>, 577 <&ccu CLK_BUS_EHCI1>, 578 <&ccu CLK_USB_OHCI1>; 579 resets = <&ccu RST_BUS_OHCI1>, 580 <&ccu RST_BUS_EHCI1>; 581 phys = <&usbphy 1>; 582 phy-names = "usb"; 583 status = "disabled"; 584 }; 585 586 ohci1: usb@5200400 { 587 compatible = "allwinner,sun50i-h616-ohci", 588 "generic-ohci"; 589 reg = <0x05200400 0x100>; 590 interrupts = <GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>; 591 clocks = <&ccu CLK_BUS_OHCI1>, 592 <&ccu CLK_USB_OHCI1>; 593 resets = <&ccu RST_BUS_OHCI1>; 594 phys = <&usbphy 1>; 595 phy-names = "usb"; 596 status = "disabled"; 597 }; 598 599 ehci2: usb@5310000 { 600 compatible = "allwinner,sun50i-h616-ehci", 601 "generic-ehci"; 602 reg = <0x05310000 0x100>; 603 interrupts = <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>; 604 clocks = <&ccu CLK_BUS_OHCI2>, 605 <&ccu CLK_BUS_EHCI2>, 606 <&ccu CLK_USB_OHCI2>; 607 resets = <&ccu RST_BUS_OHCI2>, 608 <&ccu RST_BUS_EHCI2>; 609 phys = <&usbphy 2>; 610 phy-names = "usb"; 611 status = "disabled"; 612 }; 613 614 ohci2: usb@5310400 { 615 compatible = "allwinner,sun50i-h616-ohci", 616 "generic-ohci"; 617 reg = <0x05310400 0x100>; 618 interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>; 619 clocks = <&ccu CLK_BUS_OHCI2>, 620 <&ccu CLK_USB_OHCI2>; 621 resets = <&ccu RST_BUS_OHCI2>; 622 phys = <&usbphy 2>; 623 phy-names = "usb"; 624 status = "disabled"; 625 }; 626 627 ehci3: usb@5311000 { 628 compatible = "allwinner,sun50i-h616-ehci", 629 "generic-ehci"; 630 reg = <0x05311000 0x100>; 631 interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>; 632 clocks = <&ccu CLK_BUS_OHCI3>, 633 <&ccu CLK_BUS_EHCI3>, 634 <&ccu CLK_USB_OHCI3>; 635 resets = <&ccu RST_BUS_OHCI3>, 636 <&ccu RST_BUS_EHCI3>; 637 phys = <&usbphy 3>; 638 phy-names = "usb"; 639 status = "disabled"; 640 }; 641 642 ohci3: usb@5311400 { 643 compatible = "allwinner,sun50i-h616-ohci", 644 "generic-ohci"; 645 reg = <0x05311400 0x100>; 646 interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>; 647 clocks = <&ccu CLK_BUS_OHCI3>, 648 <&ccu CLK_USB_OHCI3>; 649 resets = <&ccu RST_BUS_OHCI3>; 650 phys = <&usbphy 3>; 651 phy-names = "usb"; 652 status = "disabled"; 653 }; 654 655 rtc: rtc@7000000 { 656 compatible = "allwinner,sun50i-h616-rtc", 657 "allwinner,sun50i-h6-rtc"; 658 reg = <0x07000000 0x400>; 659 interrupts = <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>, 660 <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>; 661 clock-output-names = "osc32k", "osc32k-out", "iosc"; 662 #clock-cells = <1>; 663 }; 664 665 r_ccu: clock@7010000 { 666 compatible = "allwinner,sun50i-h616-r-ccu"; 667 reg = <0x07010000 0x400>; 668 clocks = <&osc24M>, <&rtc 0>, <&rtc 2>, 669 <&ccu CLK_PLL_PERIPH0>; 670 clock-names = "hosc", "losc", "iosc", "pll-periph"; 671 #clock-cells = <1>; 672 #reset-cells = <1>; 673 }; 674 675 r_pio: pinctrl@7022000 { 676 compatible = "allwinner,sun50i-h616-r-pinctrl"; 677 reg = <0x07022000 0x400>; 678 interrupts = <GIC_SPI 43 IRQ_TYPE_LEVEL_HIGH>; 679 clocks = <&r_ccu CLK_R_APB1>, <&osc24M>, <&rtc 0>; 680 clock-names = "apb", "hosc", "losc"; 681 gpio-controller; 682 #gpio-cells = <3>; 683 interrupt-controller; 684 #interrupt-cells = <3>; 685 686 r_i2c_pins: r-i2c-pins { 687 pins = "PL0", "PL1"; 688 function = "s_i2c"; 689 }; 690 691 r_rsb_pins: r-rsb-pins { 692 pins = "PL0", "PL1"; 693 function = "s_rsb"; 694 }; 695 }; 696 697 ir: ir@7040000 { 698 compatible = "allwinner,sun50i-h616-ir", 699 "allwinner,sun6i-a31-ir"; 700 reg = <0x07040000 0x400>; 701 interrupts = <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>; 702 clocks = <&r_ccu CLK_R_APB1_IR>, 703 <&r_ccu CLK_IR>; 704 clock-names = "apb", "ir"; 705 resets = <&r_ccu RST_R_APB1_IR>; 706 pinctrl-names = "default"; 707 pinctrl-0 = <&ir_rx_pin>; 708 status = "disabled"; 709 }; 710 711 r_i2c: i2c@7081400 { 712 compatible = "allwinner,sun50i-h616-i2c", 713 "allwinner,sun6i-a31-i2c"; 714 reg = <0x07081400 0x400>; 715 interrupts = <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>; 716 clocks = <&r_ccu CLK_R_APB2_I2C>; 717 resets = <&r_ccu RST_R_APB2_I2C>; 718 status = "disabled"; 719 #address-cells = <1>; 720 #size-cells = <0>; 721 }; 722 723 r_rsb: rsb@7083000 { 724 compatible = "allwinner,sun50i-h616-rsb", 725 "allwinner,sun8i-a23-rsb"; 726 reg = <0x07083000 0x400>; 727 interrupts = <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>; 728 clocks = <&r_ccu CLK_R_APB2_RSB>; 729 clock-frequency = <3000000>; 730 resets = <&r_ccu RST_R_APB2_RSB>; 731 pinctrl-names = "default"; 732 pinctrl-0 = <&r_rsb_pins>; 733 status = "disabled"; 734 #address-cells = <1>; 735 #size-cells = <0>; 736 }; 737 }; 738}; 739