1/* 2 * Copyright 2016-2019 Toradex AG 3 * 4 * This file is dual-licensed: you can use it either under the terms 5 * of the GPL or the X11 license, at your option. Note that this dual 6 * licensing only applies to this file, and not this project as a 7 * whole. 8 * 9 * a) This file is free software; you can redistribute it and/or 10 * modify it under the terms of the GNU General Public License 11 * version 2 as published by the Free Software Foundation. 12 * 13 * This file is distributed in the hope that it will be useful 14 * but WITHOUT ANY WARRANTY; without even the implied warranty of 15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 16 * GNU General Public License for more details. 17 * 18 * Or, alternatively 19 * 20 * b) Permission is hereby granted, free of charge, to any person 21 * obtaining a copy of this software and associated documentation 22 * files (the "Software"), to deal in the Software without 23 * restriction, including without limitation the rights to use 24 * copy, modify, merge, publish, distribute, sublicense, and/or 25 * sell copies of the Software, and to permit persons to whom the 26 * Software is furnished to do so, subject to the following 27 * conditions: 28 * 29 * The above copyright notice and this permission notice shall be 30 * included in all copies or substantial portions of the Software. 31 * 32 * THE SOFTWARE IS PROVIDED , WITHOUT WARRANTY OF ANY KIND 33 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES 34 * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND 35 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT 36 * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY 37 * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING 38 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 39 * OTHER DEALINGS IN THE SOFTWARE. 40 */ 41 42/dts-v1/; 43 44#include <dt-bindings/input/input.h> 45#include "tegra124.dtsi" 46 47/ { 48 model = "Toradex Apalis TK1 on Apalis Evaluation Board"; 49 compatible = "toradex,apalis-tk1-eval", "toradex,apalis-tk1", 50 "nvidia,tegra124"; 51 52 aliases { 53 i2c0 = "/i2c@7000d000"; 54 i2c1 = "/i2c@7000c000"; 55 i2c2 = "/i2c@7000c400"; 56 i2c3 = "/i2c@7000c500"; 57 mmc0 = "/sdhci@700b0600"; 58 mmc1 = "/sdhci@700b0000"; 59 mmc2 = "/sdhci@700b0400"; 60 rtc0 = "/i2c@7000c000/rtc@68"; 61 rtc1 = "/i2c@7000d000/pmic@40"; 62 rtc2 = "/rtc@7000e000"; 63 serial0 = &uarta; 64 serial1 = &uartb; 65 serial2 = &uartc; 66 serial3 = &uartd; 67 usb0 = "/usb@7d000000"; 68 usb1 = "/usb@7d004000"; 69 usb2 = "/usb@7d008000"; 70 }; 71 72 chosen { 73 stdout-path = "serial0:115200n8"; 74 }; 75 76 memory { 77 reg = <0x0 0x80000000 0x0 0x80000000>; 78 }; 79 80 pcie@1003000 { 81 status = "okay"; 82 avddio-pex-supply = <&vdd_1v05>; 83 avdd-pex-pll-supply = <&vdd_1v05>; 84 avdd-pll-erefe-supply = <&avdd_1v05>; 85 dvddio-pex-supply = <&vdd_1v05>; 86 hvdd-pex-pll-e-supply = <®_3v3>; 87 hvdd-pex-supply = <®_3v3>; 88 vddio-pex-ctl-supply = <®_3v3>; 89 90 /* Apalis PCIe (additional lane Apalis type specific) */ 91 pci@1,0 { 92 /* PCIE1_RX/TX and TS_DIFF1/2 left disabled */ 93 }; 94 95 /* I210 Gigabit Ethernet Controller (On-module) */ 96 pci@2,0 { 97 status = "okay"; 98 }; 99 }; 100 101 host1x@50000000 { 102 hdmi@54280000 { 103 pll-supply = <®_1v05_avdd_hdmi_pll>; 104 vdd-supply = <®_3v3_avdd_hdmi>; 105 nvidia,ddc-i2c-bus = <&hdmi_ddc>; 106 nvidia,hpd-gpio = 107 <&gpio TEGRA_GPIO(N, 7) GPIO_ACTIVE_HIGH>; 108 status = "okay"; 109 }; 110 }; 111 112 gpu@0,57000000 { 113 /* 114 * Node left disabled on purpose - the bootloader will enable 115 * it after having set the VPR up 116 */ 117 vdd-supply = <&vdd_gpu>; 118 }; 119 120 pinmux: pinmux@70000868 { 121 pinctrl-names = "default"; 122 pinctrl-0 = <&state_default>; 123 124 state_default: pinmux { 125 /* Analogue Audio (On-module) */ 126 dap3_fs_pp0 { 127 nvidia,pins = "dap3_fs_pp0"; 128 nvidia,function = "i2s2"; 129 nvidia,pull = <TEGRA_PIN_PULL_NONE>; 130 nvidia,tristate = <TEGRA_PIN_DISABLE>; 131 nvidia,enable-input = <TEGRA_PIN_DISABLE>; 132 }; 133 dap3_din_pp1 { 134 nvidia,pins = "dap3_din_pp1"; 135 nvidia,function = "i2s2"; 136 nvidia,pull = <TEGRA_PIN_PULL_NONE>; 137 nvidia,tristate = <TEGRA_PIN_ENABLE>; 138 nvidia,enable-input = <TEGRA_PIN_ENABLE>; 139 }; 140 dap3_dout_pp2 { 141 nvidia,pins = "dap3_dout_pp2"; 142 nvidia,function = "i2s2"; 143 nvidia,pull = <TEGRA_PIN_PULL_NONE>; 144 nvidia,tristate = <TEGRA_PIN_DISABLE>; 145 nvidia,enable-input = <TEGRA_PIN_DISABLE>; 146 }; 147 dap3_sclk_pp3 { 148 nvidia,pins = "dap3_sclk_pp3"; 149 nvidia,function = "i2s2"; 150 nvidia,pull = <TEGRA_PIN_PULL_NONE>; 151 nvidia,tristate = <TEGRA_PIN_DISABLE>; 152 nvidia,enable-input = <TEGRA_PIN_DISABLE>; 153 }; 154 dap_mclk1_pw4 { 155 nvidia,pins = "dap_mclk1_pw4"; 156 nvidia,function = "extperiph1"; 157 nvidia,pull = <TEGRA_PIN_PULL_NONE>; 158 nvidia,tristate = <TEGRA_PIN_DISABLE>; 159 nvidia,enable-input = <TEGRA_PIN_DISABLE>; 160 }; 161 162 /* Apalis BKL1_ON */ 163 pbb5 { 164 nvidia,pins = "pbb5"; 165 nvidia,function = "vgp5"; 166 nvidia,pull = <TEGRA_PIN_PULL_NONE>; 167 nvidia,tristate = <TEGRA_PIN_DISABLE>; 168 nvidia,enable-input = <TEGRA_PIN_DISABLE>; 169 }; 170 171 /* Apalis BKL1_PWM */ 172 pu6 { 173 nvidia,pins = "pu6"; 174 nvidia,function = "pwm3"; 175 nvidia,pull = <TEGRA_PIN_PULL_NONE>; 176 nvidia,tristate = <TEGRA_PIN_DISABLE>; 177 nvidia,enable-input = <TEGRA_PIN_DISABLE>; 178 }; 179 180 /* Apalis CAM1_MCLK */ 181 cam_mclk_pcc0 { 182 nvidia,pins = "cam_mclk_pcc0"; 183 nvidia,function = "vi_alt3"; 184 nvidia,pull = <TEGRA_PIN_PULL_NONE>; 185 nvidia,tristate = <TEGRA_PIN_DISABLE>; 186 nvidia,enable-input = <TEGRA_PIN_DISABLE>; 187 }; 188 189 /* Apalis Digital Audio */ 190 dap2_fs_pa2 { 191 nvidia,pins = "dap2_fs_pa2"; 192 nvidia,function = "hda"; 193 nvidia,pull = <TEGRA_PIN_PULL_NONE>; 194 nvidia,tristate = <TEGRA_PIN_DISABLE>; 195 nvidia,enable-input = <TEGRA_PIN_ENABLE>; 196 }; 197 dap2_sclk_pa3 { 198 nvidia,pins = "dap2_sclk_pa3"; 199 nvidia,function = "hda"; 200 nvidia,pull = <TEGRA_PIN_PULL_NONE>; 201 nvidia,tristate = <TEGRA_PIN_DISABLE>; 202 nvidia,enable-input = <TEGRA_PIN_ENABLE>; 203 }; 204 dap2_din_pa4 { 205 nvidia,pins = "dap2_din_pa4"; 206 nvidia,function = "hda"; 207 nvidia,pull = <TEGRA_PIN_PULL_NONE>; 208 nvidia,tristate = <TEGRA_PIN_ENABLE>; 209 nvidia,enable-input = <TEGRA_PIN_ENABLE>; 210 }; 211 dap2_dout_pa5 { 212 nvidia,pins = "dap2_dout_pa5"; 213 nvidia,function = "hda"; 214 nvidia,pull = <TEGRA_PIN_PULL_NONE>; 215 nvidia,tristate = <TEGRA_PIN_DISABLE>; 216 nvidia,enable-input = <TEGRA_PIN_DISABLE>; 217 }; 218 pbb3 { /* DAP1_RESET */ 219 nvidia,pins = "pbb3"; 220 nvidia,pull = <TEGRA_PIN_PULL_NONE>; 221 nvidia,tristate = <TEGRA_PIN_DISABLE>; 222 nvidia,enable-input = <TEGRA_PIN_DISABLE>; 223 }; 224 clk3_out_pee0 { 225 nvidia,pins = "clk3_out_pee0"; 226 nvidia,function = "extperiph3"; 227 nvidia,pull = <TEGRA_PIN_PULL_NONE>; 228 nvidia,tristate = <TEGRA_PIN_DISABLE>; 229 nvidia,enable-input = <TEGRA_PIN_DISABLE>; 230 }; 231 232 /* Apalis GPIO */ 233 usb_vbus_en0_pn4 { 234 nvidia,pins = "usb_vbus_en0_pn4"; 235 nvidia,function = "rsvd2"; 236 nvidia,pull = <TEGRA_PIN_PULL_NONE>; 237 nvidia,tristate = <TEGRA_PIN_DISABLE>; 238 nvidia,enable-input = <TEGRA_PIN_ENABLE>; 239 nvidia,open-drain = <TEGRA_PIN_DISABLE>; 240 }; 241 usb_vbus_en1_pn5 { 242 nvidia,pins = "usb_vbus_en1_pn5"; 243 nvidia,function = "rsvd2"; 244 nvidia,pull = <TEGRA_PIN_PULL_NONE>; 245 nvidia,tristate = <TEGRA_PIN_DISABLE>; 246 nvidia,enable-input = <TEGRA_PIN_ENABLE>; 247 nvidia,open-drain = <TEGRA_PIN_DISABLE>; 248 }; 249 pex_l0_rst_n_pdd1 { 250 nvidia,pins = "pex_l0_rst_n_pdd1"; 251 nvidia,function = "rsvd2"; 252 nvidia,pull = <TEGRA_PIN_PULL_NONE>; 253 nvidia,tristate = <TEGRA_PIN_DISABLE>; 254 nvidia,enable-input = <TEGRA_PIN_ENABLE>; 255 }; 256 pex_l0_clkreq_n_pdd2 { 257 nvidia,pins = "pex_l0_clkreq_n_pdd2"; 258 nvidia,function = "rsvd2"; 259 nvidia,pull = <TEGRA_PIN_PULL_NONE>; 260 nvidia,tristate = <TEGRA_PIN_DISABLE>; 261 nvidia,enable-input = <TEGRA_PIN_ENABLE>; 262 }; 263 pex_l1_rst_n_pdd5 { 264 nvidia,pins = "pex_l1_rst_n_pdd5"; 265 nvidia,function = "rsvd2"; 266 nvidia,pull = <TEGRA_PIN_PULL_NONE>; 267 nvidia,tristate = <TEGRA_PIN_DISABLE>; 268 nvidia,enable-input = <TEGRA_PIN_ENABLE>; 269 }; 270 pex_l1_clkreq_n_pdd6 { 271 nvidia,pins = "pex_l1_clkreq_n_pdd6"; 272 nvidia,function = "rsvd2"; 273 nvidia,pull = <TEGRA_PIN_PULL_NONE>; 274 nvidia,tristate = <TEGRA_PIN_DISABLE>; 275 nvidia,enable-input = <TEGRA_PIN_ENABLE>; 276 }; 277 dp_hpd_pff0 { 278 nvidia,pins = "dp_hpd_pff0"; 279 nvidia,function = "dp"; 280 nvidia,pull = <TEGRA_PIN_PULL_NONE>; 281 nvidia,tristate = <TEGRA_PIN_DISABLE>; 282 nvidia,enable-input = <TEGRA_PIN_ENABLE>; 283 }; 284 pff2 { 285 nvidia,pins = "pff2"; 286 nvidia,function = "rsvd2"; 287 nvidia,pull = <TEGRA_PIN_PULL_NONE>; 288 nvidia,tristate = <TEGRA_PIN_DISABLE>; 289 nvidia,enable-input = <TEGRA_PIN_ENABLE>; 290 }; 291 owr { /* PEX_L1_CLKREQ_N multiplexed GPIO6 */ 292 nvidia,pins = "owr"; 293 nvidia,function = "rsvd2"; 294 nvidia,pull = <TEGRA_PIN_PULL_NONE>; 295 nvidia,tristate = <TEGRA_PIN_ENABLE>; 296 nvidia,enable-input = <TEGRA_PIN_DISABLE>; 297 nvidia,rcv-sel = <TEGRA_PIN_DISABLE>; 298 }; 299 300 /* Apalis HDMI1_CEC */ 301 hdmi_cec_pee3 { 302 nvidia,pins = "hdmi_cec_pee3"; 303 nvidia,function = "cec"; 304 nvidia,pull = <TEGRA_PIN_PULL_NONE>; 305 nvidia,tristate = <TEGRA_PIN_DISABLE>; 306 nvidia,enable-input = <TEGRA_PIN_ENABLE>; 307 nvidia,open-drain = <TEGRA_PIN_DISABLE>; 308 }; 309 310 /* Apalis HDMI1_HPD */ 311 hdmi_int_pn7 { 312 nvidia,pins = "hdmi_int_pn7"; 313 nvidia,function = "rsvd1"; 314 nvidia,pull = <TEGRA_PIN_PULL_DOWN>; 315 nvidia,tristate = <TEGRA_PIN_ENABLE>; 316 nvidia,enable-input = <TEGRA_PIN_ENABLE>; 317 nvidia,rcv-sel = <TEGRA_PIN_DISABLE>; 318 }; 319 320 /* Apalis I2C1 */ 321 gen1_i2c_scl_pc4 { 322 nvidia,pins = "gen1_i2c_scl_pc4"; 323 nvidia,function = "i2c1"; 324 nvidia,pull = <TEGRA_PIN_PULL_NONE>; 325 nvidia,tristate = <TEGRA_PIN_DISABLE>; 326 nvidia,enable-input = <TEGRA_PIN_ENABLE>; 327 nvidia,open-drain = <TEGRA_PIN_ENABLE>; 328 }; 329 gen1_i2c_sda_pc5 { 330 nvidia,pins = "gen1_i2c_sda_pc5"; 331 nvidia,function = "i2c1"; 332 nvidia,pull = <TEGRA_PIN_PULL_NONE>; 333 nvidia,tristate = <TEGRA_PIN_DISABLE>; 334 nvidia,enable-input = <TEGRA_PIN_ENABLE>; 335 nvidia,open-drain = <TEGRA_PIN_ENABLE>; 336 }; 337 338 /* Apalis I2C3 (CAM) */ 339 cam_i2c_scl_pbb1 { 340 nvidia,pins = "cam_i2c_scl_pbb1"; 341 nvidia,function = "i2c3"; 342 nvidia,pull = <TEGRA_PIN_PULL_NONE>; 343 nvidia,tristate = <TEGRA_PIN_DISABLE>; 344 nvidia,enable-input = <TEGRA_PIN_ENABLE>; 345 nvidia,open-drain = <TEGRA_PIN_ENABLE>; 346 }; 347 cam_i2c_sda_pbb2 { 348 nvidia,pins = "cam_i2c_sda_pbb2"; 349 nvidia,function = "i2c3"; 350 nvidia,pull = <TEGRA_PIN_PULL_NONE>; 351 nvidia,tristate = <TEGRA_PIN_DISABLE>; 352 nvidia,enable-input = <TEGRA_PIN_ENABLE>; 353 nvidia,open-drain = <TEGRA_PIN_ENABLE>; 354 }; 355 356 /* Apalis I2C4 (DDC) */ 357 ddc_scl_pv4 { 358 nvidia,pins = "ddc_scl_pv4"; 359 nvidia,function = "i2c4"; 360 nvidia,pull = <TEGRA_PIN_PULL_NONE>; 361 nvidia,tristate = <TEGRA_PIN_DISABLE>; 362 nvidia,enable-input = <TEGRA_PIN_ENABLE>; 363 nvidia,rcv-sel = <TEGRA_PIN_DISABLE>; 364 }; 365 ddc_sda_pv5 { 366 nvidia,pins = "ddc_sda_pv5"; 367 nvidia,function = "i2c4"; 368 nvidia,pull = <TEGRA_PIN_PULL_NONE>; 369 nvidia,tristate = <TEGRA_PIN_DISABLE>; 370 nvidia,enable-input = <TEGRA_PIN_ENABLE>; 371 nvidia,rcv-sel = <TEGRA_PIN_DISABLE>; 372 }; 373 374 /* Apalis MMC1 */ 375 sdmmc1_cd_n_pv3 { /* CD# GPIO */ 376 nvidia,pins = "sdmmc1_wp_n_pv3"; 377 nvidia,function = "sdmmc1"; 378 nvidia,pull = <TEGRA_PIN_PULL_UP>; 379 nvidia,tristate = <TEGRA_PIN_ENABLE>; 380 nvidia,enable-input = <TEGRA_PIN_ENABLE>; 381 }; 382 clk2_out_pw5 { /* D5 GPIO */ 383 nvidia,pins = "clk2_out_pw5"; 384 nvidia,function = "rsvd2"; 385 nvidia,pull = <TEGRA_PIN_PULL_NONE>; 386 nvidia,tristate = <TEGRA_PIN_DISABLE>; 387 nvidia,enable-input = <TEGRA_PIN_ENABLE>; 388 }; 389 sdmmc1_dat3_py4 { 390 nvidia,pins = "sdmmc1_dat3_py4"; 391 nvidia,function = "sdmmc1"; 392 nvidia,pull = <TEGRA_PIN_PULL_UP>; 393 nvidia,tristate = <TEGRA_PIN_DISABLE>; 394 nvidia,enable-input = <TEGRA_PIN_ENABLE>; 395 }; 396 sdmmc1_dat2_py5 { 397 nvidia,pins = "sdmmc1_dat2_py5"; 398 nvidia,function = "sdmmc1"; 399 nvidia,pull = <TEGRA_PIN_PULL_UP>; 400 nvidia,tristate = <TEGRA_PIN_DISABLE>; 401 nvidia,enable-input = <TEGRA_PIN_ENABLE>; 402 }; 403 sdmmc1_dat1_py6 { 404 nvidia,pins = "sdmmc1_dat1_py6"; 405 nvidia,function = "sdmmc1"; 406 nvidia,pull = <TEGRA_PIN_PULL_UP>; 407 nvidia,tristate = <TEGRA_PIN_DISABLE>; 408 nvidia,enable-input = <TEGRA_PIN_ENABLE>; 409 }; 410 sdmmc1_dat0_py7 { 411 nvidia,pins = "sdmmc1_dat0_py7"; 412 nvidia,function = "sdmmc1"; 413 nvidia,pull = <TEGRA_PIN_PULL_UP>; 414 nvidia,tristate = <TEGRA_PIN_DISABLE>; 415 nvidia,enable-input = <TEGRA_PIN_ENABLE>; 416 }; 417 sdmmc1_clk_pz0 { 418 nvidia,pins = "sdmmc1_clk_pz0"; 419 nvidia,function = "sdmmc1"; 420 nvidia,pull = <TEGRA_PIN_PULL_NONE>; 421 nvidia,tristate = <TEGRA_PIN_DISABLE>; 422 nvidia,enable-input = <TEGRA_PIN_ENABLE>; 423 }; 424 sdmmc1_cmd_pz1 { 425 nvidia,pins = "sdmmc1_cmd_pz1"; 426 nvidia,function = "sdmmc1"; 427 nvidia,pull = <TEGRA_PIN_PULL_UP>; 428 nvidia,tristate = <TEGRA_PIN_DISABLE>; 429 nvidia,enable-input = <TEGRA_PIN_ENABLE>; 430 }; 431 clk2_req_pcc5 { /* D4 GPIO */ 432 nvidia,pins = "clk2_req_pcc5"; 433 nvidia,function = "rsvd2"; 434 nvidia,pull = <TEGRA_PIN_PULL_NONE>; 435 nvidia,tristate = <TEGRA_PIN_DISABLE>; 436 nvidia,enable-input = <TEGRA_PIN_ENABLE>; 437 }; 438 sdmmc3_clk_lb_in_pee5 { /* D6 GPIO */ 439 nvidia,pins = "sdmmc3_clk_lb_in_pee5"; 440 nvidia,function = "rsvd2"; 441 nvidia,pull = <TEGRA_PIN_PULL_NONE>; 442 nvidia,tristate = <TEGRA_PIN_DISABLE>; 443 nvidia,enable-input = <TEGRA_PIN_ENABLE>; 444 }; 445 usb_vbus_en2_pff1 { /* D7 GPIO */ 446 nvidia,pins = "usb_vbus_en2_pff1"; 447 nvidia,function = "rsvd2"; 448 nvidia,pull = <TEGRA_PIN_PULL_NONE>; 449 nvidia,tristate = <TEGRA_PIN_DISABLE>; 450 nvidia,enable-input = <TEGRA_PIN_ENABLE>; 451 }; 452 453 /* Apalis PWM */ 454 ph0 { 455 nvidia,pins = "ph0"; 456 nvidia,function = "pwm0"; 457 nvidia,pull = <TEGRA_PIN_PULL_NONE>; 458 nvidia,tristate = <TEGRA_PIN_DISABLE>; 459 nvidia,enable-input = <TEGRA_PIN_DISABLE>; 460 }; 461 ph1 { 462 nvidia,pins = "ph1"; 463 nvidia,function = "pwm1"; 464 nvidia,pull = <TEGRA_PIN_PULL_NONE>; 465 nvidia,tristate = <TEGRA_PIN_DISABLE>; 466 nvidia,enable-input = <TEGRA_PIN_DISABLE>; 467 }; 468 ph2 { 469 nvidia,pins = "ph2"; 470 nvidia,function = "pwm2"; 471 nvidia,pull = <TEGRA_PIN_PULL_NONE>; 472 nvidia,tristate = <TEGRA_PIN_DISABLE>; 473 nvidia,enable-input = <TEGRA_PIN_DISABLE>; 474 }; 475 /* PWM3 active on pu6 being Apalis BKL1_PWM as well */ 476 ph3 { 477 nvidia,pins = "ph3"; 478 nvidia,function = "pwm3"; 479 nvidia,pull = <TEGRA_PIN_PULL_NONE>; 480 nvidia,tristate = <TEGRA_PIN_DISABLE>; 481 nvidia,enable-input = <TEGRA_PIN_DISABLE>; 482 }; 483 484 /* Apalis SATA1_ACT# */ 485 dap1_dout_pn2 { 486 nvidia,pins = "dap1_dout_pn2"; 487 nvidia,function = "gmi"; 488 nvidia,pull = <TEGRA_PIN_PULL_NONE>; 489 nvidia,tristate = <TEGRA_PIN_DISABLE>; 490 nvidia,enable-input = <TEGRA_PIN_DISABLE>; 491 }; 492 493 /* Apalis SD1 */ 494 sdmmc3_clk_pa6 { 495 nvidia,pins = "sdmmc3_clk_pa6"; 496 nvidia,function = "sdmmc3"; 497 nvidia,pull = <TEGRA_PIN_PULL_NONE>; 498 nvidia,tristate = <TEGRA_PIN_DISABLE>; 499 nvidia,enable-input = <TEGRA_PIN_ENABLE>; 500 }; 501 sdmmc3_cmd_pa7 { 502 nvidia,pins = "sdmmc3_cmd_pa7"; 503 nvidia,function = "sdmmc3"; 504 nvidia,pull = <TEGRA_PIN_PULL_UP>; 505 nvidia,tristate = <TEGRA_PIN_DISABLE>; 506 nvidia,enable-input = <TEGRA_PIN_ENABLE>; 507 }; 508 sdmmc3_dat3_pb4 { 509 nvidia,pins = "sdmmc3_dat3_pb4"; 510 nvidia,function = "sdmmc3"; 511 nvidia,pull = <TEGRA_PIN_PULL_UP>; 512 nvidia,tristate = <TEGRA_PIN_DISABLE>; 513 nvidia,enable-input = <TEGRA_PIN_ENABLE>; 514 }; 515 sdmmc3_dat2_pb5 { 516 nvidia,pins = "sdmmc3_dat2_pb5"; 517 nvidia,function = "sdmmc3"; 518 nvidia,pull = <TEGRA_PIN_PULL_UP>; 519 nvidia,tristate = <TEGRA_PIN_DISABLE>; 520 nvidia,enable-input = <TEGRA_PIN_ENABLE>; 521 }; 522 sdmmc3_dat1_pb6 { 523 nvidia,pins = "sdmmc3_dat1_pb6"; 524 nvidia,function = "sdmmc3"; 525 nvidia,pull = <TEGRA_PIN_PULL_UP>; 526 nvidia,tristate = <TEGRA_PIN_DISABLE>; 527 nvidia,enable-input = <TEGRA_PIN_ENABLE>; 528 }; 529 sdmmc3_dat0_pb7 { 530 nvidia,pins = "sdmmc3_dat0_pb7"; 531 nvidia,function = "sdmmc3"; 532 nvidia,pull = <TEGRA_PIN_PULL_UP>; 533 nvidia,tristate = <TEGRA_PIN_DISABLE>; 534 nvidia,enable-input = <TEGRA_PIN_ENABLE>; 535 }; 536 sdmmc3_cd_n_pv2 { /* CD# GPIO */ 537 nvidia,pins = "sdmmc3_cd_n_pv2"; 538 nvidia,function = "rsvd3"; 539 nvidia,pull = <TEGRA_PIN_PULL_UP>; 540 nvidia,tristate = <TEGRA_PIN_ENABLE>; 541 nvidia,enable-input = <TEGRA_PIN_ENABLE>; 542 }; 543 544 /* Apalis SPDIF */ 545 spdif_out_pk5 { 546 nvidia,pins = "spdif_out_pk5"; 547 nvidia,function = "spdif"; 548 nvidia,pull = <TEGRA_PIN_PULL_NONE>; 549 nvidia,tristate = <TEGRA_PIN_DISABLE>; 550 nvidia,enable-input = <TEGRA_PIN_DISABLE>; 551 }; 552 spdif_in_pk6 { 553 nvidia,pins = "spdif_in_pk6"; 554 nvidia,function = "spdif"; 555 nvidia,pull = <TEGRA_PIN_PULL_NONE>; 556 nvidia,tristate = <TEGRA_PIN_ENABLE>; 557 nvidia,enable-input = <TEGRA_PIN_ENABLE>; 558 }; 559 560 /* Apalis SPI1 */ 561 ulpi_clk_py0 { 562 nvidia,pins = "ulpi_clk_py0"; 563 nvidia,function = "spi1"; 564 nvidia,pull = <TEGRA_PIN_PULL_NONE>; 565 nvidia,tristate = <TEGRA_PIN_DISABLE>; 566 nvidia,enable-input = <TEGRA_PIN_DISABLE>; 567 }; 568 ulpi_dir_py1 { 569 nvidia,pins = "ulpi_dir_py1"; 570 nvidia,function = "spi1"; 571 nvidia,pull = <TEGRA_PIN_PULL_NONE>; 572 nvidia,tristate = <TEGRA_PIN_ENABLE>; 573 nvidia,enable-input = <TEGRA_PIN_ENABLE>; 574 }; 575 ulpi_nxt_py2 { 576 nvidia,pins = "ulpi_nxt_py2"; 577 nvidia,function = "spi1"; 578 nvidia,pull = <TEGRA_PIN_PULL_NONE>; 579 nvidia,tristate = <TEGRA_PIN_DISABLE>; 580 nvidia,enable-input = <TEGRA_PIN_DISABLE>; 581 }; 582 ulpi_stp_py3 { 583 nvidia,pins = "ulpi_stp_py3"; 584 nvidia,function = "spi1"; 585 nvidia,pull = <TEGRA_PIN_PULL_NONE>; 586 nvidia,tristate = <TEGRA_PIN_DISABLE>; 587 nvidia,enable-input = <TEGRA_PIN_DISABLE>; 588 }; 589 590 /* Apalis SPI2 */ 591 pg5 { 592 nvidia,pins = "pg5"; 593 nvidia,function = "spi4"; 594 nvidia,pull = <TEGRA_PIN_PULL_NONE>; 595 nvidia,tristate = <TEGRA_PIN_DISABLE>; 596 nvidia,enable-input = <TEGRA_PIN_DISABLE>; 597 }; 598 pg6 { 599 nvidia,pins = "pg6"; 600 nvidia,function = "spi4"; 601 nvidia,pull = <TEGRA_PIN_PULL_NONE>; 602 nvidia,tristate = <TEGRA_PIN_DISABLE>; 603 nvidia,enable-input = <TEGRA_PIN_DISABLE>; 604 }; 605 pg7 { 606 nvidia,pins = "pg7"; 607 nvidia,function = "spi4"; 608 nvidia,pull = <TEGRA_PIN_PULL_NONE>; 609 nvidia,tristate = <TEGRA_PIN_ENABLE>; 610 nvidia,enable-input = <TEGRA_PIN_ENABLE>; 611 }; 612 pi3 { 613 nvidia,pins = "pi3"; 614 nvidia,function = "spi4"; 615 nvidia,pull = <TEGRA_PIN_PULL_NONE>; 616 nvidia,tristate = <TEGRA_PIN_DISABLE>; 617 nvidia,enable-input = <TEGRA_PIN_DISABLE>; 618 }; 619 620 /* Apalis UART1 */ 621 pb1 { /* DCD GPIO */ 622 nvidia,pins = "pb1"; 623 nvidia,function = "rsvd2"; 624 nvidia,pull = <TEGRA_PIN_PULL_NONE>; 625 nvidia,tristate = <TEGRA_PIN_ENABLE>; 626 nvidia,enable-input = <TEGRA_PIN_ENABLE>; 627 }; 628 pk7 { /* RI GPIO */ 629 nvidia,pins = "pk7"; 630 nvidia,function = "rsvd2"; 631 nvidia,pull = <TEGRA_PIN_PULL_NONE>; 632 nvidia,tristate = <TEGRA_PIN_ENABLE>; 633 nvidia,enable-input = <TEGRA_PIN_ENABLE>; 634 }; 635 uart1_txd_pu0 { 636 nvidia,pins = "pu0"; 637 nvidia,function = "uarta"; 638 nvidia,pull = <TEGRA_PIN_PULL_NONE>; 639 nvidia,tristate = <TEGRA_PIN_DISABLE>; 640 nvidia,enable-input = <TEGRA_PIN_DISABLE>; 641 }; 642 uart1_rxd_pu1 { 643 nvidia,pins = "pu1"; 644 nvidia,function = "uarta"; 645 nvidia,pull = <TEGRA_PIN_PULL_NONE>; 646 nvidia,tristate = <TEGRA_PIN_ENABLE>; 647 nvidia,enable-input = <TEGRA_PIN_ENABLE>; 648 }; 649 uart1_cts_n_pu2 { 650 nvidia,pins = "pu2"; 651 nvidia,function = "uarta"; 652 nvidia,pull = <TEGRA_PIN_PULL_NONE>; 653 nvidia,tristate = <TEGRA_PIN_ENABLE>; 654 nvidia,enable-input = <TEGRA_PIN_ENABLE>; 655 }; 656 uart1_rts_n_pu3 { 657 nvidia,pins = "pu3"; 658 nvidia,function = "uarta"; 659 nvidia,pull = <TEGRA_PIN_PULL_NONE>; 660 nvidia,tristate = <TEGRA_PIN_DISABLE>; 661 nvidia,enable-input = <TEGRA_PIN_DISABLE>; 662 }; 663 uart3_cts_n_pa1 { /* DSR GPIO */ 664 nvidia,pins = "uart3_cts_n_pa1"; 665 nvidia,function = "gmi"; 666 nvidia,pull = <TEGRA_PIN_PULL_NONE>; 667 nvidia,tristate = <TEGRA_PIN_ENABLE>; 668 nvidia,enable-input = <TEGRA_PIN_ENABLE>; 669 }; 670 uart3_rts_n_pc0 { /* DTR GPIO */ 671 nvidia,pins = "uart3_rts_n_pc0"; 672 nvidia,function = "gmi"; 673 nvidia,pull = <TEGRA_PIN_PULL_NONE>; 674 nvidia,tristate = <TEGRA_PIN_DISABLE>; 675 nvidia,enable-input = <TEGRA_PIN_DISABLE>; 676 }; 677 678 /* Apalis UART2 */ 679 uart2_txd_pc2 { 680 nvidia,pins = "uart2_txd_pc2"; 681 nvidia,function = "irda"; 682 nvidia,pull = <TEGRA_PIN_PULL_NONE>; 683 nvidia,tristate = <TEGRA_PIN_DISABLE>; 684 nvidia,enable-input = <TEGRA_PIN_DISABLE>; 685 }; 686 uart2_rxd_pc3 { 687 nvidia,pins = "uart2_rxd_pc3"; 688 nvidia,function = "irda"; 689 nvidia,pull = <TEGRA_PIN_PULL_NONE>; 690 nvidia,tristate = <TEGRA_PIN_ENABLE>; 691 nvidia,enable-input = <TEGRA_PIN_ENABLE>; 692 }; 693 uart2_cts_n_pj5 { 694 nvidia,pins = "uart2_cts_n_pj5"; 695 nvidia,function = "uartb"; 696 nvidia,pull = <TEGRA_PIN_PULL_NONE>; 697 nvidia,tristate = <TEGRA_PIN_ENABLE>; 698 nvidia,enable-input = <TEGRA_PIN_ENABLE>; 699 }; 700 uart2_rts_n_pj6 { 701 nvidia,pins = "uart2_rts_n_pj6"; 702 nvidia,function = "uartb"; 703 nvidia,pull = <TEGRA_PIN_PULL_NONE>; 704 nvidia,tristate = <TEGRA_PIN_DISABLE>; 705 nvidia,enable-input = <TEGRA_PIN_DISABLE>; 706 }; 707 708 /* Apalis UART3 */ 709 uart3_txd_pw6 { 710 nvidia,pins = "uart3_txd_pw6"; 711 nvidia,function = "uartc"; 712 nvidia,pull = <TEGRA_PIN_PULL_NONE>; 713 nvidia,tristate = <TEGRA_PIN_DISABLE>; 714 nvidia,enable-input = <TEGRA_PIN_DISABLE>; 715 }; 716 uart3_rxd_pw7 { 717 nvidia,pins = "uart3_rxd_pw7"; 718 nvidia,function = "uartc"; 719 nvidia,pull = <TEGRA_PIN_PULL_NONE>; 720 nvidia,tristate = <TEGRA_PIN_ENABLE>; 721 nvidia,enable-input = <TEGRA_PIN_ENABLE>; 722 }; 723 724 /* Apalis UART4 */ 725 uart4_rxd_pb0 { 726 nvidia,pins = "pb0"; 727 nvidia,function = "uartd"; 728 nvidia,pull = <TEGRA_PIN_PULL_NONE>; 729 nvidia,tristate = <TEGRA_PIN_ENABLE>; 730 nvidia,enable-input = <TEGRA_PIN_ENABLE>; 731 }; 732 uart4_txd_pj7 { 733 nvidia,pins = "pj7"; 734 nvidia,function = "uartd"; 735 nvidia,pull = <TEGRA_PIN_PULL_NONE>; 736 nvidia,tristate = <TEGRA_PIN_DISABLE>; 737 nvidia,enable-input = <TEGRA_PIN_DISABLE>; 738 }; 739 740 /* Apalis USBH_EN */ 741 gen2_i2c_sda_pt6 { 742 nvidia,pins = "gen2_i2c_sda_pt6"; 743 nvidia,function = "rsvd2"; 744 nvidia,pull = <TEGRA_PIN_PULL_NONE>; 745 nvidia,tristate = <TEGRA_PIN_DISABLE>; 746 nvidia,enable-input = <TEGRA_PIN_DISABLE>; 747 nvidia,open-drain = <TEGRA_PIN_DISABLE>; 748 }; 749 750 /* Apalis USBH_OC# */ 751 pbb0 { 752 nvidia,pins = "pbb0"; 753 nvidia,function = "vgp6"; 754 nvidia,pull = <TEGRA_PIN_PULL_NONE>; 755 nvidia,tristate = <TEGRA_PIN_ENABLE>; 756 nvidia,enable-input = <TEGRA_PIN_ENABLE>; 757 }; 758 759 /* Apalis USBO1_EN */ 760 gen2_i2c_scl_pt5 { 761 nvidia,pins = "gen2_i2c_scl_pt5"; 762 nvidia,function = "rsvd2"; 763 nvidia,pull = <TEGRA_PIN_PULL_NONE>; 764 nvidia,tristate = <TEGRA_PIN_DISABLE>; 765 nvidia,enable-input = <TEGRA_PIN_DISABLE>; 766 nvidia,open-drain = <TEGRA_PIN_DISABLE>; 767 }; 768 769 /* Apalis USBO1_OC# */ 770 pbb4 { 771 nvidia,pins = "pbb4"; 772 nvidia,function = "vgp4"; 773 nvidia,pull = <TEGRA_PIN_PULL_NONE>; 774 nvidia,tristate = <TEGRA_PIN_ENABLE>; 775 nvidia,enable-input = <TEGRA_PIN_ENABLE>; 776 }; 777 778 /* Apalis WAKE1_MICO */ 779 pex_wake_n_pdd3 { 780 nvidia,pins = "pex_wake_n_pdd3"; 781 nvidia,function = "rsvd2"; 782 nvidia,pull = <TEGRA_PIN_PULL_NONE>; 783 nvidia,tristate = <TEGRA_PIN_ENABLE>; 784 nvidia,enable-input = <TEGRA_PIN_ENABLE>; 785 }; 786 787 /* CORE_PWR_REQ */ 788 core_pwr_req { 789 nvidia,pins = "core_pwr_req"; 790 nvidia,function = "pwron"; 791 nvidia,pull = <TEGRA_PIN_PULL_NONE>; 792 nvidia,tristate = <TEGRA_PIN_DISABLE>; 793 nvidia,enable-input = <TEGRA_PIN_DISABLE>; 794 }; 795 796 /* CPU_PWR_REQ */ 797 cpu_pwr_req { 798 nvidia,pins = "cpu_pwr_req"; 799 nvidia,function = "cpu"; 800 nvidia,pull = <TEGRA_PIN_PULL_NONE>; 801 nvidia,tristate = <TEGRA_PIN_DISABLE>; 802 nvidia,enable-input = <TEGRA_PIN_DISABLE>; 803 }; 804 805 /* DVFS */ 806 dvfs_pwm_px0 { 807 nvidia,pins = "dvfs_pwm_px0"; 808 nvidia,function = "cldvfs"; 809 nvidia,pull = <TEGRA_PIN_PULL_NONE>; 810 nvidia,tristate = <TEGRA_PIN_DISABLE>; 811 nvidia,enable-input = <TEGRA_PIN_DISABLE>; 812 }; 813 dvfs_clk_px2 { 814 nvidia,pins = "dvfs_clk_px2"; 815 nvidia,function = "cldvfs"; 816 nvidia,pull = <TEGRA_PIN_PULL_NONE>; 817 nvidia,tristate = <TEGRA_PIN_DISABLE>; 818 nvidia,enable-input = <TEGRA_PIN_DISABLE>; 819 }; 820 821 /* eMMC */ 822 sdmmc4_dat0_paa0 { 823 nvidia,pins = "sdmmc4_dat0_paa0"; 824 nvidia,function = "sdmmc4"; 825 nvidia,pull = <TEGRA_PIN_PULL_UP>; 826 nvidia,tristate = <TEGRA_PIN_DISABLE>; 827 nvidia,enable-input = <TEGRA_PIN_ENABLE>; 828 }; 829 sdmmc4_dat1_paa1 { 830 nvidia,pins = "sdmmc4_dat1_paa1"; 831 nvidia,function = "sdmmc4"; 832 nvidia,pull = <TEGRA_PIN_PULL_UP>; 833 nvidia,tristate = <TEGRA_PIN_DISABLE>; 834 nvidia,enable-input = <TEGRA_PIN_ENABLE>; 835 }; 836 sdmmc4_dat2_paa2 { 837 nvidia,pins = "sdmmc4_dat2_paa2"; 838 nvidia,function = "sdmmc4"; 839 nvidia,pull = <TEGRA_PIN_PULL_UP>; 840 nvidia,tristate = <TEGRA_PIN_DISABLE>; 841 nvidia,enable-input = <TEGRA_PIN_ENABLE>; 842 }; 843 sdmmc4_dat3_paa3 { 844 nvidia,pins = "sdmmc4_dat3_paa3"; 845 nvidia,function = "sdmmc4"; 846 nvidia,pull = <TEGRA_PIN_PULL_UP>; 847 nvidia,tristate = <TEGRA_PIN_DISABLE>; 848 nvidia,enable-input = <TEGRA_PIN_ENABLE>; 849 }; 850 sdmmc4_dat4_paa4 { 851 nvidia,pins = "sdmmc4_dat4_paa4"; 852 nvidia,function = "sdmmc4"; 853 nvidia,pull = <TEGRA_PIN_PULL_UP>; 854 nvidia,tristate = <TEGRA_PIN_DISABLE>; 855 nvidia,enable-input = <TEGRA_PIN_ENABLE>; 856 }; 857 sdmmc4_dat5_paa5 { 858 nvidia,pins = "sdmmc4_dat5_paa5"; 859 nvidia,function = "sdmmc4"; 860 nvidia,pull = <TEGRA_PIN_PULL_UP>; 861 nvidia,tristate = <TEGRA_PIN_DISABLE>; 862 nvidia,enable-input = <TEGRA_PIN_ENABLE>; 863 }; 864 sdmmc4_dat6_paa6 { 865 nvidia,pins = "sdmmc4_dat6_paa6"; 866 nvidia,function = "sdmmc4"; 867 nvidia,pull = <TEGRA_PIN_PULL_UP>; 868 nvidia,tristate = <TEGRA_PIN_DISABLE>; 869 nvidia,enable-input = <TEGRA_PIN_ENABLE>; 870 }; 871 sdmmc4_dat7_paa7 { 872 nvidia,pins = "sdmmc4_dat7_paa7"; 873 nvidia,function = "sdmmc4"; 874 nvidia,pull = <TEGRA_PIN_PULL_UP>; 875 nvidia,tristate = <TEGRA_PIN_DISABLE>; 876 nvidia,enable-input = <TEGRA_PIN_ENABLE>; 877 }; 878 sdmmc4_clk_pcc4 { 879 nvidia,pins = "sdmmc4_clk_pcc4"; 880 nvidia,function = "sdmmc4"; 881 nvidia,pull = <TEGRA_PIN_PULL_NONE>; 882 nvidia,tristate = <TEGRA_PIN_DISABLE>; 883 nvidia,enable-input = <TEGRA_PIN_ENABLE>; 884 }; 885 sdmmc4_cmd_pt7 { 886 nvidia,pins = "sdmmc4_cmd_pt7"; 887 nvidia,function = "sdmmc4"; 888 nvidia,pull = <TEGRA_PIN_PULL_UP>; 889 nvidia,tristate = <TEGRA_PIN_DISABLE>; 890 nvidia,enable-input = <TEGRA_PIN_ENABLE>; 891 }; 892 893 /* JTAG_RTCK */ 894 jtag_rtck { 895 nvidia,pins = "jtag_rtck"; 896 nvidia,function = "rtck"; 897 nvidia,pull = <TEGRA_PIN_PULL_UP>; 898 nvidia,tristate = <TEGRA_PIN_DISABLE>; 899 nvidia,enable-input = <TEGRA_PIN_DISABLE>; 900 }; 901 902 /* LAN_DEV_OFF# */ 903 ulpi_data5_po6 { 904 nvidia,pins = "ulpi_data5_po6"; 905 nvidia,function = "ulpi"; 906 nvidia,pull = <TEGRA_PIN_PULL_UP>; 907 nvidia,tristate = <TEGRA_PIN_DISABLE>; 908 nvidia,enable-input = <TEGRA_PIN_DISABLE>; 909 }; 910 911 /* LAN_RESET# */ 912 kb_row10_ps2 { 913 nvidia,pins = "kb_row10_ps2"; 914 nvidia,function = "rsvd2"; 915 nvidia,pull = <TEGRA_PIN_PULL_UP>; 916 nvidia,tristate = <TEGRA_PIN_DISABLE>; 917 nvidia,enable-input = <TEGRA_PIN_DISABLE>; 918 }; 919 920 /* LAN_WAKE# */ 921 ulpi_data4_po5 { 922 nvidia,pins = "ulpi_data4_po5"; 923 nvidia,function = "ulpi"; 924 nvidia,pull = <TEGRA_PIN_PULL_NONE>; 925 nvidia,tristate = <TEGRA_PIN_ENABLE>; 926 nvidia,enable-input = <TEGRA_PIN_ENABLE>; 927 }; 928 929 /* MCU_INT1# */ 930 pk2 { 931 nvidia,pins = "pk2"; 932 nvidia,function = "rsvd1"; 933 nvidia,pull = <TEGRA_PIN_PULL_UP>; 934 nvidia,tristate = <TEGRA_PIN_ENABLE>; 935 nvidia,enable-input = <TEGRA_PIN_ENABLE>; 936 }; 937 938 /* MCU_INT2# */ 939 pj2 { 940 nvidia,pins = "pj2"; 941 nvidia,function = "rsvd1"; 942 nvidia,pull = <TEGRA_PIN_PULL_UP>; 943 nvidia,tristate = <TEGRA_PIN_ENABLE>; 944 nvidia,enable-input = <TEGRA_PIN_ENABLE>; 945 }; 946 947 /* MCU_INT3# */ 948 pi5 { 949 nvidia,pins = "pi5"; 950 nvidia,function = "rsvd2"; 951 nvidia,pull = <TEGRA_PIN_PULL_UP>; 952 nvidia,tristate = <TEGRA_PIN_ENABLE>; 953 nvidia,enable-input = <TEGRA_PIN_ENABLE>; 954 }; 955 956 /* MCU_INT4# */ 957 pj0 { 958 nvidia,pins = "pj0"; 959 nvidia,function = "rsvd1"; 960 nvidia,pull = <TEGRA_PIN_PULL_UP>; 961 nvidia,tristate = <TEGRA_PIN_ENABLE>; 962 nvidia,enable-input = <TEGRA_PIN_ENABLE>; 963 }; 964 965 /* MCU_RESET */ 966 pbb6 { 967 nvidia,pins = "pbb6"; 968 nvidia,function = "rsvd2"; 969 nvidia,pull = <TEGRA_PIN_PULL_NONE>; 970 nvidia,tristate = <TEGRA_PIN_DISABLE>; 971 nvidia,enable-input = <TEGRA_PIN_DISABLE>; 972 }; 973 974 /* MCU SPI */ 975 gpio_x4_aud_px4 { 976 nvidia,pins = "gpio_x4_aud_px4"; 977 nvidia,function = "spi2"; 978 nvidia,pull = <TEGRA_PIN_PULL_NONE>; 979 nvidia,tristate = <TEGRA_PIN_DISABLE>; 980 nvidia,enable-input = <TEGRA_PIN_DISABLE>; 981 }; 982 gpio_x5_aud_px5 { 983 nvidia,pins = "gpio_x5_aud_px5"; 984 nvidia,function = "spi2"; 985 nvidia,pull = <TEGRA_PIN_PULL_NONE>; 986 nvidia,tristate = <TEGRA_PIN_DISABLE>; 987 nvidia,enable-input = <TEGRA_PIN_DISABLE>; 988 }; 989 gpio_x6_aud_px6 { /* MCU_CS */ 990 nvidia,pins = "gpio_x6_aud_px6"; 991 nvidia,function = "spi2"; 992 nvidia,pull = <TEGRA_PIN_PULL_NONE>; 993 nvidia,tristate = <TEGRA_PIN_DISABLE>; 994 nvidia,enable-input = <TEGRA_PIN_DISABLE>; 995 }; 996 gpio_x7_aud_px7 { 997 nvidia,pins = "gpio_x7_aud_px7"; 998 nvidia,function = "spi2"; 999 nvidia,pull = <TEGRA_PIN_PULL_NONE>; 1000 nvidia,tristate = <TEGRA_PIN_ENABLE>; 1001 nvidia,enable-input = <TEGRA_PIN_ENABLE>; 1002 }; 1003 gpio_w2_aud_pw2 { /* MCU_CSEZP */ 1004 nvidia,pins = "gpio_w2_aud_pw2"; 1005 nvidia,function = "spi2"; 1006 nvidia,pull = <TEGRA_PIN_PULL_NONE>; 1007 nvidia,tristate = <TEGRA_PIN_DISABLE>; 1008 nvidia,enable-input = <TEGRA_PIN_DISABLE>; 1009 }; 1010 1011 /* PMIC_CLK_32K */ 1012 clk_32k_in { 1013 nvidia,pins = "clk_32k_in"; 1014 nvidia,function = "clk"; 1015 nvidia,pull = <TEGRA_PIN_PULL_NONE>; 1016 nvidia,tristate = <TEGRA_PIN_ENABLE>; 1017 nvidia,enable-input = <TEGRA_PIN_ENABLE>; 1018 }; 1019 1020 /* PMIC_CPU_OC_INT */ 1021 clk_32k_out_pa0 { 1022 nvidia,pins = "clk_32k_out_pa0"; 1023 nvidia,function = "soc"; 1024 nvidia,pull = <TEGRA_PIN_PULL_NONE>; 1025 nvidia,tristate = <TEGRA_PIN_ENABLE>; 1026 nvidia,enable-input = <TEGRA_PIN_ENABLE>; 1027 }; 1028 1029 /* PWR_I2C */ 1030 pwr_i2c_scl_pz6 { 1031 nvidia,pins = "pwr_i2c_scl_pz6"; 1032 nvidia,function = "i2cpwr"; 1033 nvidia,pull = <TEGRA_PIN_PULL_NONE>; 1034 nvidia,tristate = <TEGRA_PIN_DISABLE>; 1035 nvidia,enable-input = <TEGRA_PIN_ENABLE>; 1036 nvidia,open-drain = <TEGRA_PIN_ENABLE>; 1037 }; 1038 pwr_i2c_sda_pz7 { 1039 nvidia,pins = "pwr_i2c_sda_pz7"; 1040 nvidia,function = "i2cpwr"; 1041 nvidia,pull = <TEGRA_PIN_PULL_NONE>; 1042 nvidia,tristate = <TEGRA_PIN_DISABLE>; 1043 nvidia,enable-input = <TEGRA_PIN_ENABLE>; 1044 nvidia,open-drain = <TEGRA_PIN_ENABLE>; 1045 }; 1046 1047 /* PWR_INT_N */ 1048 pwr_int_n { 1049 nvidia,pins = "pwr_int_n"; 1050 nvidia,function = "pmi"; 1051 nvidia,pull = <TEGRA_PIN_PULL_UP>; 1052 nvidia,tristate = <TEGRA_PIN_ENABLE>; 1053 nvidia,enable-input = <TEGRA_PIN_ENABLE>; 1054 }; 1055 1056 /* RESET_MOCI_CTRL */ 1057 pu4 { 1058 nvidia,pins = "pu4"; 1059 nvidia,function = "gmi"; 1060 nvidia,pull = <TEGRA_PIN_PULL_NONE>; 1061 nvidia,tristate = <TEGRA_PIN_DISABLE>; 1062 nvidia,enable-input = <TEGRA_PIN_DISABLE>; 1063 }; 1064 1065 /* RESET_OUT_N */ 1066 reset_out_n { 1067 nvidia,pins = "reset_out_n"; 1068 nvidia,function = "reset_out_n"; 1069 nvidia,pull = <TEGRA_PIN_PULL_NONE>; 1070 nvidia,tristate = <TEGRA_PIN_DISABLE>; 1071 nvidia,enable-input = <TEGRA_PIN_ENABLE>; 1072 }; 1073 1074 /* SHIFT_CTRL_DIR_IN */ 1075 kb_row0_pr0 { 1076 nvidia,pins = "kb_row0_pr0"; 1077 nvidia,function = "rsvd2"; 1078 nvidia,pull = <TEGRA_PIN_PULL_DOWN>; 1079 nvidia,tristate = <TEGRA_PIN_ENABLE>; 1080 nvidia,enable-input = <TEGRA_PIN_DISABLE>; 1081 }; 1082 kb_row1_pr1 { 1083 nvidia,pins = "kb_row1_pr1"; 1084 nvidia,function = "rsvd2"; 1085 nvidia,pull = <TEGRA_PIN_PULL_DOWN>; 1086 nvidia,tristate = <TEGRA_PIN_ENABLE>; 1087 nvidia,enable-input = <TEGRA_PIN_DISABLE>; 1088 }; 1089 1090 /* Configure level-shifter as output for HDA */ 1091 kb_row11_ps3 { 1092 nvidia,pins = "kb_row11_ps3"; 1093 nvidia,function = "rsvd2"; 1094 nvidia,pull = <TEGRA_PIN_PULL_UP>; 1095 nvidia,tristate = <TEGRA_PIN_ENABLE>; 1096 nvidia,enable-input = <TEGRA_PIN_DISABLE>; 1097 }; 1098 1099 /* SHIFT_CTRL_DIR_OUT */ 1100 kb_col5_pq5 { 1101 nvidia,pins = "kb_col5_pq5"; 1102 nvidia,function = "rsvd2"; 1103 nvidia,pull = <TEGRA_PIN_PULL_UP>; 1104 nvidia,tristate = <TEGRA_PIN_ENABLE>; 1105 nvidia,enable-input = <TEGRA_PIN_DISABLE>; 1106 }; 1107 kb_col6_pq6 { 1108 nvidia,pins = "kb_col6_pq6"; 1109 nvidia,function = "rsvd2"; 1110 nvidia,pull = <TEGRA_PIN_PULL_UP>; 1111 nvidia,tristate = <TEGRA_PIN_ENABLE>; 1112 nvidia,enable-input = <TEGRA_PIN_DISABLE>; 1113 }; 1114 kb_col7_pq7 { 1115 nvidia,pins = "kb_col7_pq7"; 1116 nvidia,function = "rsvd2"; 1117 nvidia,pull = <TEGRA_PIN_PULL_UP>; 1118 nvidia,tristate = <TEGRA_PIN_ENABLE>; 1119 nvidia,enable-input = <TEGRA_PIN_DISABLE>; 1120 }; 1121 1122 /* SHIFT_CTRL_OE */ 1123 kb_col0_pq0 { 1124 nvidia,pins = "kb_col0_pq0"; 1125 nvidia,function = "rsvd2"; 1126 nvidia,pull = <TEGRA_PIN_PULL_DOWN>; 1127 nvidia,tristate = <TEGRA_PIN_ENABLE>; 1128 nvidia,enable-input = <TEGRA_PIN_DISABLE>; 1129 }; 1130 kb_col1_pq1 { 1131 nvidia,pins = "kb_col1_pq1"; 1132 nvidia,function = "rsvd2"; 1133 nvidia,pull = <TEGRA_PIN_PULL_DOWN>; 1134 nvidia,tristate = <TEGRA_PIN_ENABLE>; 1135 nvidia,enable-input = <TEGRA_PIN_DISABLE>; 1136 }; 1137 kb_col2_pq2 { 1138 nvidia,pins = "kb_col2_pq2"; 1139 nvidia,function = "rsvd2"; 1140 nvidia,pull = <TEGRA_PIN_PULL_DOWN>; 1141 nvidia,tristate = <TEGRA_PIN_ENABLE>; 1142 nvidia,enable-input = <TEGRA_PIN_DISABLE>; 1143 }; 1144 kb_col4_pq4 { 1145 nvidia,pins = "kb_col4_pq4"; 1146 nvidia,function = "kbc"; 1147 nvidia,pull = <TEGRA_PIN_PULL_DOWN>; 1148 nvidia,tristate = <TEGRA_PIN_ENABLE>; 1149 nvidia,enable-input = <TEGRA_PIN_DISABLE>; 1150 }; 1151 kb_row2_pr2 { 1152 nvidia,pins = "kb_row2_pr2"; 1153 nvidia,function = "rsvd2"; 1154 nvidia,pull = <TEGRA_PIN_PULL_DOWN>; 1155 nvidia,tristate = <TEGRA_PIN_ENABLE>; 1156 nvidia,enable-input = <TEGRA_PIN_DISABLE>; 1157 }; 1158 1159 /* GPIO_PI6 aka TMP451 ALERT#/THERM2# */ 1160 pi6 { 1161 nvidia,pins = "pi6"; 1162 nvidia,function = "rsvd1"; 1163 nvidia,pull = <TEGRA_PIN_PULL_UP>; 1164 nvidia,tristate = <TEGRA_PIN_ENABLE>; 1165 nvidia,enable-input = <TEGRA_PIN_ENABLE>; 1166 }; 1167 1168 /* TOUCH_INT */ 1169 gpio_w3_aud_pw3 { 1170 nvidia,pins = "gpio_w3_aud_pw3"; 1171 nvidia,function = "spi6"; 1172 nvidia,pull = <TEGRA_PIN_PULL_NONE>; 1173 nvidia,tristate = <TEGRA_PIN_ENABLE>; 1174 nvidia,enable-input = <TEGRA_PIN_ENABLE>; 1175 }; 1176 1177 pc7 { /* NC */ 1178 nvidia,pins = "pc7"; 1179 nvidia,function = "rsvd1"; 1180 nvidia,pull = <TEGRA_PIN_PULL_DOWN>; 1181 nvidia,tristate = <TEGRA_PIN_ENABLE>; 1182 nvidia,enable-input = <TEGRA_PIN_DISABLE>; 1183 }; 1184 pg0 { /* NC */ 1185 nvidia,pins = "pg0"; 1186 nvidia,function = "rsvd1"; 1187 nvidia,pull = <TEGRA_PIN_PULL_DOWN>; 1188 nvidia,tristate = <TEGRA_PIN_ENABLE>; 1189 nvidia,enable-input = <TEGRA_PIN_DISABLE>; 1190 }; 1191 pg1 { /* NC */ 1192 nvidia,pins = "pg1"; 1193 nvidia,function = "rsvd1"; 1194 nvidia,pull = <TEGRA_PIN_PULL_DOWN>; 1195 nvidia,tristate = <TEGRA_PIN_ENABLE>; 1196 nvidia,enable-input = <TEGRA_PIN_DISABLE>; 1197 }; 1198 pg2 { /* NC */ 1199 nvidia,pins = "pg2"; 1200 nvidia,function = "rsvd1"; 1201 nvidia,pull = <TEGRA_PIN_PULL_DOWN>; 1202 nvidia,tristate = <TEGRA_PIN_ENABLE>; 1203 nvidia,enable-input = <TEGRA_PIN_DISABLE>; 1204 }; 1205 pg3 { /* NC */ 1206 nvidia,pins = "pg3"; 1207 nvidia,function = "rsvd1"; 1208 nvidia,pull = <TEGRA_PIN_PULL_DOWN>; 1209 nvidia,tristate = <TEGRA_PIN_ENABLE>; 1210 nvidia,enable-input = <TEGRA_PIN_DISABLE>; 1211 }; 1212 pg4 { /* NC */ 1213 nvidia,pins = "pg4"; 1214 nvidia,function = "rsvd1"; 1215 nvidia,pull = <TEGRA_PIN_PULL_DOWN>; 1216 nvidia,tristate = <TEGRA_PIN_ENABLE>; 1217 nvidia,enable-input = <TEGRA_PIN_DISABLE>; 1218 }; 1219 ph4 { /* NC */ 1220 nvidia,pins = "ph4"; 1221 nvidia,function = "rsvd2"; 1222 nvidia,pull = <TEGRA_PIN_PULL_DOWN>; 1223 nvidia,tristate = <TEGRA_PIN_ENABLE>; 1224 nvidia,enable-input = <TEGRA_PIN_DISABLE>; 1225 }; 1226 ph5 { /* NC */ 1227 nvidia,pins = "ph5"; 1228 nvidia,function = "rsvd2"; 1229 nvidia,pull = <TEGRA_PIN_PULL_DOWN>; 1230 nvidia,tristate = <TEGRA_PIN_ENABLE>; 1231 nvidia,enable-input = <TEGRA_PIN_DISABLE>; 1232 }; 1233 ph6 { /* NC */ 1234 nvidia,pins = "ph6"; 1235 nvidia,function = "gmi"; 1236 nvidia,pull = <TEGRA_PIN_PULL_DOWN>; 1237 nvidia,tristate = <TEGRA_PIN_ENABLE>; 1238 nvidia,enable-input = <TEGRA_PIN_DISABLE>; 1239 }; 1240 ph7 { /* NC */ 1241 nvidia,pins = "ph7"; 1242 nvidia,function = "gmi"; 1243 nvidia,pull = <TEGRA_PIN_PULL_DOWN>; 1244 nvidia,tristate = <TEGRA_PIN_ENABLE>; 1245 nvidia,enable-input = <TEGRA_PIN_DISABLE>; 1246 }; 1247 pi0 { /* NC */ 1248 nvidia,pins = "pi0"; 1249 nvidia,function = "rsvd1"; 1250 nvidia,pull = <TEGRA_PIN_PULL_DOWN>; 1251 nvidia,tristate = <TEGRA_PIN_ENABLE>; 1252 nvidia,enable-input = <TEGRA_PIN_DISABLE>; 1253 }; 1254 pi1 { /* NC */ 1255 nvidia,pins = "pi1"; 1256 nvidia,function = "rsvd1"; 1257 nvidia,pull = <TEGRA_PIN_PULL_DOWN>; 1258 nvidia,tristate = <TEGRA_PIN_ENABLE>; 1259 nvidia,enable-input = <TEGRA_PIN_DISABLE>; 1260 }; 1261 pi2 { /* NC */ 1262 nvidia,pins = "pi2"; 1263 nvidia,function = "rsvd4"; 1264 nvidia,pull = <TEGRA_PIN_PULL_DOWN>; 1265 nvidia,tristate = <TEGRA_PIN_ENABLE>; 1266 nvidia,enable-input = <TEGRA_PIN_DISABLE>; 1267 }; 1268 pi4 { /* NC */ 1269 nvidia,pins = "pi4"; 1270 nvidia,function = "gmi"; 1271 nvidia,pull = <TEGRA_PIN_PULL_DOWN>; 1272 nvidia,tristate = <TEGRA_PIN_ENABLE>; 1273 nvidia,enable-input = <TEGRA_PIN_DISABLE>; 1274 }; 1275 pi7 { /* NC */ 1276 nvidia,pins = "pi7"; 1277 nvidia,function = "rsvd1"; 1278 nvidia,pull = <TEGRA_PIN_PULL_DOWN>; 1279 nvidia,tristate = <TEGRA_PIN_ENABLE>; 1280 nvidia,enable-input = <TEGRA_PIN_DISABLE>; 1281 }; 1282 pk0 { /* NC */ 1283 nvidia,pins = "pk0"; 1284 nvidia,function = "rsvd1"; 1285 nvidia,pull = <TEGRA_PIN_PULL_DOWN>; 1286 nvidia,tristate = <TEGRA_PIN_ENABLE>; 1287 nvidia,enable-input = <TEGRA_PIN_DISABLE>; 1288 }; 1289 pk1 { /* NC */ 1290 nvidia,pins = "pk1"; 1291 nvidia,function = "rsvd4"; 1292 nvidia,pull = <TEGRA_PIN_PULL_DOWN>; 1293 nvidia,tristate = <TEGRA_PIN_ENABLE>; 1294 nvidia,enable-input = <TEGRA_PIN_DISABLE>; 1295 }; 1296 pk3 { /* NC */ 1297 nvidia,pins = "pk3"; 1298 nvidia,function = "gmi"; 1299 nvidia,pull = <TEGRA_PIN_PULL_DOWN>; 1300 nvidia,tristate = <TEGRA_PIN_ENABLE>; 1301 nvidia,enable-input = <TEGRA_PIN_DISABLE>; 1302 }; 1303 pk4 { /* NC */ 1304 nvidia,pins = "pk4"; 1305 nvidia,function = "rsvd2"; 1306 nvidia,pull = <TEGRA_PIN_PULL_DOWN>; 1307 nvidia,tristate = <TEGRA_PIN_ENABLE>; 1308 nvidia,enable-input = <TEGRA_PIN_DISABLE>; 1309 }; 1310 dap1_fs_pn0 { /* NC */ 1311 nvidia,pins = "dap1_fs_pn0"; 1312 nvidia,function = "rsvd4"; 1313 nvidia,pull = <TEGRA_PIN_PULL_DOWN>; 1314 nvidia,tristate = <TEGRA_PIN_ENABLE>; 1315 nvidia,enable-input = <TEGRA_PIN_DISABLE>; 1316 }; 1317 dap1_din_pn1 { /* NC */ 1318 nvidia,pins = "dap1_din_pn1"; 1319 nvidia,function = "rsvd4"; 1320 nvidia,pull = <TEGRA_PIN_PULL_DOWN>; 1321 nvidia,tristate = <TEGRA_PIN_ENABLE>; 1322 nvidia,enable-input = <TEGRA_PIN_DISABLE>; 1323 }; 1324 dap1_sclk_pn3 { /* NC */ 1325 nvidia,pins = "dap1_sclk_pn3"; 1326 nvidia,function = "rsvd4"; 1327 nvidia,pull = <TEGRA_PIN_PULL_DOWN>; 1328 nvidia,tristate = <TEGRA_PIN_ENABLE>; 1329 nvidia,enable-input = <TEGRA_PIN_DISABLE>; 1330 }; 1331 ulpi_data7_po0 { /* NC */ 1332 nvidia,pins = "ulpi_data7_po0"; 1333 nvidia,function = "ulpi"; 1334 nvidia,pull = <TEGRA_PIN_PULL_DOWN>; 1335 nvidia,tristate = <TEGRA_PIN_ENABLE>; 1336 nvidia,enable-input = <TEGRA_PIN_DISABLE>; 1337 }; 1338 ulpi_data0_po1 { /* NC */ 1339 nvidia,pins = "ulpi_data0_po1"; 1340 nvidia,function = "ulpi"; 1341 nvidia,pull = <TEGRA_PIN_PULL_DOWN>; 1342 nvidia,tristate = <TEGRA_PIN_ENABLE>; 1343 nvidia,enable-input = <TEGRA_PIN_DISABLE>; 1344 }; 1345 ulpi_data1_po2 { /* NC */ 1346 nvidia,pins = "ulpi_data1_po2"; 1347 nvidia,function = "ulpi"; 1348 nvidia,pull = <TEGRA_PIN_PULL_DOWN>; 1349 nvidia,tristate = <TEGRA_PIN_ENABLE>; 1350 nvidia,enable-input = <TEGRA_PIN_DISABLE>; 1351 }; 1352 ulpi_data2_po3 { /* NC */ 1353 nvidia,pins = "ulpi_data2_po3"; 1354 nvidia,function = "ulpi"; 1355 nvidia,pull = <TEGRA_PIN_PULL_DOWN>; 1356 nvidia,tristate = <TEGRA_PIN_ENABLE>; 1357 nvidia,enable-input = <TEGRA_PIN_DISABLE>; 1358 }; 1359 ulpi_data3_po4 { /* NC */ 1360 nvidia,pins = "ulpi_data3_po4"; 1361 nvidia,function = "ulpi"; 1362 nvidia,pull = <TEGRA_PIN_PULL_DOWN>; 1363 nvidia,tristate = <TEGRA_PIN_ENABLE>; 1364 nvidia,enable-input = <TEGRA_PIN_DISABLE>; 1365 }; 1366 ulpi_data6_po7 { /* NC */ 1367 nvidia,pins = "ulpi_data6_po7"; 1368 nvidia,function = "ulpi"; 1369 nvidia,pull = <TEGRA_PIN_PULL_DOWN>; 1370 nvidia,tristate = <TEGRA_PIN_ENABLE>; 1371 nvidia,enable-input = <TEGRA_PIN_DISABLE>; 1372 }; 1373 dap4_fs_pp4 { /* NC */ 1374 nvidia,pins = "dap4_fs_pp4"; 1375 nvidia,function = "rsvd4"; 1376 nvidia,pull = <TEGRA_PIN_PULL_DOWN>; 1377 nvidia,tristate = <TEGRA_PIN_ENABLE>; 1378 nvidia,enable-input = <TEGRA_PIN_DISABLE>; 1379 }; 1380 dap4_din_pp5 { /* NC */ 1381 nvidia,pins = "dap4_din_pp5"; 1382 nvidia,function = "rsvd3"; 1383 nvidia,pull = <TEGRA_PIN_PULL_DOWN>; 1384 nvidia,tristate = <TEGRA_PIN_ENABLE>; 1385 nvidia,enable-input = <TEGRA_PIN_DISABLE>; 1386 }; 1387 dap4_dout_pp6 { /* NC */ 1388 nvidia,pins = "dap4_dout_pp6"; 1389 nvidia,function = "rsvd4"; 1390 nvidia,pull = <TEGRA_PIN_PULL_DOWN>; 1391 nvidia,tristate = <TEGRA_PIN_ENABLE>; 1392 nvidia,enable-input = <TEGRA_PIN_DISABLE>; 1393 }; 1394 dap4_sclk_pp7 { /* NC */ 1395 nvidia,pins = "dap4_sclk_pp7"; 1396 nvidia,function = "rsvd3"; 1397 nvidia,pull = <TEGRA_PIN_PULL_DOWN>; 1398 nvidia,tristate = <TEGRA_PIN_ENABLE>; 1399 nvidia,enable-input = <TEGRA_PIN_DISABLE>; 1400 }; 1401 kb_col3_pq3 { /* NC */ 1402 nvidia,pins = "kb_col3_pq3"; 1403 nvidia,function = "kbc"; 1404 nvidia,pull = <TEGRA_PIN_PULL_DOWN>; 1405 nvidia,tristate = <TEGRA_PIN_ENABLE>; 1406 nvidia,enable-input = <TEGRA_PIN_DISABLE>; 1407 }; 1408 kb_row3_pr3 { /* NC */ 1409 nvidia,pins = "kb_row3_pr3"; 1410 nvidia,function = "kbc"; 1411 nvidia,pull = <TEGRA_PIN_PULL_DOWN>; 1412 nvidia,tristate = <TEGRA_PIN_ENABLE>; 1413 nvidia,enable-input = <TEGRA_PIN_DISABLE>; 1414 }; 1415 kb_row4_pr4 { /* NC */ 1416 nvidia,pins = "kb_row4_pr4"; 1417 nvidia,function = "rsvd3"; 1418 nvidia,pull = <TEGRA_PIN_PULL_DOWN>; 1419 nvidia,tristate = <TEGRA_PIN_ENABLE>; 1420 nvidia,enable-input = <TEGRA_PIN_DISABLE>; 1421 }; 1422 kb_row5_pr5 { /* NC */ 1423 nvidia,pins = "kb_row5_pr5"; 1424 nvidia,function = "rsvd3"; 1425 nvidia,pull = <TEGRA_PIN_PULL_DOWN>; 1426 nvidia,tristate = <TEGRA_PIN_ENABLE>; 1427 nvidia,enable-input = <TEGRA_PIN_DISABLE>; 1428 }; 1429 kb_row6_pr6 { /* NC */ 1430 nvidia,pins = "kb_row6_pr6"; 1431 nvidia,function = "kbc"; 1432 nvidia,pull = <TEGRA_PIN_PULL_DOWN>; 1433 nvidia,tristate = <TEGRA_PIN_ENABLE>; 1434 nvidia,enable-input = <TEGRA_PIN_DISABLE>; 1435 }; 1436 kb_row7_pr7 { /* NC */ 1437 nvidia,pins = "kb_row7_pr7"; 1438 nvidia,function = "rsvd2"; 1439 nvidia,pull = <TEGRA_PIN_PULL_DOWN>; 1440 nvidia,tristate = <TEGRA_PIN_ENABLE>; 1441 nvidia,enable-input = <TEGRA_PIN_DISABLE>; 1442 }; 1443 kb_row8_ps0 { /* NC */ 1444 nvidia,pins = "kb_row8_ps0"; 1445 nvidia,function = "rsvd2"; 1446 nvidia,pull = <TEGRA_PIN_PULL_DOWN>; 1447 nvidia,tristate = <TEGRA_PIN_ENABLE>; 1448 nvidia,enable-input = <TEGRA_PIN_DISABLE>; 1449 }; 1450 kb_row9_ps1 { /* NC */ 1451 nvidia,pins = "kb_row9_ps1"; 1452 nvidia,function = "rsvd2"; 1453 nvidia,pull = <TEGRA_PIN_PULL_DOWN>; 1454 nvidia,tristate = <TEGRA_PIN_ENABLE>; 1455 nvidia,enable-input = <TEGRA_PIN_DISABLE>; 1456 }; 1457 kb_row12_ps4 { /* NC */ 1458 nvidia,pins = "kb_row12_ps4"; 1459 nvidia,function = "rsvd2"; 1460 nvidia,pull = <TEGRA_PIN_PULL_DOWN>; 1461 nvidia,tristate = <TEGRA_PIN_ENABLE>; 1462 nvidia,enable-input = <TEGRA_PIN_DISABLE>; 1463 }; 1464 kb_row13_ps5 { /* NC */ 1465 nvidia,pins = "kb_row13_ps5"; 1466 nvidia,function = "rsvd2"; 1467 nvidia,pull = <TEGRA_PIN_PULL_DOWN>; 1468 nvidia,tristate = <TEGRA_PIN_ENABLE>; 1469 nvidia,enable-input = <TEGRA_PIN_DISABLE>; 1470 }; 1471 kb_row14_ps6 { /* NC */ 1472 nvidia,pins = "kb_row14_ps6"; 1473 nvidia,function = "rsvd2"; 1474 nvidia,pull = <TEGRA_PIN_PULL_DOWN>; 1475 nvidia,tristate = <TEGRA_PIN_ENABLE>; 1476 nvidia,enable-input = <TEGRA_PIN_DISABLE>; 1477 }; 1478 kb_row15_ps7 { /* NC */ 1479 nvidia,pins = "kb_row15_ps7"; 1480 nvidia,function = "rsvd3"; 1481 nvidia,pull = <TEGRA_PIN_PULL_DOWN>; 1482 nvidia,tristate = <TEGRA_PIN_ENABLE>; 1483 nvidia,enable-input = <TEGRA_PIN_DISABLE>; 1484 }; 1485 kb_row16_pt0 { /* NC */ 1486 nvidia,pins = "kb_row16_pt0"; 1487 nvidia,function = "rsvd2"; 1488 nvidia,pull = <TEGRA_PIN_PULL_DOWN>; 1489 nvidia,tristate = <TEGRA_PIN_ENABLE>; 1490 nvidia,enable-input = <TEGRA_PIN_DISABLE>; 1491 }; 1492 kb_row17_pt1 { /* NC */ 1493 nvidia,pins = "kb_row17_pt1"; 1494 nvidia,function = "rsvd2"; 1495 nvidia,pull = <TEGRA_PIN_PULL_DOWN>; 1496 nvidia,tristate = <TEGRA_PIN_ENABLE>; 1497 nvidia,enable-input = <TEGRA_PIN_DISABLE>; 1498 }; 1499 pu5 { /* NC */ 1500 nvidia,pins = "pu5"; 1501 nvidia,function = "gmi"; 1502 nvidia,pull = <TEGRA_PIN_PULL_DOWN>; 1503 nvidia,tristate = <TEGRA_PIN_ENABLE>; 1504 nvidia,enable-input = <TEGRA_PIN_DISABLE>; 1505 }; 1506 /* 1507 * PCB Version Indication: V1.2 and later have GPIO_PV0 1508 * wired to GND, was NC before 1509 */ 1510 pv0 { 1511 nvidia,pins = "pv0"; 1512 nvidia,function = "rsvd1"; 1513 nvidia,pull = <TEGRA_PIN_PULL_UP>; 1514 nvidia,tristate = <TEGRA_PIN_ENABLE>; 1515 nvidia,enable-input = <TEGRA_PIN_DISABLE>; 1516 }; 1517 pv1 { /* NC */ 1518 nvidia,pins = "pv1"; 1519 nvidia,function = "rsvd1"; 1520 nvidia,pull = <TEGRA_PIN_PULL_DOWN>; 1521 nvidia,tristate = <TEGRA_PIN_ENABLE>; 1522 nvidia,enable-input = <TEGRA_PIN_DISABLE>; 1523 }; 1524 gpio_x1_aud_px1 { /* NC */ 1525 nvidia,pins = "gpio_x1_aud_px1"; 1526 nvidia,function = "rsvd2"; 1527 nvidia,pull = <TEGRA_PIN_PULL_DOWN>; 1528 nvidia,tristate = <TEGRA_PIN_ENABLE>; 1529 nvidia,enable-input = <TEGRA_PIN_DISABLE>; 1530 }; 1531 gpio_x3_aud_px3 { /* NC */ 1532 nvidia,pins = "gpio_x3_aud_px3"; 1533 nvidia,function = "rsvd4"; 1534 nvidia,pull = <TEGRA_PIN_PULL_DOWN>; 1535 nvidia,tristate = <TEGRA_PIN_ENABLE>; 1536 nvidia,enable-input = <TEGRA_PIN_DISABLE>; 1537 }; 1538 pbb7 { /* NC */ 1539 nvidia,pins = "pbb7"; 1540 nvidia,function = "rsvd2"; 1541 nvidia,pull = <TEGRA_PIN_PULL_DOWN>; 1542 nvidia,tristate = <TEGRA_PIN_ENABLE>; 1543 nvidia,enable-input = <TEGRA_PIN_DISABLE>; 1544 }; 1545 pcc1 { /* NC */ 1546 nvidia,pins = "pcc1"; 1547 nvidia,function = "rsvd2"; 1548 nvidia,pull = <TEGRA_PIN_PULL_DOWN>; 1549 nvidia,tristate = <TEGRA_PIN_ENABLE>; 1550 nvidia,enable-input = <TEGRA_PIN_DISABLE>; 1551 }; 1552 pcc2 { /* NC */ 1553 nvidia,pins = "pcc2"; 1554 nvidia,function = "rsvd2"; 1555 nvidia,pull = <TEGRA_PIN_PULL_DOWN>; 1556 nvidia,tristate = <TEGRA_PIN_ENABLE>; 1557 nvidia,enable-input = <TEGRA_PIN_DISABLE>; 1558 }; 1559 clk3_req_pee1 { /* NC */ 1560 nvidia,pins = "clk3_req_pee1"; 1561 nvidia,function = "rsvd2"; 1562 nvidia,pull = <TEGRA_PIN_PULL_DOWN>; 1563 nvidia,tristate = <TEGRA_PIN_ENABLE>; 1564 nvidia,enable-input = <TEGRA_PIN_DISABLE>; 1565 }; 1566 dap_mclk1_req_pee2 { /* NC */ 1567 nvidia,pins = "dap_mclk1_req_pee2"; 1568 nvidia,function = "rsvd4"; 1569 nvidia,pull = <TEGRA_PIN_PULL_DOWN>; 1570 nvidia,tristate = <TEGRA_PIN_ENABLE>; 1571 nvidia,enable-input = <TEGRA_PIN_DISABLE>; 1572 }; 1573 /* 1574 * Leave SDMMC3_CLK_LB_OUT muxed as SDMMC3 with output 1575 * driver enabled aka not tristated and input driver 1576 * enabled as well as it features some magic properties 1577 * even though the external loopback is disabled and the 1578 * internal loopback used as per 1579 * SDMMC_VENDOR_MISC_CNTRL_0 register's SDMMC_SPARE1 1580 * bits being set to 0xfffd according to the TRM! 1581 */ 1582 sdmmc3_clk_lb_out_pee4 { /* NC */ 1583 nvidia,pins = "sdmmc3_clk_lb_out_pee4"; 1584 nvidia,function = "sdmmc3"; 1585 nvidia,pull = <TEGRA_PIN_PULL_NONE>; 1586 nvidia,tristate = <TEGRA_PIN_DISABLE>; 1587 nvidia,enable-input = <TEGRA_PIN_ENABLE>; 1588 }; 1589 }; 1590 }; 1591 1592 /* Apalis UART1 */ 1593 serial@70006000 { 1594 status = "okay"; 1595 }; 1596 1597 /* Apalis UART2 */ 1598 serial@70006040 { 1599 compatible = "nvidia,tegra124-hsuart"; 1600 status = "okay"; 1601 }; 1602 1603 /* Apalis UART3 */ 1604 serial@70006200 { 1605 compatible = "nvidia,tegra124-hsuart"; 1606 status = "okay"; 1607 }; 1608 1609 /* Apalis UART4 */ 1610 serial@70006300 { 1611 compatible = "nvidia,tegra124-hsuart"; 1612 status = "okay"; 1613 }; 1614 1615 pwm@7000a000 { 1616 status = "okay"; 1617 }; 1618 1619 /* 1620 * GEN1_I2C: I2C1_SDA/SCL on MXM3 pin 209/211 (e.g. RTC on carrier 1621 * board) 1622 */ 1623 i2c@7000c000 { 1624 status = "okay"; 1625 clock-frequency = <400000>; 1626 1627 pcie-switch@58 { 1628 compatible = "plx,pex8605"; 1629 reg = <0x58>; 1630 }; 1631 1632 /* M41T0M6 real time clock on carrier board */ 1633 rtc@68 { 1634 compatible = "st,m41t00"; 1635 reg = <0x68>; 1636 }; 1637 }; 1638 1639 /* GEN2_I2C: unused */ 1640 1641 /* 1642 * CAM_I2C: I2C3_SDA/SCL (CAM) on MXM3 pin 201/203 (e.g. camera sensor 1643 * on carrier board) 1644 */ 1645 i2c@7000c500 { 1646 status = "okay"; 1647 clock-frequency = <400000>; 1648 }; 1649 1650 /* 1651 * I2C4 (DDC): I2C4_SDA/SCL (DDC) on MXM3 pin 205/207 1652 * (e.g. display EDID) 1653 */ 1654 hdmi_ddc: i2c@7000c700 { 1655 status = "okay"; 1656 clock-frequency = <10000>; 1657 }; 1658 1659 /* PWR_I2C: power I2C to audio codec, PMIC and temperature sensor */ 1660 i2c@7000d000 { 1661 status = "okay"; 1662 clock-frequency = <400000>; 1663 1664 /* SGTL5000 audio codec */ 1665 sgtl5000: codec@a { 1666 compatible = "fsl,sgtl5000"; 1667 reg = <0x0a>; 1668 VDDA-supply = <®_3v3>; 1669 VDDIO-supply = <&vddio_1v8>; 1670 clocks = <&tegra_car TEGRA124_CLK_EXTERN1>; 1671 }; 1672 1673 pmic: pmic@40 { 1674 compatible = "ams,as3722"; 1675 reg = <0x40>; 1676 interrupts = <0 86 IRQ_TYPE_LEVEL_HIGH>; 1677 ams,system-power-controller; 1678 #interrupt-cells = <2>; 1679 interrupt-controller; 1680 gpio-controller; 1681 #gpio-cells = <2>; 1682 pinctrl-names = "default"; 1683 pinctrl-0 = <&as3722_default>; 1684 1685 as3722_default: pinmux { 1686 gpio2_7 { 1687 pins = "gpio2", /* PWR_EN_+V3.3 */ 1688 "gpio7"; /* +V1.6_LPO */ 1689 function = "gpio"; 1690 bias-pull-up; 1691 }; 1692 1693 gpio0_1_3_4_5_6 { 1694 pins = "gpio0", "gpio1", "gpio3", 1695 "gpio4", "gpio5", "gpio6"; 1696 bias-high-impedance; 1697 }; 1698 }; 1699 1700 regulators { 1701 vsup-sd2-supply = <®_3v3>; 1702 vsup-sd3-supply = <®_3v3>; 1703 vsup-sd4-supply = <®_3v3>; 1704 vsup-sd5-supply = <®_3v3>; 1705 vin-ldo0-supply = <&vddio_ddr_1v35>; 1706 vin-ldo1-6-supply = <®_3v3>; 1707 vin-ldo2-5-7-supply = <&vddio_1v8>; 1708 vin-ldo3-4-supply = <®_3v3>; 1709 vin-ldo9-10-supply = <®_3v3>; 1710 vin-ldo11-supply = <®_3v3>; 1711 1712 vdd_cpu: sd0 { 1713 regulator-name = "+VDD_CPU_AP"; 1714 regulator-min-microvolt = <700000>; 1715 regulator-max-microvolt = <1400000>; 1716 regulator-min-microamp = <3500000>; 1717 regulator-max-microamp = <3500000>; 1718 regulator-always-on; 1719 regulator-boot-on; 1720 ams,ext-control = <2>; 1721 }; 1722 1723 sd1 { 1724 regulator-name = "+VDD_CORE"; 1725 regulator-min-microvolt = <700000>; 1726 regulator-max-microvolt = <1350000>; 1727 regulator-min-microamp = <2500000>; 1728 regulator-max-microamp = <4000000>; 1729 regulator-always-on; 1730 regulator-boot-on; 1731 ams,ext-control = <1>; 1732 }; 1733 1734 vddio_ddr_1v35: sd2 { 1735 regulator-name = 1736 "+V1.35_VDDIO_DDR(sd2)"; 1737 regulator-min-microvolt = <1350000>; 1738 regulator-max-microvolt = <1350000>; 1739 regulator-always-on; 1740 regulator-boot-on; 1741 }; 1742 1743 sd3 { 1744 regulator-name = 1745 "+V1.35_VDDIO_DDR(sd3)"; 1746 regulator-min-microvolt = <1350000>; 1747 regulator-max-microvolt = <1350000>; 1748 regulator-always-on; 1749 regulator-boot-on; 1750 }; 1751 1752 vdd_1v05: sd4 { 1753 regulator-name = "+V1.05"; 1754 regulator-min-microvolt = <1050000>; 1755 regulator-max-microvolt = <1050000>; 1756 }; 1757 1758 vddio_1v8: sd5 { 1759 regulator-name = "+V1.8"; 1760 regulator-min-microvolt = <1800000>; 1761 regulator-max-microvolt = <1800000>; 1762 regulator-boot-on; 1763 regulator-always-on; 1764 }; 1765 1766 vdd_gpu: sd6 { 1767 regulator-name = "+VDD_GPU_AP"; 1768 regulator-min-microvolt = <650000>; 1769 regulator-max-microvolt = <1200000>; 1770 regulator-min-microamp = <3500000>; 1771 regulator-max-microamp = <3500000>; 1772 regulator-boot-on; 1773 regulator-always-on; 1774 }; 1775 1776 avdd_1v05: ldo0 { 1777 regulator-name = "+V1.05_AVDD"; 1778 regulator-min-microvolt = <1050000>; 1779 regulator-max-microvolt = <1050000>; 1780 regulator-boot-on; 1781 regulator-always-on; 1782 ams,ext-control = <1>; 1783 }; 1784 1785 vddio_sdmmc1: ldo1 { 1786 regulator-name = "VDDIO_SDMMC1"; 1787 regulator-min-microvolt = <1800000>; 1788 regulator-max-microvolt = <3300000>; 1789 }; 1790 1791 ldo2 { 1792 regulator-name = "+V1.2"; 1793 regulator-min-microvolt = <1200000>; 1794 regulator-max-microvolt = <1200000>; 1795 regulator-boot-on; 1796 regulator-always-on; 1797 }; 1798 1799 ldo3 { 1800 regulator-name = "+V1.05_RTC"; 1801 regulator-min-microvolt = <1000000>; 1802 regulator-max-microvolt = <1000000>; 1803 regulator-boot-on; 1804 regulator-always-on; 1805 ams,enable-tracking; 1806 }; 1807 1808 /* 1.8V for LVDS, 3.3V for eDP */ 1809 ldo4 { 1810 regulator-name = "AVDD_LVDS0_PLL"; 1811 regulator-min-microvolt = <1800000>; 1812 regulator-max-microvolt = <1800000>; 1813 }; 1814 1815 /* LDO5 not used */ 1816 1817 vddio_sdmmc3: ldo6 { 1818 regulator-name = "VDDIO_SDMMC3"; 1819 regulator-min-microvolt = <1800000>; 1820 regulator-max-microvolt = <3300000>; 1821 }; 1822 1823 /* LDO7 not used */ 1824 1825 ldo9 { 1826 regulator-name = "+V3.3_ETH(ldo9)"; 1827 regulator-min-microvolt = <3300000>; 1828 regulator-max-microvolt = <3300000>; 1829 regulator-always-on; 1830 }; 1831 1832 ldo10 { 1833 regulator-name = "+V3.3_ETH(ldo10)"; 1834 regulator-min-microvolt = <3300000>; 1835 regulator-max-microvolt = <3300000>; 1836 regulator-always-on; 1837 }; 1838 1839 ldo11 { 1840 regulator-name = "+V1.8_VPP_FUSE"; 1841 regulator-min-microvolt = <1800000>; 1842 regulator-max-microvolt = <1800000>; 1843 }; 1844 }; 1845 }; 1846 1847 /* 1848 * TMP451 temperature sensor 1849 * Note: THERM_N directly connected to AS3722 PMIC THERM 1850 */ 1851 temperature-sensor@4c { 1852 compatible = "ti,tmp451"; 1853 reg = <0x4c>; 1854 interrupt-parent = <&gpio>; 1855 interrupts = <TEGRA_GPIO(I, 6) IRQ_TYPE_LEVEL_LOW>; 1856 #thermal-sensor-cells = <1>; 1857 }; 1858 }; 1859 1860 /* SPI1: Apalis SPI1 */ 1861 spi@7000d400 { 1862 status = "okay"; 1863 spi-max-frequency = <50000000>; 1864 1865 spidev0: spidev@0 { 1866 compatible = "spidev"; 1867 reg = <0>; 1868 spi-max-frequency = <50000000>; 1869 }; 1870 }; 1871 1872 /* SPI2: MCU SPI */ 1873 spi@7000d600 { 1874 status = "okay"; 1875 spi-max-frequency = <25000000>; 1876 }; 1877 1878 /* SPI4: Apalis SPI2 */ 1879 spi@7000da00 { 1880 status = "okay"; 1881 spi-max-frequency = <50000000>; 1882 1883 spidev1: spidev@0 { 1884 compatible = "spidev"; 1885 reg = <0>; 1886 spi-max-frequency = <50000000>; 1887 }; 1888 }; 1889 1890 pmc@7000e400 { 1891 nvidia,invert-interrupt; 1892 nvidia,suspend-mode = <1>; 1893 nvidia,cpu-pwr-good-time = <500>; 1894 nvidia,cpu-pwr-off-time = <300>; 1895 nvidia,core-pwr-good-time = <641 3845>; 1896 nvidia,core-pwr-off-time = <61036>; 1897 nvidia,core-power-req-active-high; 1898 nvidia,sys-clock-req-active-high; 1899 1900 /* Set power_off bit in ResetControl register of AS3722 PMIC */ 1901 i2c-thermtrip { 1902 nvidia,i2c-controller-id = <4>; 1903 nvidia,bus-addr = <0x40>; 1904 nvidia,reg-addr = <0x36>; 1905 nvidia,reg-data = <0x2>; 1906 }; 1907 }; 1908 1909 /* Apalis Serial ATA */ 1910 sata@70020000 { 1911 avdd-supply = <&vdd_1v05>; 1912 hvdd-supply = <®_3v3>; 1913 vddio-supply = <&vdd_1v05>; 1914 status = "okay"; 1915 }; 1916 1917 hda@70030000 { 1918 status = "okay"; 1919 }; 1920 1921 usb@70090000 { 1922 /* USBO1, USBO1 (SS), USBH2, USBH4 and USBH4 (SS) */ 1923 avddio-pex-supply = <&vdd_1v05>; 1924 avdd-pll-erefe-supply = <&avdd_1v05>; 1925 avdd-pll-utmip-supply = <&vddio_1v8>; 1926 avdd-usb-ss-pll-supply = <&vdd_1v05>; 1927 avdd-usb-supply = <®_3v3>; 1928 dvddio-pex-supply = <&vdd_1v05>; 1929 hvdd-usb-ss-pll-e-supply = <®_3v3>; 1930 hvdd-usb-ss-supply = <®_3v3>; 1931 status = "okay"; 1932 }; 1933 1934 padctl@7009f000 { 1935 pinctrl-0 = <&padctl_default>; 1936 pinctrl-names = "default"; 1937 1938 padctl_default: pinmux { 1939 usb3 { 1940 nvidia,lanes = "pcie-0", "pcie-1"; 1941 nvidia,function = "usb3"; 1942 nvidia,iddq = <0>; 1943 }; 1944 1945 pcie { 1946 nvidia,lanes = "pcie-2", "pcie-3", 1947 "pcie-4"; 1948 nvidia,function = "pcie"; 1949 nvidia,iddq = <0>; 1950 }; 1951 1952 sata { 1953 nvidia,lanes = "sata-0"; 1954 nvidia,function = "sata"; 1955 nvidia,iddq = <0>; 1956 }; 1957 }; 1958 }; 1959 1960 /* Apalis MMC1 */ 1961 sdhci@700b0000 { 1962 status = "okay"; 1963 /* MMC1_CD# */ 1964 cd-gpios = <&gpio TEGRA_GPIO(V, 3) GPIO_ACTIVE_LOW>; 1965 bus-width = <4>; 1966 vqmmc-supply = <&vddio_sdmmc1>; 1967 }; 1968 1969 /* Apalis SD1 */ 1970 sdhci@700b0400 { 1971 status = "okay"; 1972 /* SD1_CD# */ 1973 cd-gpios = <&gpio TEGRA_GPIO(V, 2) GPIO_ACTIVE_LOW>; 1974 bus-width = <4>; 1975 vqmmc-supply = <&vddio_sdmmc3>; 1976 }; 1977 1978 /* eMMC */ 1979 sdhci@700b0600 { 1980 status = "okay"; 1981 bus-width = <8>; 1982 non-removable; 1983 }; 1984 1985 /* CPU DFLL clock */ 1986 clock@70110000 { 1987 status = "okay"; 1988 vdd-cpu-supply = <&vdd_cpu>; 1989 nvidia,i2c-fs-rate = <400000>; 1990 }; 1991 1992 ahub@70300000 { 1993 i2s@70301200 { 1994 status = "okay"; 1995 }; 1996 }; 1997 1998 /* EHCI instance 0: USB1_DP/N -> USBO1_DP/N */ 1999 usb@7d000000 { 2000 status = "okay"; 2001 dr_mode = "otg"; 2002 }; 2003 2004 usb-phy@7d000000 { 2005 status = "okay"; 2006 vbus-supply = <®_usbo1_vbus>; 2007 }; 2008 2009 /* EHCI instance 1: USB2_DP/N -> USBH2_DP/N */ 2010 usb@7d004000 { 2011 status = "okay"; 2012 }; 2013 2014 usb-phy@7d004000 { 2015 status = "okay"; 2016 vbus-supply = <®_usbh_vbus>; 2017 }; 2018 2019 /* EHCI instance 2: USB3_DP/N -> USBH4_DP/N */ 2020 usb@7d008000 { 2021 status = "okay"; 2022 }; 2023 2024 usb-phy@7d008000 { 2025 status = "okay"; 2026 vbus-supply = <®_usbh_vbus>; 2027 }; 2028 2029 backlight: backlight { 2030 compatible = "pwm-backlight"; 2031 /* BKL1_PWM */ 2032 pwms = <&pwm 3 5000000>; 2033 brightness-levels = <255 231 223 207 191 159 127 0>; 2034 default-brightness-level = <6>; 2035 /* BKL1_ON */ 2036 enable-gpios = <&gpio TEGRA_GPIO(BB, 5) GPIO_ACTIVE_HIGH>; 2037 }; 2038 2039 clocks { 2040 compatible = "simple-bus"; 2041 #address-cells = <1>; 2042 #size-cells = <0>; 2043 2044 clk32k_in: clock@0 { 2045 compatible = "fixed-clock"; 2046 reg = <0>; 2047 #clock-cells = <0>; 2048 clock-frequency = <32768>; 2049 }; 2050 }; 2051 2052 cpus { 2053 cpu@0 { 2054 vdd-cpu-supply = <&vdd_cpu>; 2055 }; 2056 }; 2057 2058 gpio-keys { 2059 compatible = "gpio-keys"; 2060 2061 wakeup { 2062 label = "WAKE1_MICO"; 2063 gpios = <&gpio TEGRA_GPIO(DD, 3) GPIO_ACTIVE_LOW>; 2064 linux,code = <KEY_WAKEUP>; 2065 debounce-interval = <10>; 2066 wakeup-source; 2067 }; 2068 }; 2069 2070 reg_1v05_avdd_hdmi_pll: regulator-1v05-avdd-hdmi-pll { 2071 compatible = "regulator-fixed"; 2072 regulator-name = "+V1.05_AVDD_HDMI_PLL"; 2073 regulator-min-microvolt = <1050000>; 2074 regulator-max-microvolt = <1050000>; 2075 gpio = <&gpio TEGRA_GPIO(H, 7) GPIO_ACTIVE_LOW>; 2076 vin-supply = <&vdd_1v05>; 2077 }; 2078 2079 reg_3v3_mxm: regulator-3v3-mxm { 2080 compatible = "regulator-fixed"; 2081 regulator-name = "+V3.3_MXM"; 2082 regulator-min-microvolt = <3300000>; 2083 regulator-max-microvolt = <3300000>; 2084 regulator-always-on; 2085 regulator-boot-on; 2086 }; 2087 2088 reg_3v3: regulator-3v3 { 2089 compatible = "regulator-fixed"; 2090 regulator-name = "+V3.3"; 2091 regulator-min-microvolt = <3300000>; 2092 regulator-max-microvolt = <3300000>; 2093 regulator-always-on; 2094 regulator-boot-on; 2095 /* PWR_EN_+V3.3 */ 2096 gpio = <&pmic 2 GPIO_ACTIVE_HIGH>; 2097 enable-active-high; 2098 vin-supply = <®_3v3_mxm>; 2099 }; 2100 2101 reg_3v3_avdd_hdmi: regulator-3v3-avdd-hdmi { 2102 compatible = "regulator-fixed"; 2103 regulator-name = "+V3.3_AVDD_HDMI"; 2104 regulator-min-microvolt = <3300000>; 2105 regulator-max-microvolt = <3300000>; 2106 vin-supply = <&vdd_1v05>; 2107 }; 2108 2109 reg_5v0: regulator-5v0 { 2110 compatible = "regulator-fixed"; 2111 regulator-name = "5V_SW"; 2112 regulator-min-microvolt = <5000000>; 2113 regulator-max-microvolt = <5000000>; 2114 }; 2115 2116 /* USBO1_EN */ 2117 reg_usbo1_vbus: regulator-usbo1-vbus { 2118 compatible = "regulator-fixed"; 2119 regulator-name = "VCC_USBO1"; 2120 regulator-min-microvolt = <5000000>; 2121 regulator-max-microvolt = <5000000>; 2122 gpio = <&gpio TEGRA_GPIO(T, 5) GPIO_ACTIVE_HIGH>; 2123 enable-active-high; 2124 vin-supply = <®_5v0>; 2125 }; 2126 2127 /* USBH_EN */ 2128 reg_usbh_vbus: regulator-usbh-vbus { 2129 compatible = "regulator-fixed"; 2130 regulator-name = "VCC_USBH(2A|2C|2D|3|4)"; 2131 regulator-min-microvolt = <5000000>; 2132 regulator-max-microvolt = <5000000>; 2133 gpio = <&gpio TEGRA_GPIO(T, 6) GPIO_ACTIVE_HIGH>; 2134 enable-active-high; 2135 vin-supply = <®_5v0>; 2136 }; 2137 2138 sound { 2139 compatible = "toradex,tegra-audio-sgtl5000-apalis_tk1", 2140 "nvidia,tegra-audio-sgtl5000"; 2141 nvidia,model = "Toradex Apalis TK1"; 2142 nvidia,audio-routing = 2143 "Headphone Jack", "HP_OUT", 2144 "LINE_IN", "Line In Jack", 2145 "MIC_IN", "Mic Jack"; 2146 nvidia,i2s-controller = <&tegra_i2s2>; 2147 nvidia,audio-codec = <&sgtl5000>; 2148 clocks = <&tegra_car TEGRA124_CLK_PLL_A>, 2149 <&tegra_car TEGRA124_CLK_PLL_A_OUT0>, 2150 <&tegra_car TEGRA124_CLK_EXTERN1>; 2151 clock-names = "pll_a", "pll_a_out0", "mclk"; 2152 }; 2153 2154 thermal-zones { 2155 cpu { 2156 trips { 2157 trip@0 { 2158 temperature = <101000>; 2159 hysteresis = <0>; 2160 type = "critical"; 2161 }; 2162 }; 2163 2164 cooling-maps { 2165 /* 2166 * There are currently no cooling maps because 2167 * there are no cooling devices 2168 */ 2169 }; 2170 }; 2171 2172 mem { 2173 trips { 2174 trip@0 { 2175 temperature = <101000>; 2176 hysteresis = <0>; 2177 type = "critical"; 2178 }; 2179 }; 2180 2181 cooling-maps { 2182 /* 2183 * There are currently no cooling maps because 2184 * there are no cooling devices 2185 */ 2186 }; 2187 }; 2188 2189 gpu { 2190 trips { 2191 trip@0 { 2192 temperature = <101000>; 2193 hysteresis = <0>; 2194 type = "critical"; 2195 }; 2196 }; 2197 2198 cooling-maps { 2199 /* 2200 * There are currently no cooling maps because 2201 * there are no cooling devices 2202 */ 2203 }; 2204 }; 2205 }; 2206}; 2207