1/*
2 * ARM Ltd. Versatile Express
3 *
4 * Motherboard Express uATX
5 * V2M-P1
6 *
7 * HBI-0190D
8 *
9 * RS1 memory map ("ARM Cortex-A Series memory map" in the board's
10 * Technical Reference Manual)
11 *
12 * WARNING! The hardware described in this file is independent from the
13 * original variant (vexpress-v2m.dtsi), but there is a strong
14 * correspondence between the two configurations.
15 *
16 * TAKE CARE WHEN MAINTAINING THIS FILE TO PROPAGATE ANY RELEVANT
17 * CHANGES TO vexpress-v2m.dtsi!
18 */
19
20/ {
21	smb@8000000 {
22		motherboard {
23			model = "V2M-P1";
24			arm,hbi = <0x190>;
25			arm,vexpress,site = <0>;
26			arm,v2m-memory-map = "rs1";
27			compatible = "arm,vexpress,v2m-p1", "simple-bus";
28			#address-cells = <2>; /* SMB chipselect number and offset */
29			#size-cells = <1>;
30			#interrupt-cells = <1>;
31			ranges;
32
33			flash@0,00000000 {
34				compatible = "arm,vexpress-flash", "cfi-flash";
35				reg = <0 0x00000000 0x04000000>,
36				      <4 0x00000000 0x04000000>;
37				bank-width = <4>;
38			};
39
40			psram@1,00000000 {
41				compatible = "arm,vexpress-psram", "mtd-ram";
42				reg = <1 0x00000000 0x02000000>;
43				bank-width = <4>;
44			};
45
46			ethernet@2,02000000 {
47				compatible = "smsc,lan9118", "smsc,lan9115";
48				reg = <2 0x02000000 0x10000>;
49				interrupts = <15>;
50				phy-mode = "mii";
51				reg-io-width = <4>;
52				smsc,irq-active-high;
53				smsc,irq-push-pull;
54				vdd33a-supply = <&v2m_fixed_3v3>;
55				vddvario-supply = <&v2m_fixed_3v3>;
56			};
57
58			usb@2,03000000 {
59				compatible = "nxp,usb-isp1761";
60				reg = <2 0x03000000 0x20000>;
61				interrupts = <16>;
62				port1-otg;
63			};
64
65			iofpga@3,00000000 {
66				compatible = "simple-bus";
67				#address-cells = <1>;
68				#size-cells = <1>;
69				ranges = <0 3 0 0x200000>;
70
71				v2m_sysreg: sysreg@10000 {
72					compatible = "arm,vexpress-sysreg";
73					reg = <0x010000 0x1000>;
74					#address-cells = <1>;
75					#size-cells = <1>;
76					ranges = <0 0x10000 0x1000>;
77
78					v2m_led_gpios: gpio@8 {
79						compatible = "arm,vexpress-sysreg,sys_led";
80						reg = <0x008 4>;
81						gpio-controller;
82						#gpio-cells = <2>;
83					};
84
85					v2m_mmc_gpios: gpio@48 {
86						compatible = "arm,vexpress-sysreg,sys_mci";
87						reg = <0x048 4>;
88						gpio-controller;
89						#gpio-cells = <2>;
90					};
91
92					v2m_flash_gpios: gpio@4c {
93						compatible = "arm,vexpress-sysreg,sys_flash";
94						reg = <0x04c 4>;
95						gpio-controller;
96						#gpio-cells = <2>;
97					};
98				};
99
100				v2m_sysctl: sysctl@20000 {
101					compatible = "arm,sp810", "arm,primecell";
102					reg = <0x020000 0x1000>;
103					clocks = <&v2m_refclk32khz>, <&v2m_refclk1mhz>, <&smbclk>;
104					clock-names = "refclk", "timclk", "apb_pclk";
105					#clock-cells = <1>;
106					clock-output-names = "timerclken0", "timerclken1", "timerclken2", "timerclken3";
107					assigned-clocks = <&v2m_sysctl 0>, <&v2m_sysctl 1>, <&v2m_sysctl 3>, <&v2m_sysctl 3>;
108					assigned-clock-parents = <&v2m_refclk1mhz>, <&v2m_refclk1mhz>, <&v2m_refclk1mhz>, <&v2m_refclk1mhz>;
109				};
110
111				/* PCI-E I2C bus */
112				v2m_i2c_pcie: i2c@30000 {
113					compatible = "arm,versatile-i2c";
114					reg = <0x030000 0x1000>;
115
116					#address-cells = <1>;
117					#size-cells = <0>;
118
119					pcie-switch@60 {
120						compatible = "idt,89hpes32h8";
121						reg = <0x60>;
122					};
123				};
124
125				aaci@40000 {
126					compatible = "arm,pl041", "arm,primecell";
127					reg = <0x040000 0x1000>;
128					interrupts = <11>;
129					clocks = <&smbclk>;
130					clock-names = "apb_pclk";
131				};
132
133				mmci@50000 {
134					compatible = "arm,pl180", "arm,primecell";
135					reg = <0x050000 0x1000>;
136					interrupts = <9>, <10>;
137					cd-gpios = <&v2m_mmc_gpios 0 0>;
138					wp-gpios = <&v2m_mmc_gpios 1 0>;
139					max-frequency = <12000000>;
140					vmmc-supply = <&v2m_fixed_3v3>;
141					clocks = <&v2m_clk24mhz>, <&smbclk>;
142					clock-names = "mclk", "apb_pclk";
143				};
144
145				kmi@60000 {
146					compatible = "arm,pl050", "arm,primecell";
147					reg = <0x060000 0x1000>;
148					interrupts = <12>;
149					clocks = <&v2m_clk24mhz>, <&smbclk>;
150					clock-names = "KMIREFCLK", "apb_pclk";
151				};
152
153				kmi@70000 {
154					compatible = "arm,pl050", "arm,primecell";
155					reg = <0x070000 0x1000>;
156					interrupts = <13>;
157					clocks = <&v2m_clk24mhz>, <&smbclk>;
158					clock-names = "KMIREFCLK", "apb_pclk";
159				};
160
161				v2m_serial0: uart@90000 {
162					compatible = "arm,pl011", "arm,primecell";
163					reg = <0x090000 0x1000>;
164					interrupts = <5>;
165					clocks = <&v2m_oscclk2>, <&smbclk>;
166					clock-names = "uartclk", "apb_pclk";
167				};
168
169				v2m_serial1: uart@a0000 {
170					compatible = "arm,pl011", "arm,primecell";
171					reg = <0x0a0000 0x1000>;
172					interrupts = <6>;
173					clocks = <&v2m_oscclk2>, <&smbclk>;
174					clock-names = "uartclk", "apb_pclk";
175				};
176
177				v2m_serial2: uart@b0000 {
178					compatible = "arm,pl011", "arm,primecell";
179					reg = <0x0b0000 0x1000>;
180					interrupts = <7>;
181					clocks = <&v2m_oscclk2>, <&smbclk>;
182					clock-names = "uartclk", "apb_pclk";
183				};
184
185				v2m_serial3: uart@c0000 {
186					compatible = "arm,pl011", "arm,primecell";
187					reg = <0x0c0000 0x1000>;
188					interrupts = <8>;
189					clocks = <&v2m_oscclk2>, <&smbclk>;
190					clock-names = "uartclk", "apb_pclk";
191				};
192
193				wdt@f0000 {
194					compatible = "arm,sp805", "arm,primecell";
195					reg = <0x0f0000 0x1000>;
196					interrupts = <0>;
197					clocks = <&v2m_refclk32khz>, <&smbclk>;
198					clock-names = "wdogclk", "apb_pclk";
199				};
200
201				v2m_timer01: timer@110000 {
202					compatible = "arm,sp804", "arm,primecell";
203					reg = <0x110000 0x1000>;
204					interrupts = <2>;
205					clocks = <&v2m_sysctl 0>, <&v2m_sysctl 1>, <&smbclk>;
206					clock-names = "timclken1", "timclken2", "apb_pclk";
207				};
208
209				v2m_timer23: timer@120000 {
210					compatible = "arm,sp804", "arm,primecell";
211					reg = <0x120000 0x1000>;
212					interrupts = <3>;
213					clocks = <&v2m_sysctl 2>, <&v2m_sysctl 3>, <&smbclk>;
214					clock-names = "timclken1", "timclken2", "apb_pclk";
215				};
216
217				/* DVI I2C bus */
218				v2m_i2c_dvi: i2c@160000 {
219					compatible = "arm,versatile-i2c";
220					reg = <0x160000 0x1000>;
221					#address-cells = <1>;
222					#size-cells = <0>;
223
224					dvi-transmitter@39 {
225						compatible = "sil,sii9022-tpi", "sil,sii9022";
226						reg = <0x39>;
227
228						ports {
229							#address-cells = <1>;
230							#size-cells = <0>;
231
232							port@0 {
233								reg = <0>;
234								dvi_bridge_in: endpoint {
235									remote-endpoint = <&clcd_pads>;
236								};
237							};
238						};
239					};
240
241					dvi-transmitter@60 {
242						compatible = "sil,sii9022-cpi", "sil,sii9022";
243						reg = <0x60>;
244					};
245				};
246
247				rtc@170000 {
248					compatible = "arm,pl031", "arm,primecell";
249					reg = <0x170000 0x1000>;
250					interrupts = <4>;
251					clocks = <&smbclk>;
252					clock-names = "apb_pclk";
253				};
254
255				compact-flash@1a0000 {
256					compatible = "arm,vexpress-cf", "ata-generic";
257					reg = <0x1a0000 0x100
258					       0x1a0100 0xf00>;
259					reg-shift = <2>;
260				};
261
262				clcd@1f0000 {
263					compatible = "arm,pl111", "arm,primecell";
264					reg = <0x1f0000 0x1000>;
265					interrupt-names = "combined";
266					interrupts = <14>;
267					clocks = <&v2m_oscclk1>, <&smbclk>;
268					clock-names = "clcdclk", "apb_pclk";
269					/* 800x600 16bpp @36MHz works fine */
270					max-memory-bandwidth = <54000000>;
271					memory-region = <&vram>;
272
273					port {
274						clcd_pads: endpoint {
275							remote-endpoint = <&dvi_bridge_in>;
276							arm,pl11x,tft-r0g0b0-pads = <0 8 16>;
277						};
278					};
279				};
280			};
281
282			v2m_fixed_3v3: fixed-regulator-0 {
283				compatible = "regulator-fixed";
284				regulator-name = "3V3";
285				regulator-min-microvolt = <3300000>;
286				regulator-max-microvolt = <3300000>;
287				regulator-always-on;
288			};
289
290			v2m_clk24mhz: clk24mhz {
291				compatible = "fixed-clock";
292				#clock-cells = <0>;
293				clock-frequency = <24000000>;
294				clock-output-names = "v2m:clk24mhz";
295			};
296
297			v2m_refclk1mhz: refclk1mhz {
298				compatible = "fixed-clock";
299				#clock-cells = <0>;
300				clock-frequency = <1000000>;
301				clock-output-names = "v2m:refclk1mhz";
302			};
303
304			v2m_refclk32khz: refclk32khz {
305				compatible = "fixed-clock";
306				#clock-cells = <0>;
307				clock-frequency = <32768>;
308				clock-output-names = "v2m:refclk32khz";
309			};
310
311			leds {
312				compatible = "gpio-leds";
313
314				user1 {
315					label = "v2m:green:user1";
316					gpios = <&v2m_led_gpios 0 0>;
317					linux,default-trigger = "heartbeat";
318				};
319
320				user2 {
321					label = "v2m:green:user2";
322					gpios = <&v2m_led_gpios 1 0>;
323					linux,default-trigger = "mmc0";
324				};
325
326				user3 {
327					label = "v2m:green:user3";
328					gpios = <&v2m_led_gpios 2 0>;
329					linux,default-trigger = "cpu0";
330				};
331
332				user4 {
333					label = "v2m:green:user4";
334					gpios = <&v2m_led_gpios 3 0>;
335					linux,default-trigger = "cpu1";
336				};
337
338				user5 {
339					label = "v2m:green:user5";
340					gpios = <&v2m_led_gpios 4 0>;
341					linux,default-trigger = "cpu2";
342				};
343
344				user6 {
345					label = "v2m:green:user6";
346					gpios = <&v2m_led_gpios 5 0>;
347					linux,default-trigger = "cpu3";
348				};
349
350				user7 {
351					label = "v2m:green:user7";
352					gpios = <&v2m_led_gpios 6 0>;
353					linux,default-trigger = "cpu4";
354				};
355
356				user8 {
357					label = "v2m:green:user8";
358					gpios = <&v2m_led_gpios 7 0>;
359					linux,default-trigger = "cpu5";
360				};
361			};
362
363			mcc {
364				compatible = "arm,vexpress,config-bus";
365				arm,vexpress,config-bridge = <&v2m_sysreg>;
366
367				oscclk0 {
368					/* MCC static memory clock */
369					compatible = "arm,vexpress-osc";
370					arm,vexpress-sysreg,func = <1 0>;
371					freq-range = <25000000 60000000>;
372					#clock-cells = <0>;
373					clock-output-names = "v2m:oscclk0";
374				};
375
376				v2m_oscclk1: oscclk1 {
377					/* CLCD clock */
378					compatible = "arm,vexpress-osc";
379					arm,vexpress-sysreg,func = <1 1>;
380					freq-range = <23750000 65000000>;
381					#clock-cells = <0>;
382					clock-output-names = "v2m:oscclk1";
383				};
384
385				v2m_oscclk2: oscclk2 {
386					/* IO FPGA peripheral clock */
387					compatible = "arm,vexpress-osc";
388					arm,vexpress-sysreg,func = <1 2>;
389					freq-range = <24000000 24000000>;
390					#clock-cells = <0>;
391					clock-output-names = "v2m:oscclk2";
392				};
393
394				volt-vio {
395					/* Logic level voltage */
396					compatible = "arm,vexpress-volt";
397					arm,vexpress-sysreg,func = <2 0>;
398					regulator-name = "VIO";
399					regulator-always-on;
400					label = "VIO";
401				};
402
403				temp-mcc {
404					/* MCC internal operating temperature */
405					compatible = "arm,vexpress-temp";
406					arm,vexpress-sysreg,func = <4 0>;
407					label = "MCC";
408				};
409
410				reset {
411					compatible = "arm,vexpress-reset";
412					arm,vexpress-sysreg,func = <5 0>;
413				};
414
415				muxfpga {
416					compatible = "arm,vexpress-muxfpga";
417					arm,vexpress-sysreg,func = <7 0>;
418				};
419
420				shutdown {
421					compatible = "arm,vexpress-shutdown";
422					arm,vexpress-sysreg,func = <8 0>;
423				};
424
425				reboot {
426					compatible = "arm,vexpress-reboot";
427					arm,vexpress-sysreg,func = <9 0>;
428				};
429
430				dvimode {
431					compatible = "arm,vexpress-dvimode";
432					arm,vexpress-sysreg,func = <11 0>;
433				};
434			};
435		};
436	};
437};
438