1// SPDX-License-Identifier: GPL-2.0+ 2/* 3 * Xilinx Zynq 7000 DTSI 4 * Describes the hardware common to all Zynq 7000-based boards. 5 * 6 * Copyright (C) 2011 - 2015 Xilinx 7 */ 8 9/ { 10 #address-cells = <1>; 11 #size-cells = <1>; 12 compatible = "xlnx,zynq-7000"; 13 14 cpus { 15 #address-cells = <1>; 16 #size-cells = <0>; 17 18 cpu0: cpu@0 { 19 compatible = "arm,cortex-a9"; 20 device_type = "cpu"; 21 reg = <0>; 22 clocks = <&clkc 3>; 23 clock-latency = <1000>; 24 cpu0-supply = <®ulator_vccpint>; 25 operating-points = < 26 /* kHz uV */ 27 666667 1000000 28 333334 1000000 29 >; 30 }; 31 32 cpu1: cpu@1 { 33 compatible = "arm,cortex-a9"; 34 device_type = "cpu"; 35 reg = <1>; 36 clocks = <&clkc 3>; 37 }; 38 }; 39 40 fpga_full: fpga-full { 41 compatible = "fpga-region"; 42 fpga-mgr = <&devcfg>; 43 #address-cells = <1>; 44 #size-cells = <1>; 45 ranges; 46 }; 47 48 pmu@f8891000 { 49 compatible = "arm,cortex-a9-pmu"; 50 interrupts = <0 5 4>, <0 6 4>; 51 interrupt-parent = <&intc>; 52 reg = <0xf8891000 0x1000>, 53 <0xf8893000 0x1000>; 54 }; 55 56 regulator_vccpint: fixedregulator { 57 compatible = "regulator-fixed"; 58 regulator-name = "VCCPINT"; 59 regulator-min-microvolt = <1000000>; 60 regulator-max-microvolt = <1000000>; 61 regulator-boot-on; 62 regulator-always-on; 63 }; 64 65 replicator { 66 compatible = "arm,coresight-static-replicator"; 67 clocks = <&clkc 27>, <&clkc 46>, <&clkc 47>; 68 clock-names = "apb_pclk", "dbg_trc", "dbg_apb"; 69 70 out-ports { 71 #address-cells = <1>; 72 #size-cells = <0>; 73 74 /* replicator output ports */ 75 port@0 { 76 reg = <0>; 77 replicator_out_port0: endpoint { 78 remote-endpoint = <&tpiu_in_port>; 79 }; 80 }; 81 port@1 { 82 reg = <1>; 83 replicator_out_port1: endpoint { 84 remote-endpoint = <&etb_in_port>; 85 }; 86 }; 87 }; 88 in-ports { 89 /* replicator input port */ 90 port { 91 replicator_in_port0: endpoint { 92 remote-endpoint = <&funnel_out_port>; 93 }; 94 }; 95 }; 96 }; 97 98 amba: amba { 99 u-boot,dm-pre-reloc; 100 compatible = "simple-bus"; 101 #address-cells = <1>; 102 #size-cells = <1>; 103 interrupt-parent = <&intc>; 104 ranges; 105 106 adc: adc@f8007100 { 107 compatible = "xlnx,zynq-xadc-1.00.a"; 108 reg = <0xf8007100 0x20>; 109 interrupts = <0 7 4>; 110 interrupt-parent = <&intc>; 111 clocks = <&clkc 12>; 112 }; 113 114 can0: can@e0008000 { 115 compatible = "xlnx,zynq-can-1.0"; 116 status = "disabled"; 117 clocks = <&clkc 19>, <&clkc 36>; 118 clock-names = "can_clk", "pclk"; 119 reg = <0xe0008000 0x1000>; 120 interrupts = <0 28 4>; 121 interrupt-parent = <&intc>; 122 tx-fifo-depth = <0x40>; 123 rx-fifo-depth = <0x40>; 124 }; 125 126 can1: can@e0009000 { 127 compatible = "xlnx,zynq-can-1.0"; 128 status = "disabled"; 129 clocks = <&clkc 20>, <&clkc 37>; 130 clock-names = "can_clk", "pclk"; 131 reg = <0xe0009000 0x1000>; 132 interrupts = <0 51 4>; 133 interrupt-parent = <&intc>; 134 tx-fifo-depth = <0x40>; 135 rx-fifo-depth = <0x40>; 136 }; 137 138 gpio0: gpio@e000a000 { 139 compatible = "xlnx,zynq-gpio-1.0"; 140 #gpio-cells = <2>; 141 clocks = <&clkc 42>; 142 gpio-controller; 143 interrupt-controller; 144 #interrupt-cells = <2>; 145 interrupt-parent = <&intc>; 146 interrupts = <0 20 4>; 147 reg = <0xe000a000 0x1000>; 148 }; 149 150 i2c0: i2c@e0004000 { 151 compatible = "cdns,i2c-r1p10"; 152 status = "disabled"; 153 clocks = <&clkc 38>; 154 interrupt-parent = <&intc>; 155 interrupts = <0 25 4>; 156 reg = <0xe0004000 0x1000>; 157 #address-cells = <1>; 158 #size-cells = <0>; 159 }; 160 161 i2c1: i2c@e0005000 { 162 compatible = "cdns,i2c-r1p10"; 163 status = "disabled"; 164 clocks = <&clkc 39>; 165 interrupt-parent = <&intc>; 166 interrupts = <0 48 4>; 167 reg = <0xe0005000 0x1000>; 168 #address-cells = <1>; 169 #size-cells = <0>; 170 }; 171 172 intc: interrupt-controller@f8f01000 { 173 compatible = "arm,cortex-a9-gic"; 174 #interrupt-cells = <3>; 175 interrupt-controller; 176 reg = <0xF8F01000 0x1000>, 177 <0xF8F00100 0x100>; 178 }; 179 180 L2: cache-controller@f8f02000 { 181 compatible = "arm,pl310-cache"; 182 reg = <0xF8F02000 0x1000>; 183 interrupts = <0 2 4>; 184 arm,data-latency = <3 2 2>; 185 arm,tag-latency = <2 2 2>; 186 cache-unified; 187 cache-level = <2>; 188 }; 189 190 mc: memory-controller@f8006000 { 191 compatible = "xlnx,zynq-ddrc-a05"; 192 reg = <0xf8006000 0x1000>; 193 }; 194 195 uart0: serial@e0000000 { 196 compatible = "xlnx,xuartps", "cdns,uart-r1p8"; 197 status = "disabled"; 198 clocks = <&clkc 23>, <&clkc 40>; 199 clock-names = "uart_clk", "pclk"; 200 reg = <0xE0000000 0x1000>; 201 interrupts = <0 27 4>; 202 }; 203 204 uart1: serial@e0001000 { 205 compatible = "xlnx,xuartps", "cdns,uart-r1p8"; 206 status = "disabled"; 207 clocks = <&clkc 24>, <&clkc 41>; 208 clock-names = "uart_clk", "pclk"; 209 reg = <0xE0001000 0x1000>; 210 interrupts = <0 50 4>; 211 }; 212 213 spi0: spi@e0006000 { 214 compatible = "xlnx,zynq-spi-r1p6"; 215 reg = <0xe0006000 0x1000>; 216 status = "disabled"; 217 interrupt-parent = <&intc>; 218 interrupts = <0 26 4>; 219 clocks = <&clkc 25>, <&clkc 34>; 220 clock-names = "ref_clk", "pclk"; 221 #address-cells = <1>; 222 #size-cells = <0>; 223 }; 224 225 spi1: spi@e0007000 { 226 compatible = "xlnx,zynq-spi-r1p6"; 227 reg = <0xe0007000 0x1000>; 228 status = "disabled"; 229 interrupt-parent = <&intc>; 230 interrupts = <0 49 4>; 231 clocks = <&clkc 26>, <&clkc 35>; 232 clock-names = "ref_clk", "pclk"; 233 #address-cells = <1>; 234 #size-cells = <0>; 235 }; 236 237 qspi: spi@e000d000 { 238 clock-names = "ref_clk", "pclk"; 239 clocks = <&clkc 10>, <&clkc 43>; 240 compatible = "xlnx,zynq-qspi-1.0"; 241 status = "disabled"; 242 interrupt-parent = <&intc>; 243 interrupts = <0 19 4>; 244 reg = <0xe000d000 0x1000>; 245 #address-cells = <1>; 246 #size-cells = <0>; 247 }; 248 249 smcc: memory-controller@e000e000 { 250 #address-cells = <1>; 251 #size-cells = <1>; 252 status = "disabled"; 253 clock-names = "memclk", "apb_pclk"; 254 clocks = <&clkc 11>, <&clkc 44>; 255 compatible = "arm,pl353-smc-r2p1", "arm,primecell"; 256 interrupt-parent = <&intc>; 257 interrupts = <0 18 4>; 258 ranges ; 259 reg = <0xe000e000 0x1000>; 260 nand0: flash@e1000000 { 261 status = "disabled"; 262 compatible = "arm,pl353-nand-r2p1"; 263 reg = <0xe1000000 0x1000000>; 264 #address-cells = <1>; 265 #size-cells = <1>; 266 }; 267 nor0: flash@e2000000 { 268 status = "disabled"; 269 compatible = "cfi-flash"; 270 reg = <0xe2000000 0x2000000>; 271 #address-cells = <1>; 272 #size-cells = <1>; 273 }; 274 }; 275 276 gem0: ethernet@e000b000 { 277 compatible = "cdns,zynq-gem", "cdns,gem"; 278 reg = <0xe000b000 0x1000>; 279 status = "disabled"; 280 interrupts = <0 22 4>; 281 clocks = <&clkc 30>, <&clkc 30>, <&clkc 13>; 282 clock-names = "pclk", "hclk", "tx_clk"; 283 #address-cells = <1>; 284 #size-cells = <0>; 285 }; 286 287 gem1: ethernet@e000c000 { 288 compatible = "cdns,zynq-gem", "cdns,gem"; 289 reg = <0xe000c000 0x1000>; 290 status = "disabled"; 291 interrupts = <0 45 4>; 292 clocks = <&clkc 31>, <&clkc 31>, <&clkc 14>; 293 clock-names = "pclk", "hclk", "tx_clk"; 294 #address-cells = <1>; 295 #size-cells = <0>; 296 }; 297 298 sdhci0: mmc@e0100000 { 299 compatible = "arasan,sdhci-8.9a"; 300 status = "disabled"; 301 clock-names = "clk_xin", "clk_ahb"; 302 clocks = <&clkc 21>, <&clkc 32>; 303 interrupt-parent = <&intc>; 304 interrupts = <0 24 4>; 305 reg = <0xe0100000 0x1000>; 306 }; 307 308 sdhci1: mmc@e0101000 { 309 compatible = "arasan,sdhci-8.9a"; 310 status = "disabled"; 311 clock-names = "clk_xin", "clk_ahb"; 312 clocks = <&clkc 22>, <&clkc 33>; 313 interrupt-parent = <&intc>; 314 interrupts = <0 47 4>; 315 reg = <0xe0101000 0x1000>; 316 }; 317 318 slcr: slcr@f8000000 { 319 u-boot,dm-pre-reloc; 320 #address-cells = <1>; 321 #size-cells = <1>; 322 compatible = "xlnx,zynq-slcr", "syscon", "simple-mfd"; 323 reg = <0xF8000000 0x1000>; 324 ranges; 325 clkc: clkc@100 { 326 u-boot,dm-pre-reloc; 327 #clock-cells = <1>; 328 compatible = "xlnx,ps7-clkc"; 329 fclk-enable = <0>; 330 clock-output-names = "armpll", "ddrpll", "iopll", "cpu_6or4x", 331 "cpu_3or2x", "cpu_2x", "cpu_1x", "ddr2x", "ddr3x", 332 "dci", "lqspi", "smc", "pcap", "gem0", "gem1", 333 "fclk0", "fclk1", "fclk2", "fclk3", "can0", "can1", 334 "sdio0", "sdio1", "uart0", "uart1", "spi0", "spi1", 335 "dma", "usb0_aper", "usb1_aper", "gem0_aper", 336 "gem1_aper", "sdio0_aper", "sdio1_aper", 337 "spi0_aper", "spi1_aper", "can0_aper", "can1_aper", 338 "i2c0_aper", "i2c1_aper", "uart0_aper", "uart1_aper", 339 "gpio_aper", "lqspi_aper", "smc_aper", "swdt", 340 "dbg_trc", "dbg_apb"; 341 reg = <0x100 0x100>; 342 }; 343 344 rstc: rstc@200 { 345 compatible = "xlnx,zynq-reset"; 346 reg = <0x200 0x48>; 347 #reset-cells = <1>; 348 syscon = <&slcr>; 349 }; 350 351 pinctrl0: pinctrl@700 { 352 compatible = "xlnx,pinctrl-zynq"; 353 reg = <0x700 0x200>; 354 syscon = <&slcr>; 355 }; 356 }; 357 358 dmac_s: dmac@f8003000 { 359 compatible = "arm,pl330", "arm,primecell"; 360 reg = <0xf8003000 0x1000>; 361 interrupt-parent = <&intc>; 362 interrupt-names = "abort", "dma0", "dma1", "dma2", "dma3", 363 "dma4", "dma5", "dma6", "dma7"; 364 interrupts = <0 13 4>, 365 <0 14 4>, <0 15 4>, 366 <0 16 4>, <0 17 4>, 367 <0 40 4>, <0 41 4>, 368 <0 42 4>, <0 43 4>; 369 #dma-cells = <1>; 370 #dma-channels = <8>; 371 #dma-requests = <4>; 372 clocks = <&clkc 27>; 373 clock-names = "apb_pclk"; 374 }; 375 376 devcfg: devcfg@f8007000 { 377 compatible = "xlnx,zynq-devcfg-1.0"; 378 interrupt-parent = <&intc>; 379 interrupts = <0 8 4>; 380 reg = <0xf8007000 0x100>; 381 clocks = <&clkc 12>, <&clkc 15>, <&clkc 16>, <&clkc 17>, <&clkc 18>; 382 clock-names = "ref_clk", "fclk0", "fclk1", "fclk2", "fclk3"; 383 syscon = <&slcr>; 384 }; 385 386 efuse: efuse@f800d000 { 387 compatible = "xlnx,zynq-efuse"; 388 reg = <0xf800d000 0x20>; 389 }; 390 391 global_timer: timer@f8f00200 { 392 compatible = "arm,cortex-a9-global-timer"; 393 reg = <0xf8f00200 0x20>; 394 interrupts = <1 11 0x301>; 395 interrupt-parent = <&intc>; 396 clocks = <&clkc 4>; 397 }; 398 399 ttc0: timer@f8001000 { 400 interrupt-parent = <&intc>; 401 interrupts = <0 10 4>, <0 11 4>, <0 12 4>; 402 compatible = "cdns,ttc"; 403 clocks = <&clkc 6>; 404 reg = <0xF8001000 0x1000>; 405 }; 406 407 ttc1: timer@f8002000 { 408 interrupt-parent = <&intc>; 409 interrupts = <0 37 4>, <0 38 4>, <0 39 4>; 410 compatible = "cdns,ttc"; 411 clocks = <&clkc 6>; 412 reg = <0xF8002000 0x1000>; 413 }; 414 415 scutimer: timer@f8f00600 { 416 interrupt-parent = <&intc>; 417 interrupts = <1 13 0x301>; 418 compatible = "arm,cortex-a9-twd-timer"; 419 reg = <0xf8f00600 0x20>; 420 clocks = <&clkc 4>; 421 }; 422 423 usb0: usb@e0002000 { 424 compatible = "xlnx,zynq-usb-2.20a", "chipidea,usb2"; 425 status = "disabled"; 426 clocks = <&clkc 28>; 427 interrupt-parent = <&intc>; 428 interrupts = <0 21 4>; 429 reg = <0xe0002000 0x1000>; 430 phy_type = "ulpi"; 431 }; 432 433 usb1: usb@e0003000 { 434 compatible = "xlnx,zynq-usb-2.20a", "chipidea,usb2"; 435 status = "disabled"; 436 clocks = <&clkc 29>; 437 interrupt-parent = <&intc>; 438 interrupts = <0 44 4>; 439 reg = <0xe0003000 0x1000>; 440 phy_type = "ulpi"; 441 }; 442 443 watchdog0: watchdog@f8005000 { 444 clocks = <&clkc 45>; 445 compatible = "cdns,wdt-r1p2"; 446 interrupt-parent = <&intc>; 447 interrupts = <0 9 1>; 448 reg = <0xf8005000 0x1000>; 449 timeout-sec = <10>; 450 }; 451 452 etb@f8801000 { 453 compatible = "arm,coresight-etb10", "arm,primecell"; 454 reg = <0xf8801000 0x1000>; 455 clocks = <&clkc 27>, <&clkc 46>, <&clkc 47>; 456 clock-names = "apb_pclk", "dbg_trc", "dbg_apb"; 457 in-ports { 458 port { 459 etb_in_port: endpoint { 460 remote-endpoint = <&replicator_out_port1>; 461 }; 462 }; 463 }; 464 }; 465 466 tpiu@f8803000 { 467 compatible = "arm,coresight-tpiu", "arm,primecell"; 468 reg = <0xf8803000 0x1000>; 469 clocks = <&clkc 27>, <&clkc 46>, <&clkc 47>; 470 clock-names = "apb_pclk", "dbg_trc", "dbg_apb"; 471 in-ports { 472 port { 473 tpiu_in_port: endpoint { 474 remote-endpoint = <&replicator_out_port0>; 475 }; 476 }; 477 }; 478 }; 479 480 funnel@f8804000 { 481 compatible = "arm,coresight-static-funnel", "arm,primecell"; 482 reg = <0xf8804000 0x1000>; 483 clocks = <&clkc 27>, <&clkc 46>, <&clkc 47>; 484 clock-names = "apb_pclk", "dbg_trc", "dbg_apb"; 485 486 /* funnel output ports */ 487 out-ports { 488 port { 489 funnel_out_port: endpoint { 490 remote-endpoint = 491 <&replicator_in_port0>; 492 }; 493 }; 494 }; 495 496 in-ports { 497 #address-cells = <1>; 498 #size-cells = <0>; 499 500 /* funnel input ports */ 501 port@0 { 502 reg = <0>; 503 funnel0_in_port0: endpoint { 504 remote-endpoint = <&ptm0_out_port>; 505 }; 506 }; 507 508 port@1 { 509 reg = <1>; 510 funnel0_in_port1: endpoint { 511 remote-endpoint = <&ptm1_out_port>; 512 }; 513 }; 514 515 port@2 { 516 reg = <2>; 517 funnel0_in_port2: endpoint { 518 }; 519 }; 520 /* The other input ports are not connect to anything */ 521 }; 522 }; 523 524 ptm@f889c000 { 525 compatible = "arm,coresight-etm3x", "arm,primecell"; 526 reg = <0xf889c000 0x1000>; 527 clocks = <&clkc 27>, <&clkc 46>, <&clkc 47>; 528 clock-names = "apb_pclk", "dbg_trc", "dbg_apb"; 529 cpu = <&cpu0>; 530 out-ports { 531 port { 532 ptm0_out_port: endpoint { 533 remote-endpoint = <&funnel0_in_port0>; 534 }; 535 }; 536 }; 537 }; 538 539 ptm@f889d000 { 540 compatible = "arm,coresight-etm3x", "arm,primecell"; 541 reg = <0xf889d000 0x1000>; 542 clocks = <&clkc 27>, <&clkc 46>, <&clkc 47>; 543 clock-names = "apb_pclk", "dbg_trc", "dbg_apb"; 544 cpu = <&cpu1>; 545 out-ports { 546 port { 547 ptm1_out_port: endpoint { 548 remote-endpoint = <&funnel0_in_port1>; 549 }; 550 }; 551 }; 552 }; 553 }; 554}; 555