1// SPDX-License-Identifier: GPL-2.0 2/* 3 * dts file for Xilinx Versal a2197 RevA System Controller 4 * 5 * (C) Copyright 2019, Xilinx, Inc. 6 * 7 * Michal Simek <michal.simek@xilinx.com> 8 */ 9/dts-v1/; 10 11#include "zynqmp.dtsi" 12#include "zynqmp-clk-ccf.dtsi" 13#include <dt-bindings/gpio/gpio.h> 14 15/ { 16 model = "Versal System Controller on a2197 Memory Char board RevA"; 17 compatible = "xlnx,zynqmp-m-a2197-02-revA", "xlnx,zynqmp-a2197-revA", 18 "xlnx,zynqmp-a2197", "xlnx,zynqmp"; 19 20 aliases { 21 ethernet0 = &gem0; 22 gpio0 = &gpio; 23 i2c0 = &i2c0; 24 i2c1 = &i2c1; 25 mmc0 = &sdhci0; 26 mmc1 = &sdhci1; 27 rtc0 = &rtc; 28 serial0 = &uart0; 29 serial1 = &uart1; 30 serial2 = &dcc; 31 usb0 = &usb0; 32 usb1 = &usb1; 33 spi0 = &qspi; 34 }; 35 36 chosen { 37 bootargs = "earlycon"; 38 stdout-path = "serial0:115200n8"; 39 xlnx,eeprom = <&eeprom>; 40 }; 41 42 memory@0 { 43 device_type = "memory"; 44 reg = <0x0 0x0 0x0 0x80000000>; /* FIXME don't know how big memory is there */ 45 }; 46 47 ina226-vcc-aux { 48 compatible = "iio-hwmon"; 49 io-channels = <&vcc_aux 0>, <&vcc_aux 1>, <&vcc_aux 2>, <&vcc_aux 3>; 50 }; 51 ina226-vcc-ram { 52 compatible = "iio-hwmon"; 53 io-channels = <&vcc_ram 0>, <&vcc_ram 1>, <&vcc_ram 2>, <&vcc_ram 3>; 54 }; 55 ina226-vcc1v1-lp4 { 56 compatible = "iio-hwmon"; 57 io-channels = <&vcc1v1_lp4 0>, <&vcc1v1_lp4 1>, <&vcc1v1_lp4 2>, <&vcc1v1_lp4 3>; 58 }; 59 ina226-vcc1v2-lp4 { 60 compatible = "iio-hwmon"; 61 io-channels = <&vcc1v2_lp4 0>, <&vcc1v2_lp4 1>, <&vcc1v2_lp4 2>, <&vcc1v2_lp4 3>; 62 }; 63 ina226-vdd1-1v8-lp4 { 64 compatible = "iio-hwmon"; 65 io-channels = <&vdd1_1v8_lp4 0>, <&vdd1_1v8_lp4 1>, <&vdd1_1v8_lp4 2>, <&vdd1_1v8_lp4 3>; 66 }; 67}; 68 69&qspi { 70 status = "okay"; 71 is-dual = <1>; 72 flash@0 { 73 compatible = "m25p80", "jedec,spi-nor"; /* 32MB */ 74 #address-cells = <1>; 75 #size-cells = <1>; 76 reg = <0x0>; 77 spi-tx-bus-width = <1>; 78 spi-rx-bus-width = <4>; 79 spi-max-frequency = <108000000>; 80 }; 81}; 82 83&sdhci0 { /* emmc MIO 13-23 - with some settings 16GB */ 84 status = "okay"; 85 non-removable; 86 disable-wp; 87 bus-width = <8>; 88 xlnx,mio-bank = <0>; /* FIXME tap delay */ 89}; 90 91&uart0 { /* uart0 MIO38-39 */ 92 status = "okay"; 93 u-boot,dm-pre-reloc; 94}; 95 96&uart1 { /* uart1 MIO40-41 */ 97 status = "okay"; 98 u-boot,dm-pre-reloc; 99}; 100 101&sdhci1 { /* sd1 MIO45-51 cd in place */ 102 status = "disable"; 103 no-1-8-v; 104 disable-wp; 105 xlnx,mio-bank = <1>; 106}; 107 108&gem0 { 109 status = "okay"; 110 phy-handle = <&phy0>; 111 phy-mode = "sgmii"; 112 phy-reset-gpios = <&gpio 142 GPIO_ACTIVE_LOW>; 113 phy0: ethernet-phy@0 { /* marwell m88e1512 - SGMII */ 114 reg = <0>; 115 }; 116}; 117 118&gpio { 119 status = "okay"; 120 gpio-line-names = "SCLK_OUT", "MISO_MO1", "MO2", "MO3", "MOSI_MIO0", /* 0 - 4 */ 121 "N_SS_OUT", "", "SYS_CTRL0", "SYS_CTRL1", "SYS_CTRL2", /* 5 - 9 */ 122 "SYS_CTRL3", "SYS_CTRL4", "SYS_CTRL5", "EMMC_DAT0", "EMMC_DAT1", /* 10 - 14 */ 123 "EMMC_DAT2", "EMMC_DAT3", "EMMC_DAT4", "EMMC_DAT5", "EMMC_DAT6", /* 15 - 19 */ 124 "EMMC_DAT7", "EMMC_CMD", "EMMC_CLK", "EMMC_RST_B", "", /* 20 - 24 */ 125 "", "RXD0_IN", "TXD0_OUT", "TXD1_OUT", "RXD1_IN", /* 25 - 29 */ 126 "", "", "", "", "LP_I2C0_PMC_SCL", /* 30 - 34 */ 127 "LP_I2C0_PMC_SDA", "LP_I2C1_SCL", "LP_I2C1_SDA", "UART0_RXD_IN", "UART0_TXD_OUT", /* 35 - 39 */ 128 "UART1_TXD_OUT", "UART1_RXD_IN", "ETH_RESET_B", "", "", /* 40 - 44 */ 129 "SD1_CD_B", "SD1_DATA0", "SD1_DATA1", "SD1_DATA2", "SD1_DATA3", /* 45 - 49 */ 130 "SD1_CMD", "SD1_CLK", "USB0_CLK", "USB0_DIR", "USB0_DATA2", /* 50 - 54 */ 131 "USB0_NXT", "USB0_DATA0", "USB0_DATA1", "USB0_STP", "USB0_DATA3", /* 55 - 59 */ 132 "USB0_DATA4", "USB0_DATA5", "USB0_DATA6", "USB0_DATA7", "USB1_CLK", /* 60 - 64 */ 133 "USB1_DIR", "USB1_DATA2", "USB1_NXT", "USB1_DATA0", "USB1_DATA1", /* 65 - 69 */ 134 "USB1_STP", "USB1_DATA3", "USB1_DATA4", "USB1_DATA5", "USB1_DATA6", /* 70 - 74 */ 135 "USB1_DATA7", "ETH_MDC", "ETH_MDIO", /* 75 - 77, MIO end and EMIO start */ 136 "", "", "", "", "", /* 78 - 79 */ 137 "", "", "", "", "", /* 80 - 84 */ 138 "", "", "", "", "", /* 85 -89 */ 139 "", "", "", "", "", /* 90 - 94 */ 140 "", "", "", "", "", /* 95 - 99 */ 141 "", "", "", "", "", /* 100 - 104 */ 142 "", "", "", "", "", /* 105 - 109 */ 143 "", "", "", "", "", /* 110 - 114 */ 144 "", "", "", "", "", /* 115 - 119 */ 145 "", "", "", "", "", /* 120 - 124 */ 146 "", "", "", "", "", /* 125 - 129 */ 147 "", "", "", "", "", /* 130 - 134 */ 148 "", "", "", "", "", /* 135 - 139 */ 149 "", "", "", "", "", /* 140 - 144 */ 150 "", "", "", "", "", /* 145 - 149 */ 151 "", "", "", "", "", /* 150 - 154 */ 152 "", "", "", "", "", /* 155 - 159 */ 153 "", "", "", "", "", /* 160 - 164 */ 154 "", "", "", "", "", /* 165 - 169 */ 155 "", "", "", ""; /* 170 - 174 */ 156}; 157 158&i2c0 { /* MIO 34-35 - can't stay here */ 159 status = "okay"; 160 clock-frequency = <400000>; 161 i2c-mux@74 { /* u46 */ 162 compatible = "nxp,pca9548"; 163 #address-cells = <1>; 164 #size-cells = <0>; 165 reg = <0x74>; 166 /* FIXME reset connected to SYSCTRL_IIC_MUX0_RESET */ 167 i2c@0 { /* PMBUS must be enabled via SW21 */ 168 #address-cells = <1>; 169 #size-cells = <0>; 170 reg = <0>; 171 reg_vcc1v2_lp4: tps544@15 { /* u97 */ 172 compatible = "ti,tps544b25"; 173 reg = <0x15>; 174 }; 175 reg_vcc1v1_lp4: tps544@16 { /* u95 */ 176 compatible = "ti,tps544b25"; 177 reg = <0x16>; 178 }; 179 reg_vdd1_1v8_lp4: tps544@17 { /* u99 */ 180 compatible = "ti,tps544b25"; 181 reg = <0x17>; 182 }; 183 /* UTIL_PMBUS connection */ 184 reg_vcc1v8: tps544@13 { /* u92 */ 185 compatible = "ti,tps544b25"; 186 reg = <0x13>; 187 }; 188 reg_vcc3v3: tps544@14 { /* u93 */ 189 compatible = "ti,tps544b25"; 190 reg = <0x14>; 191 }; 192 reg_vcc5v0: tps544@1e { /* u94 */ 193 compatible = "ti,tps544b25"; 194 reg = <0x1e>; 195 }; 196 reg_vpp_2v5_ddr4: tps544@1x { /* u3007 */ 197 compatible = "ti,tps544b25"; 198 reg = <0x17>; /* FIXME wrong in schematics */ 199 }; 200 }; 201 i2c@1 { /* PMBUS_INA226 */ 202 #address-cells = <1>; 203 #size-cells = <0>; 204 reg = <1>; 205 vcc_aux: ina226@42 { /* u86 */ 206 compatible = "ti,ina226"; 207 #io-channel-cells = <1>; 208 label = "ina226-vcc-aux"; 209 reg = <0x42>; 210 shunt-resistor = <5000>; 211 }; 212 vcc_ram: ina226@43 { /* u81 */ 213 compatible = "ti,ina226"; 214 #io-channel-cells = <1>; 215 label = "ina226-vcc-ram"; 216 reg = <0x43>; 217 shunt-resistor = <5000>; 218 }; 219 vcc1v1_lp4: ina226@46 { /* u96 */ 220 compatible = "ti,ina226"; 221 #io-channel-cells = <1>; 222 label = "ina226-vcc1v1-lp4"; 223 reg = <0x46>; 224 shunt-resistor = <5000>; 225 }; 226 vcc1v2_lp4: ina226@47 { /* u98 */ 227 compatible = "ti,ina226"; 228 #io-channel-cells = <1>; 229 label = "ina226-vcc1v2-lp4"; 230 reg = <0x47>; 231 shunt-resistor = <5000>; 232 }; 233 vdd1_1v8_lp4: ina226@48 { /* u100 */ 234 compatible = "ti,ina226"; 235 #io-channel-cells = <1>; 236 label = "ina226-vdd1-1v8-lp4"; 237 reg = <0x48>; 238 shunt-resistor = <5000>; 239 }; 240 }; 241 i2c@2 { /* PMBUS1 */ 242 #address-cells = <1>; 243 #size-cells = <0>; 244 reg = <2>; 245 reg_vccint: tps53681@c0 { /* u69 */ 246 compatible = "ti,tps53681", "ti,tps53679"; 247 reg = <0xc0>; 248 }; 249 reg_vcc_pmc: tps544@7 { /* u80 */ 250 compatible = "ti,tps544b25"; 251 reg = <0x7>; 252 }; 253 reg_vcc_ram: tps544@8 { /* u82 */ 254 compatible = "ti,tps544b25"; 255 reg = <0x8>; 256 }; 257 reg_vcc_pslp: tps544@9 { /* u83 */ 258 compatible = "ti,tps544b25"; 259 reg = <0x9>; 260 }; 261 reg_vcc_psfp: tps544@a { /* u84 */ 262 compatible = "ti,tps544b25"; 263 reg = <0xa>; 264 }; 265 reg_vccaux: tps544@d { /* u85 */ 266 compatible = "ti,tps544b25"; 267 reg = <0xd>; 268 }; 269 reg_vccaux_pmc: tps544@e { /* u87 */ 270 compatible = "ti,tps544b25"; 271 reg = <0xe>; 272 }; 273 reg_vcco_500: tps544@f { /* u88 */ 274 compatible = "ti,tps544b25"; 275 reg = <0xf>; 276 }; 277 reg_vcco_501: tps544@10 { /* u89 */ 278 compatible = "ti,tps544b25"; 279 reg = <0x10>; 280 }; 281 reg_vcco_502: tps544@11 { /* u90 */ 282 compatible = "ti,tps544b25"; 283 reg = <0x11>; 284 }; 285 reg_vcco_503: tps544@12 { /* u91 */ 286 compatible = "ti,tps544b25"; 287 reg = <0x12>; 288 }; 289 }; 290 i2c@3 { /* MEM PMBUS - FIXME bug in schematics */ 291 #address-cells = <1>; 292 #size-cells = <0>; 293 /* reg = <3>; */ 294 }; 295 i2c@4 { /* LP_I2C_SM */ 296 #address-cells = <1>; 297 #size-cells = <0>; 298 reg = <4>; 299 /* connected to U20G */ 300 }; 301 i2c@5 { /* C0_DDR4_RDIMM */ 302 #address-cells = <1>; 303 #size-cells = <0>; 304 reg = <5>; 305 }; 306 i2c@6 { /* C2_DDR5_RDIMM */ 307 #address-cells = <1>; 308 #size-cells = <0>; 309 reg = <6>; 310 }; 311 i2c@7 { /* C3_DDR4_UDIMM */ 312 #address-cells = <1>; 313 #size-cells = <0>; 314 reg = <7>; 315 }; 316 }; 317}; 318 319/* TODO sysctrl via J239 */ 320/* TODO samtec J212G/H via J242 */ 321/* TODO teensy via U30 PCA9543A bus 1 */ 322&i2c1 { /* i2c1 MIO 36-37 */ 323 status = "okay"; 324 clock-frequency = <400000>; 325 326 /* Must be enabled via J242 */ 327 eeprom_versal: eeprom@51 { /* x-prc-01-revA u116, x-prc-02-revA u12 */ 328 compatible = "atmel,24c02"; 329 reg = <0x51>; 330 }; 331 332 i2c-mux@74 { /* u47 */ 333 compatible = "nxp,pca9548"; 334 #address-cells = <1>; 335 #size-cells = <0>; 336 reg = <0x74>; 337 /* FIXME reset connected to SYSCTRL_IIC_MUX1_RESET */ 338 dc_i2c: i2c@0 { /* DC_I2C */ 339 #address-cells = <1>; 340 #size-cells = <0>; 341 reg = <0>; 342 /* Use for storing information about SC board */ 343 eeprom: eeprom@54 { /* u51 - m24128 16kB FIXME addr */ 344 compatible = "atmel,24c08"; 345 reg = <0x54>; 346 }; 347 si570_ref_clk: clock-generator@5d { /* u26 */ 348 #clock-cells = <0>; 349 compatible = "silabs,si570"; 350 reg = <0x5d>; /* FIXME addr */ 351 temperature-stability = <50>; 352 factory-fout = <156250000>; /* FIXME every chip can be different */ 353 clock-frequency = <33333333>; 354 clock-output-names = "REF_CLK"; /* FIXME */ 355 }; 356 /* Connection via Samtec U20D */ 357 /* Use for storing information about X-PRC card */ 358 x_prc_eeprom: eeprom@52 { /* x-prc-01-revA u120, x-prc-02-revA u16 */ 359 compatible = "atmel,24c02"; 360 reg = <0x52>; 361 }; 362 363 /* Use for setting up certain features on X-PRC card */ 364 x_prc_tca9534: gpio@22 { /* x-prc-01-revA u121, x-prc-02-revA u17 */ 365 compatible = "nxp,pca9534"; 366 reg = <0x22>; 367 gpio-controller; /* IRQ not connected */ 368 #gpio-cells = <2>; 369 gpio-line-names = "sw4_1", "sw4_2", "sw4_3", "sw4_4", 370 "", "", "", ""; 371 gtr_sel0 { 372 gpio-hog; 373 gpios = <0 0>; 374 input; /* FIXME add meaning */ 375 line-name = "sw4_1"; 376 }; 377 gtr_sel1 { 378 gpio-hog; 379 gpios = <1 0>; 380 input; /* FIXME add meaning */ 381 line-name = "sw4_2"; 382 }; 383 gtr_sel2 { 384 gpio-hog; 385 gpios = <2 0>; 386 input; /* FIXME add meaning */ 387 line-name = "sw4_3"; 388 }; 389 gtr_sel3 { 390 gpio-hog; 391 gpios = <3 0>; 392 input; /* FIXME add meaning */ 393 line-name = "sw4_4"; 394 }; 395 }; 396 }; 397 i2c@2 { /* C0_DDR4 */ 398 #address-cells = <1>; 399 #size-cells = <0>; 400 reg = <2>; 401 si570_c0_ddr4: clock-generator@55 { /* u4 */ 402 #clock-cells = <0>; 403 compatible = "silabs,si570"; 404 reg = <0x55>; 405 temperature-stability = <50>; 406 factory-fout = <30000000>; 407 clock-frequency = <30000000>; 408 clock-output-names = "C0_DD4_SI570_CLK"; 409 }; 410 }; 411 i2c@3 { /* C1_RLD3 */ 412 #address-cells = <1>; 413 #size-cells = <0>; 414 reg = <3>; 415 si570_c1_lp4: clock-generator@55 { /* u7 */ 416 #clock-cells = <0>; 417 compatible = "silabs,si570"; 418 reg = <0x55>; 419 temperature-stability = <50>; 420 factory-fout = <30000000>; 421 clock-frequency = <30000000>; 422 clock-output-names = "C1_RLD3_SI570_CLK"; 423 }; 424 }; 425 i2c@4 { /* C2_DDR5 */ 426 #address-cells = <1>; 427 #size-cells = <0>; 428 reg = <4>; 429 si570_c2_lp4: clock-generator@55 { /* u10 */ 430 #clock-cells = <0>; 431 compatible = "silabs,si570"; 432 reg = <0x55>; 433 temperature-stability = <50>; 434 factory-fout = <30000000>; 435 clock-frequency = <30000000>; 436 clock-output-names = "C2_DDR5_SI570_CLK"; 437 }; 438 }; 439 i2c@5 { /* C3_DDR4 */ 440 #address-cells = <1>; 441 #size-cells = <0>; 442 reg = <5>; 443 si570_c3_lp4: clock-generator@55 { /* u15 */ 444 #clock-cells = <0>; 445 compatible = "silabs,si570"; 446 reg = <0x55>; 447 temperature-stability = <50>; 448 factory-fout = <30000000>; 449 clock-frequency = <30000000>; 450 clock-output-names = "C3_LP4_SI570_CLK"; 451 }; 452 }; 453 i2c@6 { /* HSDP_SI570 */ 454 #address-cells = <1>; 455 #size-cells = <0>; 456 reg = <6>; 457 si570_hsdp: clock-generator@5d { /* u19 */ 458 #clock-cells = <0>; 459 compatible = "silabs,si570"; 460 reg = <0x5d>; 461 temperature-stability = <50>; 462 factory-fout = <156250000>; 463 clock-frequency = <156250000>; 464 clock-output-names = "HSDP_SI570"; 465 }; 466 }; 467 }; 468}; 469 470&usb0 { 471 status = "okay"; 472 xlnx,usb-polarity = <0>; 473 xlnx,usb-reset-mode = <0>; 474}; 475 476&dwc3_0 { 477 status = "okay"; 478 dr_mode = "host"; 479 /* dr_mode = "peripheral"; */ 480 maximum-speed = "high-speed"; 481}; 482 483&usb1 { 484 status = "disabled"; /* not at mem board */ 485 xlnx,usb-polarity = <0>; 486 xlnx,usb-reset-mode = <0>; 487}; 488 489&dwc3_1 { 490 /delete-property/ phy-names ; 491 /delete-property/ phys ; 492 maximum-speed = "high-speed"; 493 snps,dis_u2_susphy_quirk ; 494 snps,dis_u3_susphy_quirk ; 495 status = "disabled"; 496}; 497