1// SPDX-License-Identifier: GPL-2.0+
2/*
3 * dts file for Xilinx ZynqMP ZCU104
4 *
5 * (C) Copyright 2017 - 2020, Xilinx, Inc.
6 *
7 * Michal Simek <michal.simek@xilinx.com>
8 */
9
10/dts-v1/;
11
12#include "zynqmp.dtsi"
13#include "zynqmp-clk-ccf.dtsi"
14#include <dt-bindings/gpio/gpio.h>
15#include <dt-bindings/phy/phy.h>
16
17/ {
18	model = "ZynqMP ZCU104 RevA";
19	compatible = "xlnx,zynqmp-zcu104-revA", "xlnx,zynqmp-zcu104", "xlnx,zynqmp";
20
21	aliases {
22		ethernet0 = &gem3;
23		gpio0 = &gpio;
24		i2c0 = &i2c1;
25		mmc0 = &sdhci1;
26		rtc0 = &rtc;
27		serial0 = &uart0;
28		serial1 = &uart1;
29		serial2 = &dcc;
30		spi0 = &qspi;
31		usb0 = &usb0;
32	};
33
34	chosen {
35		bootargs = "earlycon";
36		stdout-path = "serial0:115200n8";
37	};
38
39	memory@0 {
40		device_type = "memory";
41		reg = <0x0 0x0 0x0 0x80000000>;
42	};
43};
44
45&can1 {
46	status = "okay";
47};
48
49&dcc {
50	status = "okay";
51};
52
53&fpd_dma_chan1 {
54	status = "okay";
55};
56
57&fpd_dma_chan2 {
58	status = "okay";
59};
60
61&fpd_dma_chan3 {
62	status = "okay";
63};
64
65&fpd_dma_chan4 {
66	status = "okay";
67};
68
69&fpd_dma_chan5 {
70	status = "okay";
71};
72
73&fpd_dma_chan6 {
74	status = "okay";
75};
76
77&fpd_dma_chan7 {
78	status = "okay";
79};
80
81&fpd_dma_chan8 {
82	status = "okay";
83};
84
85&gem3 {
86	status = "okay";
87	phy-handle = <&phy0>;
88	phy-mode = "rgmii-id";
89	phy0: ethernet-phy@c {
90		reg = <0xc>;
91		ti,rx-internal-delay = <0x8>;
92		ti,tx-internal-delay = <0xa>;
93		ti,fifo-depth = <0x1>;
94		ti,dp83867-rxctrl-strap-quirk;
95	};
96};
97
98&gpio {
99	status = "okay";
100};
101
102&gpu {
103	status = "okay";
104};
105
106&i2c1 {
107	status = "okay";
108	clock-frequency = <400000>;
109
110	/* Another connection to this bus via PL i2c via PCA9306 - u45 */
111	i2c-mux@74 { /* u34 */
112		compatible = "nxp,pca9548";
113		#address-cells = <1>;
114		#size-cells = <0>;
115		reg = <0x74>;
116		i2c@0 {
117			#address-cells = <1>;
118			#size-cells = <0>;
119			reg = <0>;
120			/*
121			 * IIC_EEPROM 1kB memory which uses 256B blocks
122			 * where every block has different address.
123			 *    0 - 256B address 0x54
124			 * 256B - 512B address 0x55
125			 * 512B - 768B address 0x56
126			 * 768B - 1024B address 0x57
127			 */
128			eeprom: eeprom@54 { /* u23 */
129				compatible = "atmel,24c08";
130				reg = <0x54>;
131				#address-cells = <1>;
132				#size-cells = <1>;
133			};
134		};
135
136		i2c@1 {
137			#address-cells = <1>;
138			#size-cells = <0>;
139			reg = <1>;
140			clock_8t49n287: clock-generator@6c { /* 8T49N287 - u182 */
141				compatible = "idt,8t49n287";
142				reg = <0x6c>;
143			};
144		};
145
146		i2c@2 {
147			#address-cells = <1>;
148			#size-cells = <0>;
149			reg = <2>;
150			irps5401_43: irps5401@43 { /* IRPS5401 - u175 */
151				compatible = "infineon,irps5401";
152				reg = <0x43>; /* pmbus / i2c 0x13 */
153			};
154			irps5401_44: irps5401@44 { /* IRPS5401 - u180 */
155				compatible = "infineon,irps5401";
156				reg = <0x44>; /* pmbus / i2c 0x14 */
157			};
158		};
159
160		i2c@4 {
161			#address-cells = <1>;
162			#size-cells = <0>;
163			reg = <4>;
164			tca6416_u97: gpio@20 {
165				compatible = "ti,tca6416";
166				reg = <0x20>;
167				gpio-controller;
168				#gpio-cells = <2>;
169				/*
170				 * IRQ not connected
171				 * Lines:
172				 * 0 - IRPS5401_ALERT_B
173				 * 1 - HDMI_8T49N241_INT_ALM
174				 * 2 - MAX6643_OT_B
175				 * 3 - MAX6643_FANFAIL_B
176				 * 5 - IIC_MUX_RESET_B
177				 * 6 - GEM3_EXP_RESET_B
178				 * 7 - FMC_LPC_PRSNT_M2C_B
179				 * 4, 10 - 17 - not connected
180				 */
181			};
182		};
183
184		i2c@5 {
185			#address-cells = <1>;
186			#size-cells = <0>;
187			reg = <5>;
188		};
189
190		i2c@7 {
191			#address-cells = <1>;
192			#size-cells = <0>;
193			reg = <7>;
194		};
195
196		/* 3, 6 not connected */
197	};
198};
199
200&qspi {
201	status = "okay";
202	flash@0 {
203		compatible = "m25p80", "jedec,spi-nor"; /* n25q512a 128MiB */
204		#address-cells = <1>;
205		#size-cells = <1>;
206		reg = <0x0>;
207		spi-tx-bus-width = <1>;
208		spi-rx-bus-width = <4>;
209		spi-max-frequency = <108000000>; /* Based on DC1 spec */
210		partition@0 { /* for testing purpose */
211			label = "qspi-fsbl-uboot";
212			reg = <0x0 0x100000>;
213		};
214		partition@100000 { /* for testing purpose */
215			label = "qspi-linux";
216			reg = <0x100000 0x500000>;
217		};
218		partition@600000 { /* for testing purpose */
219			label = "qspi-device-tree";
220			reg = <0x600000 0x20000>;
221		};
222		partition@620000 { /* for testing purpose */
223			label = "qspi-rootfs";
224			reg = <0x620000 0x5E0000>;
225		};
226	};
227};
228
229&rtc {
230	status = "okay";
231};
232
233&sata {
234	status = "okay";
235	/* SATA OOB timing settings */
236	ceva,p0-cominit-params = /bits/ 8 <0x18 0x40 0x18 0x28>;
237	ceva,p0-comwake-params = /bits/ 8 <0x06 0x14 0x08 0x0E>;
238	ceva,p0-burst-params = /bits/ 8 <0x13 0x08 0x4A 0x06>;
239	ceva,p0-retry-params = /bits/ 16 <0x96A4 0x3FFC>;
240	ceva,p1-cominit-params = /bits/ 8 <0x18 0x40 0x18 0x28>;
241	ceva,p1-comwake-params = /bits/ 8 <0x06 0x14 0x08 0x0E>;
242	ceva,p1-burst-params = /bits/ 8 <0x13 0x08 0x4A 0x06>;
243	ceva,p1-retry-params = /bits/ 16 <0x96A4 0x3FFC>;
244	phy-names = "sata-phy";
245	phys = <&lane3 PHY_TYPE_SATA 1 1 125000000>;
246};
247
248/* SD1 with level shifter */
249&sdhci1 {
250	status = "okay";
251	no-1-8-v;
252	xlnx,mio-bank = <1>;
253	disable-wp;
254};
255
256&serdes {
257	status = "okay";
258};
259
260&uart0 {
261	status = "okay";
262};
263
264&uart1 {
265	status = "okay";
266};
267
268/* ULPI SMSC USB3320 */
269&usb0 {
270	status = "okay";
271};
272
273&dwc3_0 {
274	status = "okay";
275	dr_mode = "host";
276	snps,usb3_lpm_capable;
277	phy-names = "usb3-phy";
278	phys = <&lane2 PHY_TYPE_USB3 0 2 26000000>;
279	maximum-speed = "super-speed";
280};
281
282&watchdog0 {
283	status = "okay";
284};
285
286&xilinx_ams {
287	status = "okay";
288};
289
290&ams_ps {
291	status = "okay";
292};
293
294&ams_pl {
295	status = "okay";
296};
297