1 /* SPDX-License-Identifier: GPL-2.0+ */ 2 /* 3 * Copyright 2016-2018, 2020 NXP 4 * Copyright 2015, Freescale Semiconductor 5 */ 6 7 #ifndef _ASM_ARMV8_FSL_LAYERSCAPE_CONFIG_H_ 8 #define _ASM_ARMV8_FSL_LAYERSCAPE_CONFIG_H_ 9 10 #include <linux/kconfig.h> 11 #include <fsl_ddrc_version.h> 12 13 #ifndef __ASSEMBLY__ 14 #include <linux/bitops.h> 15 #endif 16 17 #define CONFIG_STANDALONE_LOAD_ADDR 0x80300000 18 19 /* 20 * Reserve secure memory 21 * To be aligned with MMU block size 22 */ 23 #define CONFIG_SYS_MEM_RESERVE_SECURE (66 * 1024 * 1024) /* 66MB */ 24 #define SPL_TLB_SETBACK 0x1000000 /* 16MB under effective memory top */ 25 26 #ifdef CONFIG_ARCH_LS2080A 27 #define CONFIG_SYS_FSL_CLUSTER_CLOCKS { 1, 1, 4, 4 } 28 #define SRDS_MAX_LANES 8 29 #define CONFIG_SYS_PAGE_SIZE 0x10000 30 #ifndef L1_CACHE_BYTES 31 #define L1_CACHE_SHIFT 6 32 #define L1_CACHE_BYTES BIT(L1_CACHE_SHIFT) 33 #endif 34 35 #define CONFIG_SYS_FSL_OCRAM_BASE 0x18000000 /* initial RAM */ 36 #define SYS_FSL_OCRAM_SPACE_SIZE 0x00200000 /* 2M space */ 37 #define CONFIG_SYS_FSL_OCRAM_SIZE 0x00020000 /* Real size 128K */ 38 39 /* DDR */ 40 #define CONFIG_SYS_DDR_BLOCK1_SIZE ((phys_size_t)2 << 30) 41 #define CONFIG_MAX_MEM_MAPPED CONFIG_SYS_DDR_BLOCK1_SIZE 42 43 #define CONFIG_SYS_FSL_CCSR_GUR_LE 44 #define CONFIG_SYS_FSL_CCSR_SCFG_LE 45 #define CONFIG_SYS_FSL_ESDHC_LE 46 #define CONFIG_SYS_FSL_IFC_LE 47 #define CONFIG_SYS_FSL_PEX_LUT_LE 48 49 #define CONFIG_SYS_MEMAC_LITTLE_ENDIAN 50 51 /* Generic Interrupt Controller Definitions */ 52 #define GICD_BASE 0x06000000 53 #define GICR_BASE 0x06100000 54 55 /* SMMU Defintions */ 56 #define SMMU_BASE 0x05000000 /* GR0 Base */ 57 58 /* SFP */ 59 #define CONFIG_SYS_FSL_SFP_VER_3_4 60 #define CONFIG_SYS_FSL_SFP_LE 61 #define CONFIG_SYS_FSL_SRK_LE 62 63 /* Security Monitor */ 64 #define CONFIG_SYS_FSL_SEC_MON_LE 65 66 /* Secure Boot */ 67 #define CONFIG_ESBC_HDR_LS 68 69 /* DCFG - GUR */ 70 #define CONFIG_SYS_FSL_CCSR_GUR_LE 71 72 /* Cache Coherent Interconnect */ 73 #define CCI_MN_BASE 0x04000000 74 #define CCI_MN_RNF_NODEID_LIST 0x180 75 #define CCI_MN_DVM_DOMAIN_CTL 0x200 76 #define CCI_MN_DVM_DOMAIN_CTL_SET 0x210 77 78 #define CCI_HN_F_0_BASE (CCI_MN_BASE + 0x200000) 79 #define CCI_HN_F_1_BASE (CCI_MN_BASE + 0x210000) 80 #define CCN_HN_F_SAM_CTL 0x8 /* offset on base HN_F base */ 81 #define CCN_HN_F_SAM_NODEID_MASK 0x7f 82 #define CCN_HN_F_SAM_NODEID_DDR0 0x4 83 #define CCN_HN_F_SAM_NODEID_DDR1 0xe 84 85 #define CCI_RN_I_0_BASE (CCI_MN_BASE + 0x800000) 86 #define CCI_RN_I_2_BASE (CCI_MN_BASE + 0x820000) 87 #define CCI_RN_I_6_BASE (CCI_MN_BASE + 0x860000) 88 #define CCI_RN_I_12_BASE (CCI_MN_BASE + 0x8C0000) 89 #define CCI_RN_I_16_BASE (CCI_MN_BASE + 0x900000) 90 #define CCI_RN_I_20_BASE (CCI_MN_BASE + 0x940000) 91 92 #define CCI_S0_QOS_CONTROL_BASE(x) ((CCI_RN_I_0_BASE + (x * 0x10000)) + 0x10) 93 #define CCI_S1_QOS_CONTROL_BASE(x) ((CCI_RN_I_0_BASE + (x * 0x10000)) + 0x110) 94 #define CCI_S2_QOS_CONTROL_BASE(x) ((CCI_RN_I_0_BASE + (x * 0x10000)) + 0x210) 95 96 #define CCI_AUX_CONTROL_BASE(x) ((CCI_RN_I_0_BASE + (x * 0x10000)) + 0x0500) 97 98 /* TZ Protection Controller Definitions */ 99 #define TZPC_BASE 0x02200000 100 #define TZPCR0SIZE_BASE (TZPC_BASE) 101 #define TZPCDECPROT_0_STAT_BASE (TZPC_BASE + 0x800) 102 #define TZPCDECPROT_0_SET_BASE (TZPC_BASE + 0x804) 103 #define TZPCDECPROT_0_CLR_BASE (TZPC_BASE + 0x808) 104 #define TZPCDECPROT_1_STAT_BASE (TZPC_BASE + 0x80C) 105 #define TZPCDECPROT_1_SET_BASE (TZPC_BASE + 0x810) 106 #define TZPCDECPROT_1_CLR_BASE (TZPC_BASE + 0x814) 107 #define TZPCDECPROT_2_STAT_BASE (TZPC_BASE + 0x818) 108 #define TZPCDECPROT_2_SET_BASE (TZPC_BASE + 0x81C) 109 #define TZPCDECPROT_2_CLR_BASE (TZPC_BASE + 0x820) 110 111 #define DCSR_CGACRE5 0x700070914ULL 112 #define EPU_EPCMPR5 0x700060914ULL 113 #define EPU_EPCCR5 0x700060814ULL 114 #define EPU_EPSMCR5 0x700060228ULL 115 #define EPU_EPECR5 0x700060314ULL 116 #define EPU_EPCTR5 0x700060a14ULL 117 #define EPU_EPGCR 0x700060000ULL 118 119 #define CONFIG_SYS_FSL_ERRATUM_A008751 120 121 #define CONFIG_SYS_FSL_MAX_NUM_OF_SEC 1 122 123 #elif defined(CONFIG_ARCH_LS1088A) 124 #define CONFIG_SYS_FSL_NUM_CC_PLLS 3 125 #define CONFIG_SYS_FSL_CLUSTER_CLOCKS { 1, 1 } 126 #define CONFIG_GICV3 127 #define CONFIG_SYS_PAGE_SIZE 0x10000 128 129 #define SRDS_MAX_LANES 4 130 #define SRDS_BITS_PER_LANE 4 131 132 /* TZ Protection Controller Definitions */ 133 #define TZPC_BASE 0x02200000 134 #define TZPCR0SIZE_BASE (TZPC_BASE) 135 #define TZPCDECPROT_0_STAT_BASE (TZPC_BASE + 0x800) 136 #define TZPCDECPROT_0_SET_BASE (TZPC_BASE + 0x804) 137 #define TZPCDECPROT_0_CLR_BASE (TZPC_BASE + 0x808) 138 #define TZPCDECPROT_1_STAT_BASE (TZPC_BASE + 0x80C) 139 #define TZPCDECPROT_1_SET_BASE (TZPC_BASE + 0x810) 140 #define TZPCDECPROT_1_CLR_BASE (TZPC_BASE + 0x814) 141 #define TZPCDECPROT_2_STAT_BASE (TZPC_BASE + 0x818) 142 #define TZPCDECPROT_2_SET_BASE (TZPC_BASE + 0x81C) 143 #define TZPCDECPROT_2_CLR_BASE (TZPC_BASE + 0x820) 144 145 /* Generic Interrupt Controller Definitions */ 146 #define GICD_BASE 0x06000000 147 #define GICR_BASE 0x06100000 148 149 /* SMMU Defintions */ 150 #define SMMU_BASE 0x05000000 /* GR0 Base */ 151 152 /* DDR */ 153 #define CONFIG_SYS_DDR_BLOCK1_SIZE ((phys_size_t)2 << 30) 154 #define CONFIG_MAX_MEM_MAPPED CONFIG_SYS_DDR_BLOCK1_SIZE 155 156 #define CONFIG_SYS_FSL_CCSR_GUR_LE 157 #define CONFIG_SYS_FSL_CCSR_SCFG_LE 158 #define CONFIG_SYS_FSL_ESDHC_LE 159 #define CONFIG_SYS_FSL_IFC_LE 160 #define CONFIG_SYS_FSL_PEX_LUT_LE 161 162 #define CONFIG_SYS_MEMAC_LITTLE_ENDIAN 163 164 /* SFP */ 165 #define CONFIG_SYS_FSL_SFP_VER_3_4 166 #define CONFIG_SYS_FSL_SFP_LE 167 #define CONFIG_SYS_FSL_SRK_LE 168 169 /* Security Monitor */ 170 #define CONFIG_SYS_FSL_SEC_MON_LE 171 172 /* Secure Boot */ 173 #define CONFIG_ESBC_HDR_LS 174 175 /* DCFG - GUR */ 176 #define CONFIG_SYS_FSL_CCSR_GUR_LE 177 #define CONFIG_SYS_FSL_MAX_NUM_OF_SEC 1 178 #define CONFIG_SYS_FSL_OCRAM_BASE 0x18000000 /* initial RAM */ 179 #define SYS_FSL_OCRAM_SPACE_SIZE 0x00200000 /* 2M space */ 180 #define CONFIG_SYS_FSL_OCRAM_SIZE 0x00020000 /* Real size 128K */ 181 182 /* LX2160A/LX2162A Soc Support */ 183 #elif defined(CONFIG_ARCH_LX2160A) || defined(CONFIG_ARCH_LX2162A) 184 #define TZPC_BASE 0x02200000 185 #define TZPCDECPROT_0_SET_BASE (TZPC_BASE + 0x804) 186 #if !CONFIG_IS_ENABLED(DM_I2C) 187 #define CONFIG_SYS_I2C 188 #define CONFIG_SYS_I2C_EARLY_INIT 189 #endif 190 #define SRDS_MAX_LANES 8 191 #ifndef L1_CACHE_BYTES 192 #define L1_CACHE_SHIFT 6 193 #define L1_CACHE_BYTES BIT(L1_CACHE_SHIFT) 194 #endif 195 #define CONFIG_SYS_FSL_CORES_PER_CLUSTER 2 196 #define CONFIG_SYS_FSL_CLUSTER_CLOCKS { 1, 1, 1, 1, 4, 4, 4, 4 } 197 #define CONFIG_SYS_FSL_NUM_CC_PLLS 4 198 199 #define CONFIG_SYS_PAGE_SIZE 0x10000 200 201 #define CONFIG_SYS_FSL_OCRAM_BASE 0x18000000 /* initial RAM */ 202 #define SYS_FSL_OCRAM_SPACE_SIZE 0x00200000 /* 2M space */ 203 #define CONFIG_SYS_FSL_OCRAM_SIZE 0x00040000 /* Real size 256K */ 204 205 /* DDR */ 206 #define CONFIG_SYS_DDR_BLOCK1_SIZE ((phys_size_t)2 << 30) 207 #define CONFIG_MAX_MEM_MAPPED CONFIG_SYS_DDR_BLOCK1_SIZE 208 209 #define CONFIG_SYS_FSL_CCSR_GUR_LE 210 #define CONFIG_SYS_FSL_CCSR_SCFG_LE 211 #define CONFIG_SYS_FSL_ESDHC_LE 212 #define CONFIG_SYS_FSL_PEX_LUT_LE 213 214 #define CONFIG_SYS_MEMAC_LITTLE_ENDIAN 215 216 /* Generic Interrupt Controller Definitions */ 217 #define GICD_BASE 0x06000000 218 #define GICR_BASE 0x06200000 219 220 /* SMMU Definitions */ 221 #define SMMU_BASE 0x05000000 /* GR0 Base */ 222 223 /* SFP */ 224 #define CONFIG_SYS_FSL_SFP_VER_3_4 225 #define CONFIG_SYS_FSL_SFP_LE 226 #define CONFIG_SYS_FSL_SRK_LE 227 228 /* Security Monitor */ 229 #define CONFIG_SYS_FSL_SEC_MON_LE 230 231 /* Secure Boot */ 232 #define CONFIG_ESBC_HDR_LS 233 234 /* DCFG - GUR */ 235 #define CONFIG_SYS_FSL_CCSR_GUR_LE 236 237 #define CONFIG_SYS_FSL_MAX_NUM_OF_SEC 1 238 239 #elif defined(CONFIG_ARCH_LS1028A) 240 #define CONFIG_SYS_FSL_NUM_CC_PLLS 3 241 #define CONFIG_SYS_FSL_CLUSTER_CLOCKS { 1, 1 } 242 #define CONFIG_GICV3 243 #define CONFIG_FSL_TZPC_BP147 244 #define CONFIG_FSL_TZASC_400 245 246 /* TZ Protection Controller Definitions */ 247 #define TZPC_BASE 0x02200000 248 #define TZPCR0SIZE_BASE (TZPC_BASE) 249 #define TZPCDECPROT_0_STAT_BASE (TZPC_BASE + 0x800) 250 #define TZPCDECPROT_0_SET_BASE (TZPC_BASE + 0x804) 251 #define TZPCDECPROT_0_CLR_BASE (TZPC_BASE + 0x808) 252 #define TZPCDECPROT_1_STAT_BASE (TZPC_BASE + 0x80C) 253 #define TZPCDECPROT_1_SET_BASE (TZPC_BASE + 0x810) 254 #define TZPCDECPROT_1_CLR_BASE (TZPC_BASE + 0x814) 255 #define TZPCDECPROT_2_STAT_BASE (TZPC_BASE + 0x818) 256 #define TZPCDECPROT_2_SET_BASE (TZPC_BASE + 0x81C) 257 #define TZPCDECPROT_2_CLR_BASE (TZPC_BASE + 0x820) 258 259 #define SRDS_MAX_LANES 4 260 #define SRDS_BITS_PER_LANE 4 261 262 #define CONFIG_SYS_FSL_OCRAM_BASE 0x18000000 /* initial RAM */ 263 #define SYS_FSL_OCRAM_SPACE_SIZE 0x00200000 /* 2M */ 264 #define CONFIG_SYS_FSL_OCRAM_SIZE 0x00040000 /* Real size 256K */ 265 266 /* Generic Interrupt Controller Definitions */ 267 #define GICD_BASE 0x06000000 268 #define GICR_BASE 0x06040000 269 270 /* SMMU Definitions */ 271 #define SMMU_BASE 0x05000000 /* GR0 Base */ 272 273 /* DDR */ 274 #define CONFIG_SYS_DDR_BLOCK1_SIZE ((phys_size_t)2 << 30) 275 #define CONFIG_MAX_MEM_MAPPED CONFIG_SYS_DDR_BLOCK1_SIZE 276 277 #define CONFIG_SYS_FSL_CCSR_GUR_LE 278 #define CONFIG_SYS_FSL_CCSR_SCFG_LE 279 #define CONFIG_SYS_FSL_ESDHC_LE 280 #define CONFIG_SYS_FSL_PEX_LUT_LE 281 282 #define CONFIG_SYS_MEMAC_LITTLE_ENDIAN 283 284 /* SFP */ 285 #define CONFIG_SYS_FSL_SFP_VER_3_4 286 #define CONFIG_SYS_FSL_SFP_LE 287 #define CONFIG_SYS_FSL_SRK_LE 288 289 /* SEC */ 290 #define CONFIG_SYS_FSL_MAX_NUM_OF_SEC 1 291 292 /* Security Monitor */ 293 #define CONFIG_SYS_FSL_SEC_MON_LE 294 295 /* Secure Boot */ 296 #define CONFIG_ESBC_HDR_LS 297 298 /* DCFG - GUR */ 299 #define CONFIG_SYS_FSL_CCSR_GUR_LE 300 301 #elif defined(CONFIG_FSL_LSCH2) 302 #define CONFIG_SYS_FSL_OCRAM_BASE 0x10000000 /* initial RAM */ 303 #define SYS_FSL_OCRAM_SPACE_SIZE 0x00200000 /* 2M space */ 304 #define CONFIG_SYS_FSL_OCRAM_SIZE 0x00020000 /* Real size 128K */ 305 306 #define DCSR_DCFG_SBEESR2 0x20140534 307 #define DCSR_DCFG_MBEESR2 0x20140544 308 309 #define CONFIG_SYS_FSL_CCSR_SCFG_BE 310 #define CONFIG_SYS_FSL_ESDHC_BE 311 #define CONFIG_SYS_FSL_WDOG_BE 312 #define CONFIG_SYS_FSL_DSPI_BE 313 #define CONFIG_SYS_FSL_CCSR_GUR_BE 314 #define CONFIG_SYS_FSL_PEX_LUT_BE 315 316 /* SoC related */ 317 #ifdef CONFIG_ARCH_LS1043A 318 #define CONFIG_SYS_FMAN_V3 319 #define CONFIG_SYS_FSL_QMAN_V3 320 #define CONFIG_SYS_NUM_FMAN 1 321 #define CONFIG_SYS_NUM_FM1_DTSEC 7 322 #define CONFIG_SYS_NUM_FM1_10GEC 1 323 #define CONFIG_SYS_DDR_BLOCK1_SIZE ((phys_size_t)2 << 30) 324 #define CONFIG_MAX_MEM_MAPPED CONFIG_SYS_DDR_BLOCK1_SIZE 325 326 #define QE_MURAM_SIZE 0x6000UL 327 #define MAX_QE_RISC 1 328 #define QE_NUM_OF_SNUM 28 329 330 #define CONFIG_SYS_FSL_IFC_BE 331 #define CONFIG_SYS_FSL_SFP_VER_3_2 332 #define CONFIG_SYS_FSL_SEC_MON_BE 333 #define CONFIG_SYS_FSL_SFP_BE 334 #define CONFIG_SYS_FSL_SRK_LE 335 #define CONFIG_KEY_REVOCATION 336 337 /* SMMU Defintions */ 338 #define SMMU_BASE 0x09000000 339 340 /* Generic Interrupt Controller Definitions */ 341 #define GICD_BASE 0x01401000 342 #define GICC_BASE 0x01402000 343 #define GICH_BASE 0x01404000 344 #define GICV_BASE 0x01406000 345 #define GICD_SIZE 0x1000 346 #define GICC_SIZE 0x2000 347 #define GICH_SIZE 0x2000 348 #define GICV_SIZE 0x2000 349 #ifdef CONFIG_HAS_FEATURE_GIC64K_ALIGN 350 #define GICD_BASE_64K 0x01410000 351 #define GICC_BASE_64K 0x01420000 352 #define GICH_BASE_64K 0x01440000 353 #define GICV_BASE_64K 0x01460000 354 #define GICD_SIZE_64K 0x10000 355 #define GICC_SIZE_64K 0x20000 356 #define GICH_SIZE_64K 0x20000 357 #define GICV_SIZE_64K 0x20000 358 #endif 359 360 #define DCFG_CCSR_SVR 0x1ee00a4 361 #define REV1_0 0x10 362 #define REV1_1 0x11 363 #define GIC_ADDR_BIT 31 364 #define SCFG_GIC400_ALIGN 0x1570188 365 366 #define CONFIG_SYS_FSL_MAX_NUM_OF_SEC 1 367 368 #elif defined(CONFIG_ARCH_LS1012A) 369 #define GICD_BASE 0x01401000 370 #define GICC_BASE 0x01402000 371 #define CONFIG_SYS_FSL_SFP_VER_3_2 372 #define CONFIG_SYS_FSL_SEC_MON_BE 373 #define CONFIG_SYS_FSL_SFP_BE 374 #define CONFIG_SYS_FSL_SRK_LE 375 #define CONFIG_KEY_REVOCATION 376 #define CONFIG_SYS_FSL_MAX_NUM_OF_SEC 1 377 #define CONFIG_SYS_DDR_BLOCK1_SIZE ((phys_size_t)2 << 30) 378 #define CONFIG_MAX_MEM_MAPPED CONFIG_SYS_DDR_BLOCK1_SIZE 379 380 #elif defined(CONFIG_ARCH_LS1046A) 381 #define CONFIG_SYS_FMAN_V3 382 #define CONFIG_SYS_FSL_QMAN_V3 383 #define CONFIG_SYS_NUM_FMAN 1 384 #define CONFIG_SYS_NUM_FM1_DTSEC 8 385 #define CONFIG_SYS_NUM_FM1_10GEC 2 386 #define CONFIG_SYS_DDR_BLOCK1_SIZE ((phys_size_t)2 << 30) 387 #define CONFIG_MAX_MEM_MAPPED CONFIG_SYS_DDR_BLOCK1_SIZE 388 389 #define CONFIG_SYS_FSL_IFC_BE 390 #define CONFIG_SYS_FSL_SFP_VER_3_2 391 #define CONFIG_SYS_FSL_SEC_MON_BE 392 #define CONFIG_SYS_FSL_SFP_BE 393 #define CONFIG_SYS_FSL_SRK_LE 394 #define CONFIG_KEY_REVOCATION 395 396 /* SMMU Defintions */ 397 #define SMMU_BASE 0x09000000 398 399 /* Generic Interrupt Controller Definitions */ 400 #define GICD_BASE 0x01410000 401 #define GICC_BASE 0x01420000 402 403 #define CONFIG_SYS_FSL_MAX_NUM_OF_SEC 1 404 #else 405 #error SoC not defined 406 #endif 407 #endif 408 409 #endif /* _ASM_ARMV8_FSL_LAYERSCAPE_CONFIG_H_ */ 410