1 /* SPDX-License-Identifier: GPL-2.0+ */ 2 /* 3 * Copyright 2017-2021 NXP 4 * Copyright 2015 Freescale Semiconductor 5 */ 6 7 #ifndef _ASM_ARMV8_FSL_LAYERSCAPE_SOC_H_ 8 #define _ASM_ARMV8_FSL_LAYERSCAPE_SOC_H_ 9 10 #ifndef __ASSEMBLY__ 11 #include <linux/types.h> 12 #ifdef CONFIG_FSL_LSCH2 13 #include <asm/arch/immap_lsch2.h> 14 #endif 15 #ifdef CONFIG_FSL_LSCH3 16 #include <asm/arch/immap_lsch3.h> 17 #endif 18 #endif 19 #include <asm/arch/svr.h> 20 21 #ifdef CONFIG_SYS_FSL_CCSR_GUR_LE 22 #define gur_in32(a) in_le32(a) 23 #define gur_out32(a, v) out_le32(a, v) 24 #elif defined(CONFIG_SYS_FSL_CCSR_GUR_BE) 25 #define gur_in32(a) in_be32(a) 26 #define gur_out32(a, v) out_be32(a, v) 27 #endif 28 29 #ifdef CONFIG_SYS_FSL_CCSR_SCFG_LE 30 #define scfg_in32(a) in_le32(a) 31 #define scfg_out32(a, v) out_le32(a, v) 32 #define scfg_clrbits32(addr, clear) clrbits_le32(addr, clear) 33 #define scfg_clrsetbits32(addr, clear, set) clrsetbits_le32(addr, clear, set) 34 #elif defined(CONFIG_SYS_FSL_CCSR_SCFG_BE) 35 #define scfg_in32(a) in_be32(a) 36 #define scfg_out32(a, v) out_be32(a, v) 37 #define scfg_clrbits32(addr, clear) clrbits_be32(addr, clear) 38 #define scfg_clrsetbits32(addr, clear, set) clrsetbits_be32(addr, clear, set) 39 #endif 40 41 #ifdef CONFIG_SYS_FSL_PEX_LUT_LE 42 #define pex_lut_in32(a) in_le32(a) 43 #define pex_lut_out32(a, v) out_le32(a, v) 44 #elif defined(CONFIG_SYS_FSL_PEX_LUT_BE) 45 #define pex_lut_in32(a) in_be32(a) 46 #define pex_lut_out32(a, v) out_be32(a, v) 47 #endif 48 #ifndef __ASSEMBLY__ 49 struct cpu_type { 50 char name[15]; 51 u32 soc_ver; 52 u32 num_cores; 53 }; 54 55 #define CPU_TYPE_ENTRY(n, v, nc) \ 56 { .name = #n, .soc_ver = SVR_##v, .num_cores = (nc)} 57 58 #ifdef CONFIG_TFABOOT 59 #define SMC_DRAM_BANK_INFO (0xC200FF12) 60 #define SIP_SVC_RCW 0xC200FF18 61 62 phys_size_t tfa_get_dram_size(void); 63 64 enum boot_src { 65 BOOT_SOURCE_RESERVED = 0, 66 BOOT_SOURCE_IFC_NOR, 67 BOOT_SOURCE_IFC_NAND, 68 BOOT_SOURCE_QSPI_NOR, 69 BOOT_SOURCE_QSPI_NAND, 70 BOOT_SOURCE_XSPI_NOR, 71 BOOT_SOURCE_XSPI_NAND, 72 BOOT_SOURCE_SD_MMC, 73 BOOT_SOURCE_SD_MMC2, 74 BOOT_SOURCE_I2C1_EXTENDED, 75 }; 76 77 enum boot_src get_boot_src(void); 78 #endif 79 #endif 80 #define SVR_WO_E 0xFFFFFE 81 82 #define SVR_MAJ(svr) (((svr) >> 4) & 0xf) 83 #define SVR_MIN(svr) (((svr) >> 0) & 0xf) 84 #define SVR_REV(svr) (((svr) >> 0) & 0xff) 85 #define IS_E_PROCESSOR(svr) (!((svr >> 8) & 0x1)) 86 #if defined(CONFIG_ARCH_LX2160A) || defined(CONFIG_ARCH_LX2162A) 87 #define IS_C_PROCESSOR(svr) (!((svr >> 12) & 0x1)) 88 #define SVR_WO_CE 0xFFFFEE 89 #define SVR_SOC_VER(svr) (((svr) >> 8) & SVR_WO_CE) 90 #else 91 #define SVR_SOC_VER(svr) (((svr) >> 8) & SVR_WO_E) 92 #endif 93 #ifdef CONFIG_ARCH_LS1028A 94 #define IS_MULTIMEDIA_EN(svr) (!((svr >> 10) & 0x1)) 95 #endif 96 #define IS_SVR_REV(svr, maj, min) \ 97 ((SVR_MAJ(svr) == (maj)) && (SVR_MIN(svr) == (min))) 98 #define SVR_DEV(svr) ((svr) >> 8) 99 #define IS_SVR_DEV(svr, dev) (((svr) >> 16) == (dev)) 100 101 #ifndef __ASSEMBLY__ 102 #ifdef CONFIG_FSL_LSCH3 103 void fsl_lsch3_early_init_f(void); 104 int get_core_volt_from_fuse(void); 105 #elif defined(CONFIG_FSL_LSCH2) 106 void fsl_lsch2_early_init_f(void); 107 int setup_chip_volt(void); 108 /* Setup core vdd in unit mV */ 109 int board_setup_core_volt(u32 vdd); 110 #ifdef CONFIG_FSL_PFE 111 void init_pfe_scfg_dcfg_regs(void); 112 #endif 113 #endif 114 #ifdef CONFIG_QSPI_AHB_INIT 115 int qspi_ahb_init(void); 116 #endif 117 118 #ifdef CONFIG_FSPI_AHB_EN_4BYTE 119 #define SYS_NXP_FSPI_LUTCR_LOCK 0x00000001 120 #define SYS_NXP_FSPI_LUTCR_UNLOCK 0x00000002 121 #define SYS_NXP_FSPI_LUTKEY 0x5AF05AF0 122 int fspi_ahb_init(void); 123 #endif 124 125 void cpu_name(char *name); 126 #ifdef CONFIG_SYS_FSL_ERRATUM_A009635 127 void erratum_a009635(void); 128 #endif 129 130 #ifdef CONFIG_SYS_FSL_ERRATUM_A010315 131 void erratum_a010315(void); 132 #endif 133 134 bool soc_has_dp_ddr(void); 135 bool soc_has_aiop(void); 136 137 #ifdef CONFIG_GIC_V3_ITS 138 int ls_gic_rd_tables_init(void *blob); 139 #endif 140 #endif 141 142 #endif /* _ASM_ARMV8_FSL_LAYERSCAPE_SOC_H_ */ 143