1 /* SPDX-License-Identifier: GPL-2.0 */ 2 /* 3 * (C) Copyright 2017 Theobroma Systems Design und Consulting GmbH 4 */ 5 6 #ifndef __ASM_ARCH_DDR_RK3368_H__ 7 #define __ASM_ARCH_DDR_RK3368_H__ 8 9 #ifndef __ASSEMBLY__ 10 #include <linux/bitops.h> 11 #endif 12 13 /* 14 * The RK3368 DDR PCTL differs from the incarnation in the RK3288 only 15 * in a few details. Most notably, it has an additional field to track 16 * tREFI in controller cycles (i.e. trefi_mem_ddr3). 17 */ 18 struct rk3368_ddr_pctl { 19 u32 scfg; 20 u32 sctl; 21 u32 stat; 22 u32 intrstat; 23 u32 reserved0[12]; 24 u32 mcmd; 25 u32 powctl; 26 u32 powstat; 27 u32 cmdtstat; 28 u32 cmdtstaten; 29 u32 reserved1[3]; 30 u32 mrrcfg0; 31 u32 mrrstat0; 32 u32 mrrstat1; 33 u32 reserved2[4]; 34 u32 mcfg1; 35 u32 mcfg; 36 u32 ppcfg; 37 u32 mstat; 38 u32 lpddr2zqcfg; 39 u32 reserved3; 40 u32 dtupdes; 41 u32 dtuna; 42 u32 dtune; 43 u32 dtuprd0; 44 u32 dtuprd1; 45 u32 dtuprd2; 46 u32 dtuprd3; 47 u32 dtuawdt; 48 u32 reserved4[3]; 49 u32 togcnt1u; 50 u32 tinit; 51 u32 trsth; 52 u32 togcnt100n; 53 u32 trefi; 54 u32 tmrd; 55 u32 trfc; 56 u32 trp; 57 u32 trtw; 58 u32 tal; 59 u32 tcl; 60 u32 tcwl; 61 u32 tras; 62 u32 trc; 63 u32 trcd; 64 u32 trrd; 65 u32 trtp; 66 u32 twr; 67 u32 twtr; 68 u32 texsr; 69 u32 txp; 70 u32 txpdll; 71 u32 tzqcs; 72 u32 tzqcsi; 73 u32 tdqs; 74 u32 tcksre; 75 u32 tcksrx; 76 u32 tcke; 77 u32 tmod; 78 u32 trstl; 79 u32 tzqcl; 80 u32 tmrr; 81 u32 tckesr; 82 u32 tdpd; 83 u32 trefi_mem_ddr3; 84 u32 reserved5[45]; 85 u32 dtuwactl; 86 u32 dturactl; 87 u32 dtucfg; 88 u32 dtuectl; 89 u32 dtuwd0; 90 u32 dtuwd1; 91 u32 dtuwd2; 92 u32 dtuwd3; 93 u32 dtuwdm; 94 u32 dturd0; 95 u32 dturd1; 96 u32 dturd2; 97 u32 dturd3; 98 u32 dtulfsrwd; 99 u32 dtulfsrrd; 100 u32 dtueaf; 101 u32 dfitctrldelay; 102 u32 dfiodtcfg; 103 u32 dfiodtcfg1; 104 u32 dfiodtrankmap; 105 u32 dfitphywrdata; 106 u32 dfitphywrlat; 107 u32 reserved7[2]; 108 u32 dfitrddataen; 109 u32 dfitphyrdlat; 110 u32 reserved8[2]; 111 u32 dfitphyupdtype0; 112 u32 dfitphyupdtype1; 113 u32 dfitphyupdtype2; 114 u32 dfitphyupdtype3; 115 u32 dfitctrlupdmin; 116 u32 dfitctrlupdmax; 117 u32 dfitctrlupddly; 118 u32 reserved9; 119 u32 dfiupdcfg; 120 u32 dfitrefmski; 121 u32 dfitctrlupdi; 122 u32 reserved10[4]; 123 u32 dfitrcfg0; 124 u32 dfitrstat0; 125 u32 dfitrwrlvlen; 126 u32 dfitrrdlvlen; 127 u32 dfitrrdlvlgateen; 128 u32 dfiststat0; 129 u32 dfistcfg0; 130 u32 dfistcfg1; 131 u32 reserved11; 132 u32 dfitdramclken; 133 u32 dfitdramclkdis; 134 u32 dfistcfg2; 135 u32 dfistparclr; 136 u32 dfistparlog; 137 u32 reserved12[3]; 138 u32 dfilpcfg0; 139 u32 reserved13[3]; 140 u32 dfitrwrlvlresp0; 141 u32 dfitrwrlvlresp1; 142 u32 dfitrwrlvlresp2; 143 u32 dfitrrdlvlresp0; 144 u32 dfitrrdlvlresp1; 145 u32 dfitrrdlvlresp2; 146 u32 dfitrwrlvldelay0; 147 u32 dfitrwrlvldelay1; 148 u32 dfitrwrlvldelay2; 149 u32 dfitrrdlvldelay0; 150 u32 dfitrrdlvldelay1; 151 u32 dfitrrdlvldelay2; 152 u32 dfitrrdlvlgatedelay0; 153 u32 dfitrrdlvlgatedelay1; 154 u32 dfitrrdlvlgatedelay2; 155 u32 dfitrcmd; 156 u32 reserved14[46]; 157 u32 ipvr; 158 u32 iptr; 159 }; 160 check_member(rk3368_ddr_pctl, iptr, 0x03fc); 161 162 struct rk3368_ddrphy { 163 u32 reg[0x100]; 164 }; 165 check_member(rk3368_ddrphy, reg[0xff], 0x03fc); 166 167 struct rk3368_msch { 168 u32 coreid; 169 u32 revisionid; 170 u32 ddrconf; 171 u32 ddrtiming; 172 u32 ddrmode; 173 u32 readlatency; 174 u32 reserved1[8]; 175 u32 activate; 176 u32 devtodev; 177 }; 178 check_member(rk3368_msch, devtodev, 0x003c); 179 180 /* GRF_SOC_CON0 */ 181 enum { 182 NOC_RSP_ERR_STALL = BIT(9), 183 MOBILE_DDR_SEL = BIT(4), 184 DDR0_16BIT_EN = BIT(3), 185 MSCH0_MAINDDR3_DDR3 = BIT(2), 186 MSCH0_MAINPARTIALPOP = BIT(1), 187 UPCTL_C_ACTIVE = BIT(0), 188 }; 189 190 #endif 191