1 /* SPDX-License-Identifier: GPL-2.0+ */ 2 /* 3 * Copyright (C) 2018 Rockchip Electronics Co., Ltd 4 */ 5 6 #ifndef _ASM_ARCH_SDRAM_COMMON_H 7 #define _ASM_ARCH_SDRAM_COMMON_H 8 9 #ifndef MHZ 10 #define MHZ (1000 * 1000) 11 #endif 12 13 #define PATTERN (0x5aa5f00f) 14 15 #define MIN(a, b) (((a) > (b)) ? (b) : (a)) 16 #define MAX(a, b) (((a) > (b)) ? (a) : (b)) 17 18 struct sdram_cap_info { 19 unsigned int rank; 20 /* dram column number, 0 means this channel is invalid */ 21 unsigned int col; 22 /* dram bank number, 3:8bank, 2:4bank */ 23 unsigned int bk; 24 /* channel buswidth, 2:32bit, 1:16bit, 0:8bit */ 25 unsigned int bw; 26 /* die buswidth, 2:32bit, 1:16bit, 0:8bit */ 27 unsigned int dbw; 28 /* 29 * row_3_4 = 1: 6Gb or 12Gb die 30 * row_3_4 = 0: normal die, power of 2 31 */ 32 unsigned int row_3_4; 33 unsigned int cs0_row; 34 unsigned int cs1_row; 35 unsigned int cs0_high16bit_row; 36 unsigned int cs1_high16bit_row; 37 unsigned int ddrconfig; 38 }; 39 40 struct sdram_base_params { 41 unsigned int ddr_freq; 42 unsigned int dramtype; 43 unsigned int num_channels; 44 unsigned int stride; 45 unsigned int odt; 46 }; 47 48 #define DDR_SYS_REG_VERSION (0x2) 49 /* 50 * sys_reg2 bitfield struct 51 * [31] row_3_4_ch1 52 * [30] row_3_4_ch0 53 * [29:28] chinfo 54 * [27] rank_ch1 55 * [26:25] col_ch1 56 * [24] bk_ch1 57 * [23:22] cs0_row_ch1 58 * [21:20] cs1_row_ch1 59 * [19:18] bw_ch1 60 * [17:16] dbw_ch1; 61 * [15:13] ddrtype 62 * [12] channelnum 63 * [11] rank_ch0 64 * [10:9] col_ch0 65 * [8] bk_ch0 66 * [7:6] cs0_row_ch0 67 * [5:4] cs1_row_ch0 68 * [3:2] bw_ch0 69 * [1:0] dbw_ch0 70 */ 71 #define SYS_REG_ENC_ROW_3_4(n, ch) ((n) << (30 + (ch))) 72 #define SYS_REG_DEC_ROW_3_4(n, ch) (((n) >> (30 + (ch))) & 0x1) 73 #define SYS_REG_ENC_CHINFO(ch) (1 << (28 + (ch))) 74 #define SYS_REG_ENC_DDRTYPE(n) ((n) << 13) 75 #define SYS_REG_DEC_DDRTYPE(n) (((n) >> 13) & 0x7) 76 #define SYS_REG_ENC_NUM_CH(n) (((n) - 1) << 12) 77 #define SYS_REG_DEC_NUM_CH(n) (1 + (((n) >> 12) & 0x1)) 78 #define SYS_REG_ENC_RANK(n, ch) (((n) - 1) << (11 + ((ch) * 16))) 79 #define SYS_REG_DEC_RANK(n, ch) (1 + (((n) >> (11 + 16 * (ch))) & 0x1)) 80 #define SYS_REG_ENC_COL(n, ch) (((n) - 9) << (9 + ((ch) * 16))) 81 #define SYS_REG_DEC_COL(n, ch) (9 + (((n) >> (9 + 16 * (ch))) & 0x3)) 82 #define SYS_REG_ENC_BK(n, ch) (((n) == 3 ? 0 : 1) << \ 83 (8 + ((ch) * 16))) 84 #define SYS_REG_DEC_BK(n, ch) (3 - (((n) >> (8 + 16 * (ch))) & 0x1)) 85 #define SYS_REG_ENC_BW(n, ch) ((2 >> (n)) << (2 + ((ch) * 16))) 86 #define SYS_REG_DEC_BW(n, ch) (2 >> (((n) >> (2 + 16 * (ch))) & 0x3)) 87 #define SYS_REG_ENC_DBW(n, ch) ((2 >> (n)) << (0 + ((ch) * 16))) 88 #define SYS_REG_DEC_DBW(n, ch) (2 >> (((n) >> (0 + 16 * (ch))) & 0x3)) 89 /* sys reg 3 */ 90 #define SYS_REG_ENC_VERSION(n) ((n) << 28) 91 #define SYS_REG_DEC_VERSION(n) (((n) >> 28) & 0xf) 92 #define SYS_REG_ENC_CS0_ROW(n, os_reg2, os_reg3, ch) do { \ 93 (os_reg2) |= (((n) - 13) & 0x3) << (6 + 16 * (ch)); \ 94 (os_reg3) |= ((((n) - 13) & 0x4) >> 2) << \ 95 (5 + 2 * (ch)); \ 96 } while (0) 97 98 #define SYS_REG_DEC_CS0_ROW(os_reg2, os_reg3, ch) \ 99 ((((((os_reg2) >> (6 + 16 * (ch)) & 0x3) | \ 100 ((((os_reg3) >> (5 + 2 * (ch))) & 0x1) << 2)) + 1) & 0x7) + 12) 101 102 #define SYS_REG_ENC_CS1_ROW(n, os_reg2, os_reg3, ch) do { \ 103 (os_reg2) &= (~(0x3 << (4 + 16 * (ch)))); \ 104 (os_reg3) &= (~(0x1 << (4 + 2 * (ch)))); \ 105 (os_reg2) |= (((n) - 13) & 0x3) << (4 + 16 * (ch)); \ 106 (os_reg3) |= ((((n) - 13) & 0x4) >> 2) << \ 107 (4 + 2 * (ch)); \ 108 } while (0) 109 110 #define SYS_REG_DEC_CS1_ROW(os_reg2, os_reg3, ch) \ 111 ((((((os_reg2) >> (4 + 16 * (ch)) & 0x3) | \ 112 ((((os_reg3) >> (4 + 2 * (ch))) & 0x1) << 2)) + 1) & 0x7) + 12) 113 114 #define SYS_REG_ENC_CS1_COL(n, ch) (((n) - 9) << (0 + 2 * (ch))) 115 #define SYS_REG_DEC_CS1_COL(n, ch) (9 + (((n) >> (0 + 2 * (ch))) & 0x3)) 116 117 void sdram_print_dram_type(unsigned char dramtype); 118 void sdram_print_ddr_info(struct sdram_cap_info *cap_info, 119 struct sdram_base_params *base); 120 void sdram_print_stride(unsigned int stride); 121 122 void sdram_org_config(struct sdram_cap_info *cap_info, 123 struct sdram_base_params *base, 124 u32 *p_os_reg2, u32 *p_os_reg3, u32 channel); 125 126 int sdram_detect_bw(struct sdram_cap_info *cap_info); 127 int sdram_detect_cs(struct sdram_cap_info *cap_info); 128 int sdram_detect_col(struct sdram_cap_info *cap_info, 129 u32 coltmp); 130 int sdram_detect_bank(struct sdram_cap_info *cap_info, 131 u32 coltmp, u32 bktmp); 132 int sdram_detect_bg(struct sdram_cap_info *cap_info, 133 u32 coltmp); 134 int sdram_detect_dbw(struct sdram_cap_info *cap_info, u32 dram_type); 135 int sdram_detect_row(struct sdram_cap_info *cap_info, 136 u32 coltmp, u32 bktmp, u32 rowtmp); 137 int sdram_detect_row_3_4(struct sdram_cap_info *cap_info, 138 u32 coltmp, u32 bktmp); 139 int sdram_detect_high_row(struct sdram_cap_info *cap_info); 140 int sdram_detect_cs1_row(struct sdram_cap_info *cap_info, u32 dram_type); 141 u64 sdram_get_cs_cap(struct sdram_cap_info *cap_info, u32 cs, u32 dram_type); 142 void sdram_copy_to_reg(u32 *dest, const u32 *src, u32 n); 143 144 #endif 145