1 /* SPDX-License-Identifier: GPL-2.0+ */ 2 /* 3 * (C) Copyright 2010 4 * NVIDIA Corporation <www.nvidia.com> 5 */ 6 7 #ifndef __ASM_ARCH_TEGRA_DC_H 8 #define __ASM_ARCH_TEGRA_DC_H 9 10 #ifndef __ASSEMBLY__ 11 #include <linux/bitops.h> 12 #endif 13 14 /* Register definitions for the Tegra display controller */ 15 16 /* CMD register 0x000 ~ 0x43 */ 17 struct dc_cmd_reg { 18 /* Address 0x000 ~ 0x002 */ 19 uint gen_incr_syncpt; /* _CMD_GENERAL_INCR_SYNCPT_0 */ 20 uint gen_incr_syncpt_ctrl; /* _CMD_GENERAL_INCR_SYNCPT_CNTRL_0 */ 21 uint gen_incr_syncpt_err; /* _CMD_GENERAL_INCR_SYNCPT_ERROR_0 */ 22 23 uint reserved0[5]; /* reserved_0[5] */ 24 25 /* Address 0x008 ~ 0x00a */ 26 uint win_a_incr_syncpt; /* _CMD_WIN_A_INCR_SYNCPT_0 */ 27 uint win_a_incr_syncpt_ctrl; /* _CMD_WIN_A_INCR_SYNCPT_CNTRL_0 */ 28 uint win_a_incr_syncpt_err; /* _CMD_WIN_A_INCR_SYNCPT_ERROR_0 */ 29 30 uint reserved1[5]; /* reserved_1[5] */ 31 32 /* Address 0x010 ~ 0x012 */ 33 uint win_b_incr_syncpt; /* _CMD_WIN_B_INCR_SYNCPT_0 */ 34 uint win_b_incr_syncpt_ctrl; /* _CMD_WIN_B_INCR_SYNCPT_CNTRL_0 */ 35 uint win_b_incr_syncpt_err; /* _CMD_WIN_B_INCR_SYNCPT_ERROR_0 */ 36 37 uint reserved2[5]; /* reserved_2[5] */ 38 39 /* Address 0x018 ~ 0x01a */ 40 uint win_c_incr_syncpt; /* _CMD_WIN_C_INCR_SYNCPT_0 */ 41 uint win_c_incr_syncpt_ctrl; /* _CMD_WIN_C_INCR_SYNCPT_CNTRL_0 */ 42 uint win_c_incr_syncpt_err; /* _CMD_WIN_C_INCR_SYNCPT_ERROR_0 */ 43 44 uint reserved3[13]; /* reserved_3[13] */ 45 46 /* Address 0x028 */ 47 uint cont_syncpt_vsync; /* _CMD_CONT_SYNCPT_VSYNC_0 */ 48 49 uint reserved4[7]; /* reserved_4[7] */ 50 51 /* Address 0x030 ~ 0x033 */ 52 uint ctxsw; /* _CMD_CTXSW_0 */ 53 uint disp_cmd_opt0; /* _CMD_DISPLAY_COMMAND_OPTION0_0 */ 54 uint disp_cmd; /* _CMD_DISPLAY_COMMAND_0 */ 55 uint sig_raise; /* _CMD_SIGNAL_RAISE_0 */ 56 57 uint reserved5[2]; /* reserved_0[2] */ 58 59 /* Address 0x036 ~ 0x03e */ 60 uint disp_pow_ctrl; /* _CMD_DISPLAY_POWER_CONTROL_0 */ 61 uint int_stat; /* _CMD_INT_STATUS_0 */ 62 uint int_mask; /* _CMD_INT_MASK_0 */ 63 uint int_enb; /* _CMD_INT_ENABLE_0 */ 64 uint int_type; /* _CMD_INT_TYPE_0 */ 65 uint int_polarity; /* _CMD_INT_POLARITY_0 */ 66 uint sig_raise1; /* _CMD_SIGNAL_RAISE1_0 */ 67 uint sig_raise2; /* _CMD_SIGNAL_RAISE2_0 */ 68 uint sig_raise3; /* _CMD_SIGNAL_RAISE3_0 */ 69 70 uint reserved6; /* reserved_6 */ 71 72 /* Address 0x040 ~ 0x043 */ 73 uint state_access; /* _CMD_STATE_ACCESS_0 */ 74 uint state_ctrl; /* _CMD_STATE_CONTROL_0 */ 75 uint disp_win_header; /* _CMD_DISPLAY_WINDOW_HEADER_0 */ 76 uint reg_act_ctrl; /* _CMD_REG_ACT_CONTROL_0 */ 77 }; 78 79 enum { 80 PIN_REG_COUNT = 4, 81 PIN_OUTPUT_SEL_COUNT = 7, 82 }; 83 84 /* COM register 0x300 ~ 0x329 */ 85 struct dc_com_reg { 86 /* Address 0x300 ~ 0x301 */ 87 uint crc_ctrl; /* _COM_CRC_CONTROL_0 */ 88 uint crc_checksum; /* _COM_CRC_CHECKSUM_0 */ 89 90 /* _COM_PIN_OUTPUT_ENABLE0/1/2/3_0: Address 0x302 ~ 0x305 */ 91 uint pin_output_enb[PIN_REG_COUNT]; 92 93 /* _COM_PIN_OUTPUT_POLARITY0/1/2/3_0: Address 0x306 ~ 0x309 */ 94 uint pin_output_polarity[PIN_REG_COUNT]; 95 96 /* _COM_PIN_OUTPUT_DATA0/1/2/3_0: Address 0x30a ~ 0x30d */ 97 uint pin_output_data[PIN_REG_COUNT]; 98 99 /* _COM_PIN_INPUT_ENABLE0_0: Address 0x30e ~ 0x311 */ 100 uint pin_input_enb[PIN_REG_COUNT]; 101 102 /* Address 0x312 ~ 0x313 */ 103 uint pin_input_data0; /* _COM_PIN_INPUT_DATA0_0 */ 104 uint pin_input_data1; /* _COM_PIN_INPUT_DATA1_0 */ 105 106 /* _COM_PIN_OUTPUT_SELECT0/1/2/3/4/5/6_0: Address 0x314 ~ 0x31a */ 107 uint pin_output_sel[PIN_OUTPUT_SEL_COUNT]; 108 109 /* Address 0x31b ~ 0x329 */ 110 uint pin_misc_ctrl; /* _COM_PIN_MISC_CONTROL_0 */ 111 uint pm0_ctrl; /* _COM_PM0_CONTROL_0 */ 112 uint pm0_duty_cycle; /* _COM_PM0_DUTY_CYCLE_0 */ 113 uint pm1_ctrl; /* _COM_PM1_CONTROL_0 */ 114 uint pm1_duty_cycle; /* _COM_PM1_DUTY_CYCLE_0 */ 115 uint spi_ctrl; /* _COM_SPI_CONTROL_0 */ 116 uint spi_start_byte; /* _COM_SPI_START_BYTE_0 */ 117 uint hspi_wr_data_ab; /* _COM_HSPI_WRITE_DATA_AB_0 */ 118 uint hspi_wr_data_cd; /* _COM_HSPI_WRITE_DATA_CD */ 119 uint hspi_cs_dc; /* _COM_HSPI_CS_DC_0 */ 120 uint scratch_reg_a; /* _COM_SCRATCH_REGISTER_A_0 */ 121 uint scratch_reg_b; /* _COM_SCRATCH_REGISTER_B_0 */ 122 uint gpio_ctrl; /* _COM_GPIO_CTRL_0 */ 123 uint gpio_debounce_cnt; /* _COM_GPIO_DEBOUNCE_COUNTER_0 */ 124 uint crc_checksum_latched; /* _COM_CRC_CHECKSUM_LATCHED_0 */ 125 }; 126 127 enum dc_disp_h_pulse_pos { 128 H_PULSE0_POSITION_A, 129 H_PULSE0_POSITION_B, 130 H_PULSE0_POSITION_C, 131 H_PULSE0_POSITION_D, 132 H_PULSE0_POSITION_COUNT, 133 }; 134 135 struct _disp_h_pulse { 136 /* _DISP_H_PULSE0/1/2_CONTROL_0 */ 137 uint h_pulse_ctrl; 138 /* _DISP_H_PULSE0/1/2_POSITION_A/B/C/D_0 */ 139 uint h_pulse_pos[H_PULSE0_POSITION_COUNT]; 140 }; 141 142 enum dc_disp_v_pulse_pos { 143 V_PULSE0_POSITION_A, 144 V_PULSE0_POSITION_B, 145 V_PULSE0_POSITION_C, 146 V_PULSE0_POSITION_COUNT, 147 }; 148 149 struct _disp_v_pulse0 { 150 /* _DISP_H_PULSE0/1_CONTROL_0 */ 151 uint v_pulse_ctrl; 152 /* _DISP_H_PULSE0/1_POSITION_A/B/C_0 */ 153 uint v_pulse_pos[V_PULSE0_POSITION_COUNT]; 154 }; 155 156 struct _disp_v_pulse2 { 157 /* _DISP_H_PULSE2/3_CONTROL_0 */ 158 uint v_pulse_ctrl; 159 /* _DISP_H_PULSE2/3_POSITION_A_0 */ 160 uint v_pulse_pos_a; 161 }; 162 163 enum dc_disp_h_pulse_reg { 164 H_PULSE0, 165 H_PULSE1, 166 H_PULSE2, 167 H_PULSE_COUNT, 168 }; 169 170 enum dc_disp_pp_select { 171 PP_SELECT_A, 172 PP_SELECT_B, 173 PP_SELECT_C, 174 PP_SELECT_D, 175 PP_SELECT_COUNT, 176 }; 177 178 /* DISP register 0x400 ~ 0x4c1 */ 179 struct dc_disp_reg { 180 /* Address 0x400 ~ 0x40a */ 181 uint disp_signal_opt0; /* _DISP_DISP_SIGNAL_OPTIONS0_0 */ 182 uint disp_signal_opt1; /* _DISP_DISP_SIGNAL_OPTIONS1_0 */ 183 uint disp_win_opt; /* _DISP_DISP_WIN_OPTIONS_0 */ 184 uint mem_high_pri; /* _DISP_MEM_HIGH_PRIORITY_0 */ 185 uint mem_high_pri_timer; /* _DISP_MEM_HIGH_PRIORITY_TIMER_0 */ 186 uint disp_timing_opt; /* _DISP_DISP_TIMING_OPTIONS_0 */ 187 uint ref_to_sync; /* _DISP_REF_TO_SYNC_0 */ 188 uint sync_width; /* _DISP_SYNC_WIDTH_0 */ 189 uint back_porch; /* _DISP_BACK_PORCH_0 */ 190 uint disp_active; /* _DISP_DISP_ACTIVE_0 */ 191 uint front_porch; /* _DISP_FRONT_PORCH_0 */ 192 193 /* Address 0x40b ~ 0x419: _DISP_H_PULSE0/1/2_ */ 194 struct _disp_h_pulse h_pulse[H_PULSE_COUNT]; 195 196 /* Address 0x41a ~ 0x421 */ 197 struct _disp_v_pulse0 v_pulse0; /* _DISP_V_PULSE0_ */ 198 struct _disp_v_pulse0 v_pulse1; /* _DISP_V_PULSE1_ */ 199 200 /* Address 0x422 ~ 0x425 */ 201 struct _disp_v_pulse2 v_pulse3; /* _DISP_V_PULSE2_ */ 202 struct _disp_v_pulse2 v_pulse4; /* _DISP_V_PULSE3_ */ 203 204 /* Address 0x426 ~ 0x429 */ 205 uint m0_ctrl; /* _DISP_M0_CONTROL_0 */ 206 uint m1_ctrl; /* _DISP_M1_CONTROL_0 */ 207 uint di_ctrl; /* _DISP_DI_CONTROL_0 */ 208 uint pp_ctrl; /* _DISP_PP_CONTROL_0 */ 209 210 /* Address 0x42a ~ 0x42d: _DISP_PP_SELECT_A/B/C/D_0 */ 211 uint pp_select[PP_SELECT_COUNT]; 212 213 /* Address 0x42e ~ 0x435 */ 214 uint disp_clk_ctrl; /* _DISP_DISP_CLOCK_CONTROL_0 */ 215 uint disp_interface_ctrl; /* _DISP_DISP_INTERFACE_CONTROL_0 */ 216 uint disp_color_ctrl; /* _DISP_DISP_COLOR_CONTROL_0 */ 217 uint shift_clk_opt; /* _DISP_SHIFT_CLOCK_OPTIONS_0 */ 218 uint data_enable_opt; /* _DISP_DATA_ENABLE_OPTIONS_0 */ 219 uint serial_interface_opt; /* _DISP_SERIAL_INTERFACE_OPTIONS_0 */ 220 uint lcd_spi_opt; /* _DISP_LCD_SPI_OPTIONS_0 */ 221 uint border_color; /* _DISP_BORDER_COLOR_0 */ 222 223 /* Address 0x436 ~ 0x439 */ 224 uint color_key0_lower; /* _DISP_COLOR_KEY0_LOWER_0 */ 225 uint color_key0_upper; /* _DISP_COLOR_KEY0_UPPER_0 */ 226 uint color_key1_lower; /* _DISP_COLOR_KEY1_LOWER_0 */ 227 uint color_key1_upper; /* _DISP_COLOR_KEY1_UPPER_0 */ 228 229 uint reserved0[2]; /* reserved_0[2] */ 230 231 /* Address 0x43c ~ 0x442 */ 232 uint cursor_foreground; /* _DISP_CURSOR_FOREGROUND_0 */ 233 uint cursor_background; /* _DISP_CURSOR_BACKGROUND_0 */ 234 uint cursor_start_addr; /* _DISP_CURSOR_START_ADDR_0 */ 235 uint cursor_start_addr_ns; /* _DISP_CURSOR_START_ADDR_NS_0 */ 236 uint cursor_pos; /* _DISP_CURSOR_POSITION_0 */ 237 uint cursor_pos_ns; /* _DISP_CURSOR_POSITION_NS_0 */ 238 uint seq_ctrl; /* _DISP_INIT_SEQ_CONTROL_0 */ 239 240 /* Address 0x443 ~ 0x446 */ 241 uint spi_init_seq_data_a; /* _DISP_SPI_INIT_SEQ_DATA_A_0 */ 242 uint spi_init_seq_data_b; /* _DISP_SPI_INIT_SEQ_DATA_B_0 */ 243 uint spi_init_seq_data_c; /* _DISP_SPI_INIT_SEQ_DATA_C_0 */ 244 uint spi_init_seq_data_d; /* _DISP_SPI_INIT_SEQ_DATA_D_0 */ 245 246 uint reserved1[0x39]; /* reserved1[0x39], */ 247 248 /* Address 0x480 ~ 0x484 */ 249 uint dc_mccif_fifoctrl; /* _DISP_DC_MCCIF_FIFOCTRL_0 */ 250 uint mccif_disp0a_hyst; /* _DISP_MCCIF_DISPLAY0A_HYST_0 */ 251 uint mccif_disp0b_hyst; /* _DISP_MCCIF_DISPLAY0B_HYST_0 */ 252 uint mccif_disp0c_hyst; /* _DISP_MCCIF_DISPLAY0C_HYST_0 */ 253 uint mccif_disp1b_hyst; /* _DISP_MCCIF_DISPLAY1B_HYST_0 */ 254 255 uint reserved2[0x3b]; /* reserved2[0x3b] */ 256 257 /* Address 0x4c0 ~ 0x4c1 */ 258 uint dac_crt_ctrl; /* _DISP_DAC_CRT_CTRL_0 */ 259 uint disp_misc_ctrl; /* _DISP_DISP_MISC_CONTROL_0 */ 260 261 u32 rsvd_4c2[34]; /* 4c2 - 4e3 */ 262 263 /* Address 0x4e4 */ 264 u32 blend_background_color; /* _DISP_BLEND_BACKGROUND_COLOR_0 */ 265 }; 266 267 enum dc_winc_filter_p { 268 WINC_FILTER_COUNT = 0x10, 269 }; 270 271 /* Window A/B/C register 0x500 ~ 0x628 */ 272 struct dc_winc_reg { 273 274 /* Address 0x500 */ 275 uint color_palette; /* _WINC_COLOR_PALETTE_0 */ 276 277 uint reserved0[0xff]; /* reserved_0[0xff] */ 278 279 /* Address 0x600 */ 280 uint palette_color_ext; /* _WINC_PALETTE_COLOR_EXT_0 */ 281 282 /* _WINC_H_FILTER_P00~0F_0 */ 283 /* Address 0x601 ~ 0x610 */ 284 uint h_filter_p[WINC_FILTER_COUNT]; 285 286 /* Address 0x611 ~ 0x618 */ 287 uint csc_yof; /* _WINC_CSC_YOF_0 */ 288 uint csc_kyrgb; /* _WINC_CSC_KYRGB_0 */ 289 uint csc_kur; /* _WINC_CSC_KUR_0 */ 290 uint csc_kvr; /* _WINC_CSC_KVR_0 */ 291 uint csc_kug; /* _WINC_CSC_KUG_0 */ 292 uint csc_kvg; /* _WINC_CSC_KVG_0 */ 293 uint csc_kub; /* _WINC_CSC_KUB_0 */ 294 uint csc_kvb; /* _WINC_CSC_KVB_0 */ 295 296 /* Address 0x619 ~ 0x628: _WINC_V_FILTER_P00~0F_0 */ 297 uint v_filter_p[WINC_FILTER_COUNT]; 298 }; 299 300 /* WIN A/B/C Register 0x700 ~ 0x719*/ 301 struct dc_win_reg { 302 /* Address 0x700 ~ 0x719 */ 303 uint win_opt; /* _WIN_WIN_OPTIONS_0 */ 304 uint byte_swap; /* _WIN_BYTE_SWAP_0 */ 305 uint buffer_ctrl; /* _WIN_BUFFER_CONTROL_0 */ 306 uint color_depth; /* _WIN_COLOR_DEPTH_0 */ 307 uint pos; /* _WIN_POSITION_0 */ 308 uint size; /* _WIN_SIZE_0 */ 309 uint prescaled_size; /* _WIN_PRESCALED_SIZE_0 */ 310 uint h_initial_dda; /* _WIN_H_INITIAL_DDA_0 */ 311 uint v_initial_dda; /* _WIN_V_INITIAL_DDA_0 */ 312 uint dda_increment; /* _WIN_DDA_INCREMENT_0 */ 313 uint line_stride; /* _WIN_LINE_STRIDE_0 */ 314 uint buf_stride; /* _WIN_BUF_STRIDE_0 */ 315 uint uv_buf_stride; /* _WIN_UV_BUF_STRIDE_0 */ 316 uint buffer_addr_mode; /* _WIN_BUFFER_ADDR_MODE_0 */ 317 uint dv_ctrl; /* _WIN_DV_CONTROL_0 */ 318 uint blend_nokey; /* _WIN_BLEND_NOKEY_0 */ 319 uint blend_1win; /* _WIN_BLEND_1WIN_0 */ 320 uint blend_2win_x; /* _WIN_BLEND_2WIN_X_0 */ 321 uint blend_2win_y; /* _WIN_BLEND_2WIN_Y_0 */ 322 uint blend_3win_xy; /* _WIN_BLEND_3WIN_XY_0 */ 323 uint hp_fetch_ctrl; /* _WIN_HP_FETCH_CONTROL_0 */ 324 uint global_alpha; /* _WIN_GLOBAL_ALPHA */ 325 uint blend_layer_ctrl; /* _WINBUF_BLEND_LAYER_CONTROL_0 */ 326 uint blend_match_select; /* _WINBUF_BLEND_MATCH_SELECT_0 */ 327 uint blend_nomatch_select; /* _WINBUF_BLEND_NOMATCH_SELECT_0 */ 328 uint blend_alpha_1bit; /* _WINBUF_BLEND_ALPHA_1BIT_0 */ 329 }; 330 331 /* WINBUF A/B/C Register 0x800 ~ 0x80d */ 332 struct dc_winbuf_reg { 333 /* Address 0x800 ~ 0x80d */ 334 uint start_addr; /* _WINBUF_START_ADDR_0 */ 335 uint start_addr_ns; /* _WINBUF_START_ADDR_NS_0 */ 336 uint start_addr_u; /* _WINBUF_START_ADDR_U_0 */ 337 uint start_addr_u_ns; /* _WINBUF_START_ADDR_U_NS_0 */ 338 uint start_addr_v; /* _WINBUF_START_ADDR_V_0 */ 339 uint start_addr_v_ns; /* _WINBUF_START_ADDR_V_NS_0 */ 340 uint addr_h_offset; /* _WINBUF_ADDR_H_OFFSET_0 */ 341 uint addr_h_offset_ns; /* _WINBUF_ADDR_H_OFFSET_NS_0 */ 342 uint addr_v_offset; /* _WINBUF_ADDR_V_OFFSET_0 */ 343 uint addr_v_offset_ns; /* _WINBUF_ADDR_V_OFFSET_NS_0 */ 344 uint uflow_status; /* _WINBUF_UFLOW_STATUS_0 */ 345 uint buffer_surface_kind; /* DC_WIN_BUFFER_SURFACE_KIND */ 346 uint rsvd_80c; 347 uint start_addr_hi; /* DC_WINBUF_START_ADDR_HI_0 */ 348 }; 349 350 /* Display Controller (DC_) regs */ 351 struct dc_ctlr { 352 struct dc_cmd_reg cmd; /* CMD register 0x000 ~ 0x43 */ 353 uint reserved0[0x2bc]; 354 355 struct dc_com_reg com; /* COM register 0x300 ~ 0x329 */ 356 uint reserved1[0xd6]; 357 358 struct dc_disp_reg disp; /* DISP register 0x400 ~ 0x4e4 */ 359 uint reserved2[0x1b]; 360 361 struct dc_winc_reg winc; /* Window A/B/C 0x500 ~ 0x628 */ 362 uint reserved3[0xd7]; 363 364 struct dc_win_reg win; /* WIN A/B/C 0x700 ~ 0x719*/ 365 uint reserved4[0xe6]; 366 367 struct dc_winbuf_reg winbuf; /* WINBUF A/B/C 0x800 ~ 0x80d */ 368 }; 369 370 /* DC_CMD_DISPLAY_COMMAND 0x032 */ 371 #define CTRL_MODE_SHIFT 5 372 #define CTRL_MODE_MASK (0x3 << CTRL_MODE_SHIFT) 373 enum { 374 CTRL_MODE_STOP, 375 CTRL_MODE_C_DISPLAY, 376 CTRL_MODE_NC_DISPLAY, 377 }; 378 379 /* _WIN_COLOR_DEPTH_0 */ 380 enum win_color_depth_id { 381 COLOR_DEPTH_P1, 382 COLOR_DEPTH_P2, 383 COLOR_DEPTH_P4, 384 COLOR_DEPTH_P8, 385 COLOR_DEPTH_B4G4R4A4, 386 COLOR_DEPTH_B5G5R5A, 387 COLOR_DEPTH_B5G6R5, 388 COLOR_DEPTH_AB5G5R5, 389 COLOR_DEPTH_B8G8R8A8 = 12, 390 COLOR_DEPTH_R8G8B8A8, 391 COLOR_DEPTH_B6x2G6x2R6x2A8, 392 COLOR_DEPTH_R6x2G6x2B6x2A8, 393 COLOR_DEPTH_YCbCr422, 394 COLOR_DEPTH_YUV422, 395 COLOR_DEPTH_YCbCr420P, 396 COLOR_DEPTH_YUV420P, 397 COLOR_DEPTH_YCbCr422P, 398 COLOR_DEPTH_YUV422P, 399 COLOR_DEPTH_YCbCr422R, 400 COLOR_DEPTH_YUV422R, 401 COLOR_DEPTH_YCbCr422RA, 402 COLOR_DEPTH_YUV422RA, 403 }; 404 405 /* DC_CMD_DISPLAY_POWER_CONTROL 0x036 */ 406 #define PW0_ENABLE BIT(0) 407 #define PW1_ENABLE BIT(2) 408 #define PW2_ENABLE BIT(4) 409 #define PW3_ENABLE BIT(6) 410 #define PW4_ENABLE BIT(8) 411 #define PM0_ENABLE BIT(16) 412 #define PM1_ENABLE BIT(18) 413 #define SPI_ENABLE BIT(24) 414 #define HSPI_ENABLE BIT(25) 415 416 /* DC_CMD_STATE_ACCESS 0x040 */ 417 #define READ_MUX_ASSEMBLY (0 << 0) 418 #define READ_MUX_ACTIVE (1 << 0) 419 #define WRITE_MUX_ASSEMBLY (0 << 2) 420 #define WRITE_MUX_ACTIVE (1 << 2) 421 422 /* DC_CMD_STATE_CONTROL 0x041 */ 423 #define GENERAL_ACT_REQ BIT(0) 424 #define WIN_A_ACT_REQ BIT(1) 425 #define WIN_B_ACT_REQ BIT(2) 426 #define WIN_C_ACT_REQ BIT(3) 427 #define WIN_D_ACT_REQ BIT(4) 428 #define WIN_H_ACT_REQ BIT(5) 429 #define CURSOR_ACT_REQ BIT(7) 430 #define GENERAL_UPDATE BIT(8) 431 #define WIN_A_UPDATE BIT(9) 432 #define WIN_B_UPDATE BIT(10) 433 #define WIN_C_UPDATE BIT(11) 434 #define WIN_D_UPDATE BIT(12) 435 #define WIN_H_UPDATE BIT(13) 436 #define CURSOR_UPDATE BIT(15) 437 #define NC_HOST_TRIG BIT(24) 438 439 /* DC_CMD_DISPLAY_WINDOW_HEADER 0x042 */ 440 #define WINDOW_A_SELECT BIT(4) 441 #define WINDOW_B_SELECT BIT(5) 442 #define WINDOW_C_SELECT BIT(6) 443 #define WINDOW_D_SELECT BIT(7) 444 #define WINDOW_H_SELECT BIT(8) 445 446 /* DC_DISP_DISP_WIN_OPTIONS 0x402 */ 447 #define CURSOR_ENABLE BIT(16) 448 #define SOR_ENABLE BIT(25) 449 #define TVO_ENABLE BIT(28) 450 #define DSI_ENABLE BIT(29) 451 #define HDMI_ENABLE BIT(30) 452 453 /* DC_DISP_DISP_TIMING_OPTIONS 0x405 */ 454 #define VSYNC_H_POSITION(x) ((x) & 0xfff) 455 456 /* DC_DISP_DISP_CLOCK_CONTROL 0x42e */ 457 #define SHIFT_CLK_DIVIDER_SHIFT 0 458 #define SHIFT_CLK_DIVIDER_MASK (0xff << SHIFT_CLK_DIVIDER_SHIFT) 459 #define PIXEL_CLK_DIVIDER_SHIFT 8 460 #define PIXEL_CLK_DIVIDER_MSK (0xf << PIXEL_CLK_DIVIDER_SHIFT) 461 enum { 462 PIXEL_CLK_DIVIDER_PCD1, 463 PIXEL_CLK_DIVIDER_PCD1H, 464 PIXEL_CLK_DIVIDER_PCD2, 465 PIXEL_CLK_DIVIDER_PCD3, 466 PIXEL_CLK_DIVIDER_PCD4, 467 PIXEL_CLK_DIVIDER_PCD6, 468 PIXEL_CLK_DIVIDER_PCD8, 469 PIXEL_CLK_DIVIDER_PCD9, 470 PIXEL_CLK_DIVIDER_PCD12, 471 PIXEL_CLK_DIVIDER_PCD16, 472 PIXEL_CLK_DIVIDER_PCD18, 473 PIXEL_CLK_DIVIDER_PCD24, 474 PIXEL_CLK_DIVIDER_PCD13, 475 }; 476 477 /* DC_DISP_DISP_INTERFACE_CONTROL 0x42f */ 478 #define DATA_FORMAT_SHIFT 0 479 #define DATA_FORMAT_MASK (0xf << DATA_FORMAT_SHIFT) 480 enum { 481 DATA_FORMAT_DF1P1C, 482 DATA_FORMAT_DF1P2C24B, 483 DATA_FORMAT_DF1P2C18B, 484 DATA_FORMAT_DF1P2C16B, 485 DATA_FORMAT_DF2S, 486 DATA_FORMAT_DF3S, 487 DATA_FORMAT_DFSPI, 488 DATA_FORMAT_DF1P3C24B, 489 DATA_FORMAT_DF1P3C18B, 490 }; 491 #define DATA_ALIGNMENT_SHIFT 8 492 enum { 493 DATA_ALIGNMENT_MSB, 494 DATA_ALIGNMENT_LSB, 495 }; 496 #define DATA_ORDER_SHIFT 9 497 enum { 498 DATA_ORDER_RED_BLUE, 499 DATA_ORDER_BLUE_RED, 500 }; 501 502 /* DC_DISP_DATA_ENABLE_OPTIONS 0x432 */ 503 #define DE_SELECT_SHIFT 0 504 #define DE_SELECT_MASK (0x3 << DE_SELECT_SHIFT) 505 #define DE_SELECT_ACTIVE_BLANK 0x0 506 #define DE_SELECT_ACTIVE 0x1 507 #define DE_SELECT_ACTIVE_IS 0x2 508 #define DE_CONTROL_SHIFT 2 509 #define DE_CONTROL_MASK (0x7 << DE_CONTROL_SHIFT) 510 enum { 511 DE_CONTROL_ONECLK, 512 DE_CONTROL_NORMAL, 513 DE_CONTROL_EARLY_EXT, 514 DE_CONTROL_EARLY, 515 DE_CONTROL_ACTIVE_BLANK, 516 }; 517 518 /* DC_WIN_WIN_OPTIONS 0x700 */ 519 #define H_DIRECTION BIT(0) 520 enum { 521 H_DIRECTION_INCREMENT, 522 H_DIRECTION_DECREMENT, 523 }; 524 #define V_DIRECTION BIT(2) 525 enum { 526 V_DIRECTION_INCREMENT, 527 V_DIRECTION_DECREMENT, 528 }; 529 #define COLOR_EXPAND BIT(6) 530 #define CP_ENABLE BIT(16) 531 #define DV_ENABLE BIT(20) 532 #define WIN_ENABLE BIT(30) 533 534 /* DC_WIN_BYTE_SWAP 0x701 */ 535 #define BYTE_SWAP_SHIFT 0 536 #define BYTE_SWAP_MASK (3 << BYTE_SWAP_SHIFT) 537 enum { 538 BYTE_SWAP_NOSWAP, 539 BYTE_SWAP_SWAP2, 540 BYTE_SWAP_SWAP4, 541 BYTE_SWAP_SWAP4HW 542 }; 543 544 /* DC_WIN_POSITION 0x704 */ 545 #define H_POSITION_SHIFT 0 546 #define H_POSITION_MASK (0x1FFF << H_POSITION_SHIFT) 547 #define V_POSITION_SHIFT 16 548 #define V_POSITION_MASK (0x1FFF << V_POSITION_SHIFT) 549 550 /* DC_WIN_SIZE 0x705 */ 551 #define H_SIZE_SHIFT 0 552 #define H_SIZE_MASK (0x1FFF << H_SIZE_SHIFT) 553 #define V_SIZE_SHIFT 16 554 #define V_SIZE_MASK (0x1FFF << V_SIZE_SHIFT) 555 556 /* DC_WIN_PRESCALED_SIZE 0x706 */ 557 #define H_PRESCALED_SIZE_SHIFT 0 558 #define H_PRESCALED_SIZE_MASK (0x7FFF << H_PRESCALED_SIZE) 559 #define V_PRESCALED_SIZE_SHIFT 16 560 #define V_PRESCALED_SIZE_MASK (0x1FFF << V_PRESCALED_SIZE) 561 562 /* DC_WIN_DDA_INCREMENT 0x709 */ 563 #define H_DDA_INC_SHIFT 0 564 #define H_DDA_INC_MASK (0xFFFF << H_DDA_INC_SHIFT) 565 #define V_DDA_INC_SHIFT 16 566 #define V_DDA_INC_MASK (0xFFFF << V_DDA_INC_SHIFT) 567 568 #define DC_POLL_TIMEOUT_MS 50 569 #define DC_N_WINDOWS 5 570 #define DC_REG_SAVE_SPACE (DC_N_WINDOWS + 5) 571 572 #endif /* __ASM_ARCH_TEGRA_DC_H */ 573