1 /* SPDX-License-Identifier: GPL-2.0+ */
2 /*
3  * Freescale i.MX28 BCH Register Definitions
4  *
5  * Copyright (C) 2011 Marek Vasut <marek.vasut@gmail.com>
6  * on behalf of DENX Software Engineering GmbH
7  *
8  * Based on code from LTIB:
9  * Copyright 2008-2010, 2016 Freescale Semiconductor, Inc. All Rights Reserved.
10  * Copyright 2020 NXP
11  *
12  */
13 
14 #ifndef __MX28_REGS_BCH_H__
15 #define __MX28_REGS_BCH_H__
16 
17 #include <asm/mach-imx/regs-common.h>
18 
19 #ifndef	__ASSEMBLY__
20 struct mxs_bch_regs {
21 	mxs_reg_32(hw_bch_ctrl)
22 	mxs_reg_32(hw_bch_status0)
23 	mxs_reg_32(hw_bch_mode)
24 	mxs_reg_32(hw_bch_encodeptr)
25 	mxs_reg_32(hw_bch_dataptr)
26 	mxs_reg_32(hw_bch_metaptr)
27 
28 	uint32_t	reserved[4];
29 
30 	mxs_reg_32(hw_bch_layoutselect)
31 	mxs_reg_32(hw_bch_flash0layout0)
32 	mxs_reg_32(hw_bch_flash0layout1)
33 	mxs_reg_32(hw_bch_flash1layout0)
34 	mxs_reg_32(hw_bch_flash1layout1)
35 	mxs_reg_32(hw_bch_flash2layout0)
36 	mxs_reg_32(hw_bch_flash2layout1)
37 	mxs_reg_32(hw_bch_flash3layout0)
38 	mxs_reg_32(hw_bch_flash3layout1)
39 	mxs_reg_32(hw_bch_dbgkesread)
40 	mxs_reg_32(hw_bch_dbgcsferead)
41 	mxs_reg_32(hw_bch_dbgsyndegread)
42 	mxs_reg_32(hw_bch_dbgahbmread)
43 	mxs_reg_32(hw_bch_blockname)
44 	mxs_reg_32(hw_bch_version)
45 	mxs_reg_32(hw_bch_debug1)
46 };
47 #endif
48 
49 #define	BCH_CTRL_SFTRST					(1 << 31)
50 #define	BCH_CTRL_CLKGATE				(1 << 30)
51 #define	BCH_CTRL_DEBUGSYNDROME				(1 << 22)
52 #define	BCH_CTRL_M2M_LAYOUT_MASK			(0x3 << 18)
53 #define	BCH_CTRL_M2M_LAYOUT_OFFSET			18
54 #define	BCH_CTRL_M2M_ENCODE				(1 << 17)
55 #define	BCH_CTRL_M2M_ENABLE				(1 << 16)
56 #define	BCH_CTRL_DEBUG_STALL_IRQ_EN			(1 << 10)
57 #define	BCH_CTRL_COMPLETE_IRQ_EN			(1 << 8)
58 #define	BCH_CTRL_BM_ERROR_IRQ				(1 << 3)
59 #define	BCH_CTRL_DEBUG_STALL_IRQ			(1 << 2)
60 #define	BCH_CTRL_COMPLETE_IRQ				(1 << 0)
61 
62 #define	BCH_STATUS0_HANDLE_MASK				(0xfff << 20)
63 #define	BCH_STATUS0_HANDLE_OFFSET			20
64 #define	BCH_STATUS0_COMPLETED_CE_MASK			(0xf << 16)
65 #define	BCH_STATUS0_COMPLETED_CE_OFFSET			16
66 #define	BCH_STATUS0_STATUS_BLK0_MASK			(0xff << 8)
67 #define	BCH_STATUS0_STATUS_BLK0_OFFSET			8
68 #define	BCH_STATUS0_STATUS_BLK0_ZERO			(0x00 << 8)
69 #define	BCH_STATUS0_STATUS_BLK0_ERROR1			(0x01 << 8)
70 #define	BCH_STATUS0_STATUS_BLK0_ERROR2			(0x02 << 8)
71 #define	BCH_STATUS0_STATUS_BLK0_ERROR3			(0x03 << 8)
72 #define	BCH_STATUS0_STATUS_BLK0_ERROR4			(0x04 << 8)
73 #define	BCH_STATUS0_STATUS_BLK0_UNCORRECTABLE		(0xfe << 8)
74 #define	BCH_STATUS0_STATUS_BLK0_ERASED			(0xff << 8)
75 #define	BCH_STATUS0_ALLONES				(1 << 4)
76 #define	BCH_STATUS0_CORRECTED				(1 << 3)
77 #define	BCH_STATUS0_UNCORRECTABLE			(1 << 2)
78 
79 #define	BCH_MODE_ERASE_THRESHOLD_MASK			0xff
80 #define	BCH_MODE_ERASE_THRESHOLD_OFFSET			0
81 #define BCH_MODE_ERASE_THRESHOLD(v)			\
82 	(((v) << BCH_MODE_ERASE_THRESHOLD_OFFSET) &	\
83 	 BCH_MODE_ERASE_THRESHOLD_MASK)
84 
85 #define	BCH_ENCODEPTR_ADDR_MASK				0xffffffff
86 #define	BCH_ENCODEPTR_ADDR_OFFSET			0
87 
88 #define	BCH_DATAPTR_ADDR_MASK				0xffffffff
89 #define	BCH_DATAPTR_ADDR_OFFSET				0
90 
91 #define	BCH_METAPTR_ADDR_MASK				0xffffffff
92 #define	BCH_METAPTR_ADDR_OFFSET				0
93 
94 #define	BCH_LAYOUTSELECT_CS15_SELECT_MASK		(0x3 << 30)
95 #define	BCH_LAYOUTSELECT_CS15_SELECT_OFFSET		30
96 #define	BCH_LAYOUTSELECT_CS14_SELECT_MASK		(0x3 << 28)
97 #define	BCH_LAYOUTSELECT_CS14_SELECT_OFFSET		28
98 #define	BCH_LAYOUTSELECT_CS13_SELECT_MASK		(0x3 << 26)
99 #define	BCH_LAYOUTSELECT_CS13_SELECT_OFFSET		26
100 #define	BCH_LAYOUTSELECT_CS12_SELECT_MASK		(0x3 << 24)
101 #define	BCH_LAYOUTSELECT_CS12_SELECT_OFFSET		24
102 #define	BCH_LAYOUTSELECT_CS11_SELECT_MASK		(0x3 << 22)
103 #define	BCH_LAYOUTSELECT_CS11_SELECT_OFFSET		22
104 #define	BCH_LAYOUTSELECT_CS10_SELECT_MASK		(0x3 << 20)
105 #define	BCH_LAYOUTSELECT_CS10_SELECT_OFFSET		20
106 #define	BCH_LAYOUTSELECT_CS9_SELECT_MASK		(0x3 << 18)
107 #define	BCH_LAYOUTSELECT_CS9_SELECT_OFFSET		18
108 #define	BCH_LAYOUTSELECT_CS8_SELECT_MASK		(0x3 << 16)
109 #define	BCH_LAYOUTSELECT_CS8_SELECT_OFFSET		16
110 #define	BCH_LAYOUTSELECT_CS7_SELECT_MASK		(0x3 << 14)
111 #define	BCH_LAYOUTSELECT_CS7_SELECT_OFFSET		14
112 #define	BCH_LAYOUTSELECT_CS6_SELECT_MASK		(0x3 << 12)
113 #define	BCH_LAYOUTSELECT_CS6_SELECT_OFFSET		12
114 #define	BCH_LAYOUTSELECT_CS5_SELECT_MASK		(0x3 << 10)
115 #define	BCH_LAYOUTSELECT_CS5_SELECT_OFFSET		10
116 #define	BCH_LAYOUTSELECT_CS4_SELECT_MASK		(0x3 << 8)
117 #define	BCH_LAYOUTSELECT_CS4_SELECT_OFFSET		8
118 #define	BCH_LAYOUTSELECT_CS3_SELECT_MASK		(0x3 << 6)
119 #define	BCH_LAYOUTSELECT_CS3_SELECT_OFFSET		6
120 #define	BCH_LAYOUTSELECT_CS2_SELECT_MASK		(0x3 << 4)
121 #define	BCH_LAYOUTSELECT_CS2_SELECT_OFFSET		4
122 #define	BCH_LAYOUTSELECT_CS1_SELECT_MASK		(0x3 << 2)
123 #define	BCH_LAYOUTSELECT_CS1_SELECT_OFFSET		2
124 #define	BCH_LAYOUTSELECT_CS0_SELECT_MASK		(0x3 << 0)
125 #define	BCH_LAYOUTSELECT_CS0_SELECT_OFFSET		0
126 
127 #define	BCH_FLASHLAYOUT0_NBLOCKS_MASK			(0xff << 24)
128 #define	BCH_FLASHLAYOUT0_NBLOCKS_OFFSET			24
129 #define	BCH_FLASHLAYOUT0_META_SIZE_MASK			(0xff << 16)
130 #define	BCH_FLASHLAYOUT0_META_SIZE_OFFSET		16
131 #if (defined(CONFIG_MX6) || defined(CONFIG_MX7) || defined(CONFIG_IMX8) || defined(CONFIG_IMX8M))
132 #define	BCH_FLASHLAYOUT0_ECC0_MASK			(0x1f << 11)
133 #define	BCH_FLASHLAYOUT0_ECC0_OFFSET			11
134 #else
135 #define	BCH_FLASHLAYOUT0_ECC0_MASK			(0xf << 12)
136 #define	BCH_FLASHLAYOUT0_ECC0_OFFSET			12
137 #endif
138 #define	BCH_FLASHLAYOUT0_ECC0_NONE			(0x0 << 12)
139 #define	BCH_FLASHLAYOUT0_ECC0_ECC2			(0x1 << 12)
140 #define	BCH_FLASHLAYOUT0_ECC0_ECC4			(0x2 << 12)
141 #define	BCH_FLASHLAYOUT0_ECC0_ECC6			(0x3 << 12)
142 #define	BCH_FLASHLAYOUT0_ECC0_ECC8			(0x4 << 12)
143 #define	BCH_FLASHLAYOUT0_ECC0_ECC10			(0x5 << 12)
144 #define	BCH_FLASHLAYOUT0_ECC0_ECC12			(0x6 << 12)
145 #define	BCH_FLASHLAYOUT0_ECC0_ECC14			(0x7 << 12)
146 #define	BCH_FLASHLAYOUT0_ECC0_ECC16			(0x8 << 12)
147 #define	BCH_FLASHLAYOUT0_ECC0_ECC18			(0x9 << 12)
148 #define	BCH_FLASHLAYOUT0_ECC0_ECC20			(0xa << 12)
149 #define	BCH_FLASHLAYOUT0_ECC0_ECC22			(0xb << 12)
150 #define	BCH_FLASHLAYOUT0_ECC0_ECC24			(0xc << 12)
151 #define	BCH_FLASHLAYOUT0_ECC0_ECC26			(0xd << 12)
152 #define	BCH_FLASHLAYOUT0_ECC0_ECC28			(0xe << 12)
153 #define	BCH_FLASHLAYOUT0_ECC0_ECC30			(0xf << 12)
154 #define	BCH_FLASHLAYOUT0_ECC0_ECC32			(0x10 << 12)
155 #define	BCH_FLASHLAYOUT0_GF13_0_GF14_1_MASK		BIT(10)
156 #define	BCH_FLASHLAYOUT0_GF13_0_GF14_1_OFFSET		10
157 #define	BCH_FLASHLAYOUT0_DATA0_SIZE_MASK		0x3ff
158 #define	BCH_FLASHLAYOUT0_DATA0_SIZE_OFFSET		0
159 
160 #define	BCH_FLASHLAYOUT1_PAGE_SIZE_MASK			(0xffff << 16)
161 #define	BCH_FLASHLAYOUT1_PAGE_SIZE_OFFSET		16
162 #if (defined(CONFIG_MX6) || defined(CONFIG_MX7) || defined(CONFIG_IMX8) || defined(CONFIG_IMX8M))
163 #define	BCH_FLASHLAYOUT1_ECCN_MASK			(0x1f << 11)
164 #define	BCH_FLASHLAYOUT1_ECCN_OFFSET			11
165 #else
166 #define	BCH_FLASHLAYOUT1_ECCN_MASK			(0xf << 12)
167 #define	BCH_FLASHLAYOUT1_ECCN_OFFSET			12
168 #endif
169 #define	BCH_FLASHLAYOUT1_ECCN_NONE			(0x0 << 12)
170 #define	BCH_FLASHLAYOUT1_ECCN_ECC2			(0x1 << 12)
171 #define	BCH_FLASHLAYOUT1_ECCN_ECC4			(0x2 << 12)
172 #define	BCH_FLASHLAYOUT1_ECCN_ECC6			(0x3 << 12)
173 #define	BCH_FLASHLAYOUT1_ECCN_ECC8			(0x4 << 12)
174 #define	BCH_FLASHLAYOUT1_ECCN_ECC10			(0x5 << 12)
175 #define	BCH_FLASHLAYOUT1_ECCN_ECC12			(0x6 << 12)
176 #define	BCH_FLASHLAYOUT1_ECCN_ECC14			(0x7 << 12)
177 #define	BCH_FLASHLAYOUT1_ECCN_ECC16			(0x8 << 12)
178 #define	BCH_FLASHLAYOUT1_ECCN_ECC18			(0x9 << 12)
179 #define	BCH_FLASHLAYOUT1_ECCN_ECC20			(0xa << 12)
180 #define	BCH_FLASHLAYOUT1_ECCN_ECC22			(0xb << 12)
181 #define	BCH_FLASHLAYOUT1_ECCN_ECC24			(0xc << 12)
182 #define	BCH_FLASHLAYOUT1_ECCN_ECC26			(0xd << 12)
183 #define	BCH_FLASHLAYOUT1_ECCN_ECC28			(0xe << 12)
184 #define	BCH_FLASHLAYOUT1_ECCN_ECC30			(0xf << 12)
185 #define	BCH_FLASHLAYOUT1_ECCN_ECC32			(0x10 << 12)
186 #define	BCH_FLASHLAYOUT1_GF13_0_GF14_1_MASK		BIT(10)
187 #define	BCH_FLASHLAYOUT1_GF13_0_GF14_1_OFFSET		10
188 #define	BCH_FLASHLAYOUT1_DATAN_SIZE_MASK		0x3ff
189 #define	BCH_FLASHLAYOUT1_DATAN_SIZE_OFFSET		0
190 
191 #define	BCH_DEBUG0_RSVD1_MASK				(0x1f << 27)
192 #define	BCH_DEBUG0_RSVD1_OFFSET				27
193 #define	BCH_DEBUG0_ROM_BIST_ENABLE			(1 << 26)
194 #define	BCH_DEBUG0_ROM_BIST_COMPLETE			(1 << 25)
195 #define	BCH_DEBUG0_KES_DEBUG_SYNDROME_SYMBOL_MASK	(0x1ff << 16)
196 #define	BCH_DEBUG0_KES_DEBUG_SYNDROME_SYMBOL_OFFSET	16
197 #define	BCH_DEBUG0_KES_DEBUG_SYNDROME_SYMBOL_NORMAL	(0x0 << 16)
198 #define	BCH_DEBUG0_KES_DEBUG_SYNDROME_SYMBOL_TEST_MODE	(0x1 << 16)
199 #define	BCH_DEBUG0_KES_DEBUG_SHIFT_SYND			(1 << 15)
200 #define	BCH_DEBUG0_KES_DEBUG_PAYLOAD_FLAG		(1 << 14)
201 #define	BCH_DEBUG0_KES_DEBUG_MODE4K			(1 << 13)
202 #define	BCH_DEBUG0_KES_DEBUG_KICK			(1 << 12)
203 #define	BCH_DEBUG0_KES_STANDALONE			(1 << 11)
204 #define	BCH_DEBUG0_KES_DEBUG_STEP			(1 << 10)
205 #define	BCH_DEBUG0_KES_DEBUG_STALL			(1 << 9)
206 #define	BCH_DEBUG0_BM_KES_TEST_BYPASS			(1 << 8)
207 #define	BCH_DEBUG0_RSVD0_MASK				(0x3 << 6)
208 #define	BCH_DEBUG0_RSVD0_OFFSET				6
209 #define	BCH_DEBUG0_DEBUG_REG_SELECT_MASK		0x3f
210 #define	BCH_DEBUG0_DEBUG_REG_SELECT_OFFSET		0
211 
212 #define	BCH_DBGKESREAD_VALUES_MASK			0xffffffff
213 #define	BCH_DBGKESREAD_VALUES_OFFSET			0
214 
215 #define	BCH_DBGCSFEREAD_VALUES_MASK			0xffffffff
216 #define	BCH_DBGCSFEREAD_VALUES_OFFSET			0
217 
218 #define	BCH_DBGSYNDGENREAD_VALUES_MASK			0xffffffff
219 #define	BCH_DBGSYNDGENREAD_VALUES_OFFSET		0
220 
221 #define	BCH_DBGAHBMREAD_VALUES_MASK			0xffffffff
222 #define	BCH_DBGAHBMREAD_VALUES_OFFSET			0
223 
224 #define	BCH_BLOCKNAME_NAME_MASK				0xffffffff
225 #define	BCH_BLOCKNAME_NAME_OFFSET			0
226 
227 #define	BCH_VERSION_MAJOR_MASK				(0xff << 24)
228 #define	BCH_VERSION_MAJOR_OFFSET			24
229 #define	BCH_VERSION_MINOR_MASK				(0xff << 16)
230 #define	BCH_VERSION_MINOR_OFFSET			16
231 #define	BCH_VERSION_STEP_MASK				0xffff
232 #define	BCH_VERSION_STEP_OFFSET				0
233 
234 #endif	/* __MX28_REGS_BCH_H__ */
235