1 // SPDX-License-Identifier: GPL-2.0
2 /*
3 * (C) Copyright 2012 Stephen Warren
4 *
5 * See file CREDITS for list of people who contributed to this
6 * project.
7 */
8
9 #include <common.h>
10 #include <cpu_func.h>
11 #include <init.h>
12 #include <dm/device.h>
13 #include <fdt_support.h>
14 #include <asm/global_data.h>
15
16 #define BCM2711_RPI4_PCIE_XHCI_MMIO_PHYS 0x600000000UL
17 #define BCM2711_RPI4_PCIE_XHCI_MMIO_SIZE 0x800000UL
18
19 #ifdef CONFIG_ARM64
20 #include <asm/armv8/mmu.h>
21
22 #define MEM_MAP_MAX_ENTRIES (4)
23
24 static struct mm_region bcm283x_mem_map[MEM_MAP_MAX_ENTRIES] = {
25 {
26 .virt = 0x00000000UL,
27 .phys = 0x00000000UL,
28 .size = 0x3f000000UL,
29 .attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL) |
30 PTE_BLOCK_INNER_SHARE
31 }, {
32 .virt = 0x3f000000UL,
33 .phys = 0x3f000000UL,
34 .size = 0x01000000UL,
35 .attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
36 PTE_BLOCK_NON_SHARE |
37 PTE_BLOCK_PXN | PTE_BLOCK_UXN
38 }, {
39 /* List terminator */
40 0,
41 }
42 };
43
44 static struct mm_region bcm2711_mem_map[MEM_MAP_MAX_ENTRIES] = {
45 {
46 .virt = 0x00000000UL,
47 .phys = 0x00000000UL,
48 .size = 0xfc000000UL,
49 .attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL) |
50 PTE_BLOCK_INNER_SHARE
51 }, {
52 .virt = 0xfc000000UL,
53 .phys = 0xfc000000UL,
54 .size = 0x03800000UL,
55 .attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
56 PTE_BLOCK_NON_SHARE |
57 PTE_BLOCK_PXN | PTE_BLOCK_UXN
58 }, {
59 .virt = BCM2711_RPI4_PCIE_XHCI_MMIO_PHYS,
60 .phys = BCM2711_RPI4_PCIE_XHCI_MMIO_PHYS,
61 .size = BCM2711_RPI4_PCIE_XHCI_MMIO_SIZE,
62 .attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
63 PTE_BLOCK_NON_SHARE |
64 PTE_BLOCK_PXN | PTE_BLOCK_UXN
65 }, {
66 /* List terminator */
67 0,
68 }
69 };
70
71 struct mm_region *mem_map = bcm283x_mem_map;
72
73 /*
74 * I/O address space varies on different chip versions.
75 * We set the base address by inspecting the DTB.
76 */
77 static const struct udevice_id board_ids[] = {
78 { .compatible = "brcm,bcm2837", .data = (ulong)&bcm283x_mem_map},
79 { .compatible = "brcm,bcm2838", .data = (ulong)&bcm2711_mem_map},
80 { .compatible = "brcm,bcm2711", .data = (ulong)&bcm2711_mem_map},
81 { },
82 };
83
_rpi_update_mem_map(struct mm_region * pd)84 static void _rpi_update_mem_map(struct mm_region *pd)
85 {
86 int i;
87
88 for (i = 0; i < MEM_MAP_MAX_ENTRIES; i++) {
89 mem_map[i].virt = pd[i].virt;
90 mem_map[i].phys = pd[i].phys;
91 mem_map[i].size = pd[i].size;
92 mem_map[i].attrs = pd[i].attrs;
93 }
94 }
95
rpi_update_mem_map(void)96 static void rpi_update_mem_map(void)
97 {
98 int ret;
99 struct mm_region *mm;
100 const struct udevice_id *of_match = board_ids;
101
102 while (of_match->compatible) {
103 ret = fdt_node_check_compatible(gd->fdt_blob, 0,
104 of_match->compatible);
105 if (!ret) {
106 mm = (struct mm_region *)of_match->data;
107 _rpi_update_mem_map(mm);
108 break;
109 }
110
111 of_match++;
112 }
113 }
114 #else
rpi_update_mem_map(void)115 static void rpi_update_mem_map(void) {}
116 #endif
117
118 unsigned long rpi_bcm283x_base = 0x3f000000;
119
arch_cpu_init(void)120 int arch_cpu_init(void)
121 {
122 icache_enable();
123
124 return 0;
125 }
126
mach_cpu_init(void)127 int mach_cpu_init(void)
128 {
129 int ret, soc_offset;
130 u64 io_base, size;
131
132 rpi_update_mem_map();
133
134 /* Get IO base from device tree */
135 soc_offset = fdt_path_offset(gd->fdt_blob, "/soc");
136 if (soc_offset < 0)
137 return soc_offset;
138
139 ret = fdt_read_range((void *)gd->fdt_blob, soc_offset, 0, NULL,
140 &io_base, &size);
141 if (ret)
142 return ret;
143
144 rpi_bcm283x_base = io_base;
145
146 return 0;
147 }
148
149 #ifdef CONFIG_ARMV7_LPAE
150 #ifdef CONFIG_TARGET_RPI_4_32B
151 #define BCM2711_RPI4_PCIE_XHCI_MMIO_VIRT 0xff800000UL
152 #include <addr_map.h>
153 #include <asm/system.h>
154
init_addr_map(void)155 void init_addr_map(void)
156 {
157 mmu_set_region_dcache_behaviour_phys(BCM2711_RPI4_PCIE_XHCI_MMIO_VIRT,
158 BCM2711_RPI4_PCIE_XHCI_MMIO_PHYS,
159 BCM2711_RPI4_PCIE_XHCI_MMIO_SIZE,
160 DCACHE_OFF);
161
162 /* identity mapping for 0..BCM2711_RPI4_PCIE_XHCI_MMIO_VIRT */
163 addrmap_set_entry(0, 0, BCM2711_RPI4_PCIE_XHCI_MMIO_VIRT, 0);
164 /* XHCI MMIO on PCIe at BCM2711_RPI4_PCIE_XHCI_MMIO_VIRT */
165 addrmap_set_entry(BCM2711_RPI4_PCIE_XHCI_MMIO_VIRT,
166 BCM2711_RPI4_PCIE_XHCI_MMIO_PHYS,
167 BCM2711_RPI4_PCIE_XHCI_MMIO_SIZE, 1);
168 }
169 #endif
170
enable_caches(void)171 void enable_caches(void)
172 {
173 dcache_enable();
174 }
175 #endif
176