1 // SPDX-License-Identifier: GPL-2.0+
2 /*
3 * Copyright 2018-2019 NXP
4 *
5 * Peng Fan <peng.fan@nxp.com>
6 */
7
8 #include <common.h>
9 #include <asm/arch/clock.h>
10 #include <asm/arch/imx-regs.h>
11 #include <asm/arch/sys_proto.h>
12 #include <asm/global_data.h>
13 #include <asm/io.h>
14 #include <div64.h>
15 #include <errno.h>
16 #include <linux/bitops.h>
17 #include <linux/delay.h>
18
19 DECLARE_GLOBAL_DATA_PTR;
20
21 static struct anamix_pll *ana_pll = (struct anamix_pll *)ANATOP_BASE_ADDR;
22
23 static u32 get_root_clk(enum clk_root_index clock_id);
enable_ocotp_clk(unsigned char enable)24 void enable_ocotp_clk(unsigned char enable)
25 {
26 clock_enable(CCGR_OCOTP, !!enable);
27 }
28
enable_i2c_clk(unsigned char enable,unsigned i2c_num)29 int enable_i2c_clk(unsigned char enable, unsigned i2c_num)
30 {
31 /* 0 - 3 is valid i2c num */
32 if (i2c_num > 3)
33 return -EINVAL;
34
35 clock_enable(CCGR_I2C1 + i2c_num, !!enable);
36
37 return 0;
38 }
39
40 #ifdef CONFIG_SPL_BUILD
41 static struct imx_int_pll_rate_table imx8mm_fracpll_tbl[] = {
42 PLL_1443X_RATE(1000000000U, 250, 3, 1, 0),
43 PLL_1443X_RATE(800000000U, 300, 9, 0, 0),
44 PLL_1443X_RATE(750000000U, 250, 8, 0, 0),
45 PLL_1443X_RATE(650000000U, 325, 3, 2, 0),
46 PLL_1443X_RATE(600000000U, 300, 3, 2, 0),
47 PLL_1443X_RATE(594000000U, 99, 1, 2, 0),
48 PLL_1443X_RATE(400000000U, 300, 9, 1, 0),
49 PLL_1443X_RATE(266666667U, 400, 9, 2, 0),
50 PLL_1443X_RATE(167000000U, 334, 3, 4, 0),
51 PLL_1443X_RATE(100000000U, 300, 9, 3, 0),
52 };
53
fracpll_configure(enum pll_clocks pll,u32 freq)54 static int fracpll_configure(enum pll_clocks pll, u32 freq)
55 {
56 int i;
57 u32 tmp, div_val;
58 void *pll_base;
59 struct imx_int_pll_rate_table *rate;
60
61 for (i = 0; i < ARRAY_SIZE(imx8mm_fracpll_tbl); i++) {
62 if (freq == imx8mm_fracpll_tbl[i].rate)
63 break;
64 }
65
66 if (i == ARRAY_SIZE(imx8mm_fracpll_tbl)) {
67 printf("No matched freq table %u\n", freq);
68 return -EINVAL;
69 }
70
71 rate = &imx8mm_fracpll_tbl[i];
72
73 switch (pll) {
74 case ANATOP_DRAM_PLL:
75 setbits_le32(GPC_BASE_ADDR + 0xEC, 1 << 7);
76 setbits_le32(GPC_BASE_ADDR + 0xF8, 1 << 5);
77 writel(SRC_DDR1_ENABLE_MASK, SRC_BASE_ADDR + 0x1004);
78
79 pll_base = &ana_pll->dram_pll_gnrl_ctl;
80 break;
81 case ANATOP_VIDEO_PLL:
82 pll_base = &ana_pll->video_pll1_gnrl_ctl;
83 break;
84 default:
85 return 0;
86 }
87 /* Bypass clock and set lock to pll output lock */
88 tmp = readl(pll_base);
89 tmp |= BYPASS_MASK;
90 writel(tmp, pll_base);
91
92 /* Enable RST */
93 tmp &= ~RST_MASK;
94 writel(tmp, pll_base);
95
96 div_val = (rate->mdiv << MDIV_SHIFT) | (rate->pdiv << PDIV_SHIFT) |
97 (rate->sdiv << SDIV_SHIFT);
98 writel(div_val, pll_base + 4);
99 writel(rate->kdiv << KDIV_SHIFT, pll_base + 8);
100
101 __udelay(100);
102
103 /* Disable RST */
104 tmp |= RST_MASK;
105 writel(tmp, pll_base);
106
107 /* Wait Lock*/
108 while (!(readl(pll_base) & LOCK_STATUS))
109 ;
110
111 /* Bypass */
112 tmp &= ~BYPASS_MASK;
113 writel(tmp, pll_base);
114
115 return 0;
116 }
117
dram_pll_init(ulong pll_val)118 void dram_pll_init(ulong pll_val)
119 {
120 fracpll_configure(ANATOP_DRAM_PLL, pll_val);
121 }
122
123 static struct dram_bypass_clk_setting imx8mm_dram_bypass_tbl[] = {
124 DRAM_BYPASS_ROOT_CONFIG(MHZ(100), 2, CLK_ROOT_PRE_DIV1, 2,
125 CLK_ROOT_PRE_DIV2),
126 DRAM_BYPASS_ROOT_CONFIG(MHZ(250), 3, CLK_ROOT_PRE_DIV2, 2,
127 CLK_ROOT_PRE_DIV2),
128 DRAM_BYPASS_ROOT_CONFIG(MHZ(400), 1, CLK_ROOT_PRE_DIV2, 3,
129 CLK_ROOT_PRE_DIV2),
130 };
131
dram_enable_bypass(ulong clk_val)132 void dram_enable_bypass(ulong clk_val)
133 {
134 int i;
135 struct dram_bypass_clk_setting *config;
136
137 for (i = 0; i < ARRAY_SIZE(imx8mm_dram_bypass_tbl); i++) {
138 if (clk_val == imx8mm_dram_bypass_tbl[i].clk)
139 break;
140 }
141
142 if (i == ARRAY_SIZE(imx8mm_dram_bypass_tbl)) {
143 printf("No matched freq table %lu\n", clk_val);
144 return;
145 }
146
147 config = &imx8mm_dram_bypass_tbl[i];
148
149 clock_set_target_val(DRAM_ALT_CLK_ROOT, CLK_ROOT_ON |
150 CLK_ROOT_SOURCE_SEL(config->alt_root_sel) |
151 CLK_ROOT_PRE_DIV(config->alt_pre_div));
152 clock_set_target_val(DRAM_APB_CLK_ROOT, CLK_ROOT_ON |
153 CLK_ROOT_SOURCE_SEL(config->apb_root_sel) |
154 CLK_ROOT_PRE_DIV(config->apb_pre_div));
155 clock_set_target_val(DRAM_SEL_CFG, CLK_ROOT_ON |
156 CLK_ROOT_SOURCE_SEL(1));
157 }
158
dram_disable_bypass(void)159 void dram_disable_bypass(void)
160 {
161 clock_set_target_val(DRAM_SEL_CFG, CLK_ROOT_ON |
162 CLK_ROOT_SOURCE_SEL(0));
163 clock_set_target_val(DRAM_APB_CLK_ROOT, CLK_ROOT_ON |
164 CLK_ROOT_SOURCE_SEL(4) |
165 CLK_ROOT_PRE_DIV(CLK_ROOT_PRE_DIV5));
166 }
167 #endif
168
intpll_configure(enum pll_clocks pll,ulong freq)169 int intpll_configure(enum pll_clocks pll, ulong freq)
170 {
171 void __iomem *pll_gnrl_ctl, __iomem *pll_div_ctl;
172 u32 pll_div_ctl_val, pll_clke_masks;
173
174 switch (pll) {
175 case ANATOP_SYSTEM_PLL1:
176 pll_gnrl_ctl = &ana_pll->sys_pll1_gnrl_ctl;
177 pll_div_ctl = &ana_pll->sys_pll1_div_ctl;
178 pll_clke_masks = INTPLL_DIV20_CLKE_MASK |
179 INTPLL_DIV10_CLKE_MASK | INTPLL_DIV8_CLKE_MASK |
180 INTPLL_DIV6_CLKE_MASK | INTPLL_DIV5_CLKE_MASK |
181 INTPLL_DIV4_CLKE_MASK | INTPLL_DIV3_CLKE_MASK |
182 INTPLL_DIV2_CLKE_MASK | INTPLL_CLKE_MASK;
183 break;
184 case ANATOP_SYSTEM_PLL2:
185 pll_gnrl_ctl = &ana_pll->sys_pll2_gnrl_ctl;
186 pll_div_ctl = &ana_pll->sys_pll2_div_ctl;
187 pll_clke_masks = INTPLL_DIV20_CLKE_MASK |
188 INTPLL_DIV10_CLKE_MASK | INTPLL_DIV8_CLKE_MASK |
189 INTPLL_DIV6_CLKE_MASK | INTPLL_DIV5_CLKE_MASK |
190 INTPLL_DIV4_CLKE_MASK | INTPLL_DIV3_CLKE_MASK |
191 INTPLL_DIV2_CLKE_MASK | INTPLL_CLKE_MASK;
192 break;
193 case ANATOP_SYSTEM_PLL3:
194 pll_gnrl_ctl = &ana_pll->sys_pll3_gnrl_ctl;
195 pll_div_ctl = &ana_pll->sys_pll3_div_ctl;
196 pll_clke_masks = INTPLL_CLKE_MASK;
197 break;
198 case ANATOP_ARM_PLL:
199 pll_gnrl_ctl = &ana_pll->arm_pll_gnrl_ctl;
200 pll_div_ctl = &ana_pll->arm_pll_div_ctl;
201 pll_clke_masks = INTPLL_CLKE_MASK;
202 break;
203 case ANATOP_GPU_PLL:
204 pll_gnrl_ctl = &ana_pll->gpu_pll_gnrl_ctl;
205 pll_div_ctl = &ana_pll->gpu_pll_div_ctl;
206 pll_clke_masks = INTPLL_CLKE_MASK;
207 break;
208 case ANATOP_VPU_PLL:
209 pll_gnrl_ctl = &ana_pll->vpu_pll_gnrl_ctl;
210 pll_div_ctl = &ana_pll->vpu_pll_div_ctl;
211 pll_clke_masks = INTPLL_CLKE_MASK;
212 break;
213 default:
214 return -EINVAL;
215 };
216
217 switch (freq) {
218 case MHZ(600):
219 /* 24 * 0x12c / 3 / 2 ^ 2 */
220 pll_div_ctl_val = INTPLL_MAIN_DIV_VAL(0x12c) |
221 INTPLL_PRE_DIV_VAL(3) | INTPLL_POST_DIV_VAL(2);
222 break;
223 case MHZ(750):
224 /* 24 * 0xfa / 2 / 2 ^ 2 */
225 pll_div_ctl_val = INTPLL_MAIN_DIV_VAL(0xfa) |
226 INTPLL_PRE_DIV_VAL(2) | INTPLL_POST_DIV_VAL(2);
227 break;
228 case MHZ(800):
229 /* 24 * 0x190 / 3 / 2 ^ 2 */
230 pll_div_ctl_val = INTPLL_MAIN_DIV_VAL(0x190) |
231 INTPLL_PRE_DIV_VAL(3) | INTPLL_POST_DIV_VAL(2);
232 break;
233 case MHZ(1000):
234 /* 24 * 0xfa / 3 / 2 ^ 1 */
235 pll_div_ctl_val = INTPLL_MAIN_DIV_VAL(0xfa) |
236 INTPLL_PRE_DIV_VAL(3) | INTPLL_POST_DIV_VAL(1);
237 break;
238 case MHZ(1200):
239 /* 24 * 0xc8 / 2 / 2 ^ 1 */
240 pll_div_ctl_val = INTPLL_MAIN_DIV_VAL(0xc8) |
241 INTPLL_PRE_DIV_VAL(2) | INTPLL_POST_DIV_VAL(1);
242 break;
243 case MHZ(2000):
244 /* 24 * 0xfa / 3 / 2 ^ 0 */
245 pll_div_ctl_val = INTPLL_MAIN_DIV_VAL(0xfa) |
246 INTPLL_PRE_DIV_VAL(3) | INTPLL_POST_DIV_VAL(0);
247 break;
248 default:
249 return -EINVAL;
250 };
251 /* Bypass clock and set lock to pll output lock */
252 setbits_le32(pll_gnrl_ctl, INTPLL_BYPASS_MASK | INTPLL_LOCK_SEL_MASK);
253 /* Enable reset */
254 clrbits_le32(pll_gnrl_ctl, INTPLL_RST_MASK);
255 /* Configure */
256 writel(pll_div_ctl_val, pll_div_ctl);
257
258 __udelay(100);
259
260 /* Disable reset */
261 setbits_le32(pll_gnrl_ctl, INTPLL_RST_MASK);
262 /* Wait Lock */
263 while (!(readl(pll_gnrl_ctl) & INTPLL_LOCK_MASK))
264 ;
265 /* Clear bypass */
266 clrbits_le32(pll_gnrl_ctl, INTPLL_BYPASS_MASK);
267 setbits_le32(pll_gnrl_ctl, pll_clke_masks);
268
269 return 0;
270 }
271
init_uart_clk(u32 index)272 void init_uart_clk(u32 index)
273 {
274 /*
275 * set uart clock root
276 * 24M OSC
277 */
278 switch (index) {
279 case 0:
280 clock_enable(CCGR_UART1, 0);
281 clock_set_target_val(UART1_CLK_ROOT, CLK_ROOT_ON |
282 CLK_ROOT_SOURCE_SEL(0));
283 clock_enable(CCGR_UART1, 1);
284 return;
285 case 1:
286 clock_enable(CCGR_UART2, 0);
287 clock_set_target_val(UART2_CLK_ROOT, CLK_ROOT_ON |
288 CLK_ROOT_SOURCE_SEL(0));
289 clock_enable(CCGR_UART2, 1);
290 return;
291 case 2:
292 clock_enable(CCGR_UART3, 0);
293 clock_set_target_val(UART3_CLK_ROOT, CLK_ROOT_ON |
294 CLK_ROOT_SOURCE_SEL(0));
295 clock_enable(CCGR_UART3, 1);
296 return;
297 case 3:
298 clock_enable(CCGR_UART4, 0);
299 clock_set_target_val(UART4_CLK_ROOT, CLK_ROOT_ON |
300 CLK_ROOT_SOURCE_SEL(0));
301 clock_enable(CCGR_UART4, 1);
302 return;
303 default:
304 printf("Invalid uart index\n");
305 return;
306 }
307 }
308
init_wdog_clk(void)309 void init_wdog_clk(void)
310 {
311 clock_enable(CCGR_WDOG1, 0);
312 clock_enable(CCGR_WDOG2, 0);
313 clock_enable(CCGR_WDOG3, 0);
314 clock_set_target_val(WDOG_CLK_ROOT, CLK_ROOT_ON |
315 CLK_ROOT_SOURCE_SEL(0));
316 clock_enable(CCGR_WDOG1, 1);
317 clock_enable(CCGR_WDOG2, 1);
318 clock_enable(CCGR_WDOG3, 1);
319 }
320
init_clk_usdhc(u32 index)321 void init_clk_usdhc(u32 index)
322 {
323 /*
324 * set usdhc clock root
325 * sys pll1 400M
326 */
327 switch (index) {
328 case 0:
329 clock_enable(CCGR_USDHC1, 0);
330 clock_set_target_val(USDHC1_CLK_ROOT, CLK_ROOT_ON |
331 CLK_ROOT_SOURCE_SEL(1));
332 clock_enable(CCGR_USDHC1, 1);
333 return;
334 case 1:
335 clock_enable(CCGR_USDHC2, 0);
336 clock_set_target_val(USDHC2_CLK_ROOT, CLK_ROOT_ON |
337 CLK_ROOT_SOURCE_SEL(1));
338 clock_enable(CCGR_USDHC2, 1);
339 return;
340 case 2:
341 clock_enable(CCGR_USDHC3, 0);
342 clock_set_target_val(USDHC3_CLK_ROOT, CLK_ROOT_ON |
343 CLK_ROOT_SOURCE_SEL(1));
344 clock_enable(CCGR_USDHC3, 1);
345 return;
346 default:
347 printf("Invalid usdhc index\n");
348 return;
349 }
350 }
351
init_clk_ecspi(u32 index)352 void init_clk_ecspi(u32 index)
353 {
354 switch (index) {
355 case 0:
356 clock_enable(CCGR_ECSPI1, 0);
357 clock_set_target_val(ECSPI1_CLK_ROOT, CLK_ROOT_ON | CLK_ROOT_SOURCE_SEL(0));
358 clock_enable(CCGR_ECSPI1, 1);
359 return;
360 case 1:
361 clock_enable(CCGR_ECSPI2, 0);
362 clock_set_target_val(ECSPI2_CLK_ROOT, CLK_ROOT_ON | CLK_ROOT_SOURCE_SEL(0));
363 clock_enable(CCGR_ECSPI2, 1);
364 return;
365 case 2:
366 clock_enable(CCGR_ECSPI3, 0);
367 clock_set_target_val(ECSPI3_CLK_ROOT, CLK_ROOT_ON | CLK_ROOT_SOURCE_SEL(0));
368 clock_enable(CCGR_ECSPI3, 1);
369 return;
370 default:
371 printf("Invalid ecspi index\n");
372 return;
373 }
374 }
375
init_nand_clk(void)376 void init_nand_clk(void)
377 {
378 /*
379 * set rawnand root
380 * sys pll1 400M
381 */
382 clock_enable(CCGR_RAWNAND, 0);
383 clock_set_target_val(NAND_CLK_ROOT, CLK_ROOT_ON |
384 CLK_ROOT_SOURCE_SEL(3) | CLK_ROOT_POST_DIV(CLK_ROOT_POST_DIV4)); /* 100M */
385 clock_enable(CCGR_RAWNAND, 1);
386 }
387
clock_init(void)388 int clock_init(void)
389 {
390 u32 val_cfg0;
391
392 /*
393 * The gate is not exported to clk tree, so configure them here.
394 * According to ANAMIX SPEC
395 * sys pll1 fixed at 800MHz
396 * sys pll2 fixed at 1GHz
397 * Here we only enable the outputs.
398 */
399 val_cfg0 = readl(&ana_pll->sys_pll1_gnrl_ctl);
400 val_cfg0 |= INTPLL_CLKE_MASK | INTPLL_DIV2_CLKE_MASK |
401 INTPLL_DIV3_CLKE_MASK | INTPLL_DIV4_CLKE_MASK |
402 INTPLL_DIV5_CLKE_MASK | INTPLL_DIV6_CLKE_MASK |
403 INTPLL_DIV8_CLKE_MASK | INTPLL_DIV10_CLKE_MASK |
404 INTPLL_DIV20_CLKE_MASK;
405 writel(val_cfg0, &ana_pll->sys_pll1_gnrl_ctl);
406
407 val_cfg0 = readl(&ana_pll->sys_pll2_gnrl_ctl);
408 val_cfg0 |= INTPLL_CLKE_MASK | INTPLL_DIV2_CLKE_MASK |
409 INTPLL_DIV3_CLKE_MASK | INTPLL_DIV4_CLKE_MASK |
410 INTPLL_DIV5_CLKE_MASK | INTPLL_DIV6_CLKE_MASK |
411 INTPLL_DIV8_CLKE_MASK | INTPLL_DIV10_CLKE_MASK |
412 INTPLL_DIV20_CLKE_MASK;
413 writel(val_cfg0, &ana_pll->sys_pll2_gnrl_ctl);
414
415 /* Configure ARM at 1.2GHz */
416 clock_set_target_val(ARM_A53_CLK_ROOT, CLK_ROOT_ON |
417 CLK_ROOT_SOURCE_SEL(2));
418
419 intpll_configure(ANATOP_ARM_PLL, MHZ(1200));
420
421 /* Bypass CCM A53 ROOT, Switch to ARM PLL -> MUX-> CPU */
422 clock_set_target_val(CORE_SEL_CFG, CLK_ROOT_SOURCE_SEL(1));
423
424 if (is_imx8mn() || is_imx8mp())
425 intpll_configure(ANATOP_SYSTEM_PLL3, MHZ(600));
426 else
427 intpll_configure(ANATOP_SYSTEM_PLL3, MHZ(750));
428
429 #ifdef CONFIG_IMX8MP
430 /* 8MP ROM already set NOC to 800Mhz, only need to configure NOC_IO clk to 600Mhz */
431 /* 8MP ROM already set GIC to 400Mhz, system_pll1_800m with div = 2 */
432 clock_set_target_val(NOC_IO_CLK_ROOT, CLK_ROOT_ON | CLK_ROOT_SOURCE_SEL(2));
433 #else
434 clock_set_target_val(NOC_CLK_ROOT, CLK_ROOT_ON | CLK_ROOT_SOURCE_SEL(2));
435
436 /* config GIC to sys_pll2_100m */
437 clock_enable(CCGR_GIC, 0);
438 clock_set_target_val(GIC_CLK_ROOT, CLK_ROOT_ON |
439 CLK_ROOT_SOURCE_SEL(3));
440 clock_enable(CCGR_GIC, 1);
441 #endif
442
443 clock_set_target_val(NAND_USDHC_BUS_CLK_ROOT, CLK_ROOT_ON |
444 CLK_ROOT_SOURCE_SEL(1));
445
446 clock_enable(CCGR_DDR1, 0);
447 clock_set_target_val(DRAM_ALT_CLK_ROOT, CLK_ROOT_ON |
448 CLK_ROOT_SOURCE_SEL(1));
449 clock_set_target_val(DRAM_APB_CLK_ROOT, CLK_ROOT_ON |
450 CLK_ROOT_SOURCE_SEL(1));
451 clock_enable(CCGR_DDR1, 1);
452
453 init_wdog_clk();
454
455 clock_enable(CCGR_TEMP_SENSOR, 1);
456
457 clock_enable(CCGR_SEC_DEBUG, 1);
458
459 return 0;
460 };
461
imx_get_uartclk(void)462 u32 imx_get_uartclk(void)
463 {
464 return 24000000U;
465 }
466
decode_intpll(enum clk_root_src intpll)467 static u32 decode_intpll(enum clk_root_src intpll)
468 {
469 u32 pll_gnrl_ctl, pll_div_ctl, pll_clke_mask;
470 u32 main_div, pre_div, post_div, div;
471 u64 freq;
472
473 switch (intpll) {
474 case ARM_PLL_CLK:
475 pll_gnrl_ctl = readl(&ana_pll->arm_pll_gnrl_ctl);
476 pll_div_ctl = readl(&ana_pll->arm_pll_div_ctl);
477 break;
478 case GPU_PLL_CLK:
479 pll_gnrl_ctl = readl(&ana_pll->gpu_pll_gnrl_ctl);
480 pll_div_ctl = readl(&ana_pll->gpu_pll_div_ctl);
481 break;
482 case VPU_PLL_CLK:
483 pll_gnrl_ctl = readl(&ana_pll->vpu_pll_gnrl_ctl);
484 pll_div_ctl = readl(&ana_pll->vpu_pll_div_ctl);
485 break;
486 case SYSTEM_PLL1_800M_CLK:
487 case SYSTEM_PLL1_400M_CLK:
488 case SYSTEM_PLL1_266M_CLK:
489 case SYSTEM_PLL1_200M_CLK:
490 case SYSTEM_PLL1_160M_CLK:
491 case SYSTEM_PLL1_133M_CLK:
492 case SYSTEM_PLL1_100M_CLK:
493 case SYSTEM_PLL1_80M_CLK:
494 case SYSTEM_PLL1_40M_CLK:
495 pll_gnrl_ctl = readl(&ana_pll->sys_pll1_gnrl_ctl);
496 pll_div_ctl = readl(&ana_pll->sys_pll1_div_ctl);
497 break;
498 case SYSTEM_PLL2_1000M_CLK:
499 case SYSTEM_PLL2_500M_CLK:
500 case SYSTEM_PLL2_333M_CLK:
501 case SYSTEM_PLL2_250M_CLK:
502 case SYSTEM_PLL2_200M_CLK:
503 case SYSTEM_PLL2_166M_CLK:
504 case SYSTEM_PLL2_125M_CLK:
505 case SYSTEM_PLL2_100M_CLK:
506 case SYSTEM_PLL2_50M_CLK:
507 pll_gnrl_ctl = readl(&ana_pll->sys_pll2_gnrl_ctl);
508 pll_div_ctl = readl(&ana_pll->sys_pll2_div_ctl);
509 break;
510 case SYSTEM_PLL3_CLK:
511 pll_gnrl_ctl = readl(&ana_pll->sys_pll3_gnrl_ctl);
512 pll_div_ctl = readl(&ana_pll->sys_pll3_div_ctl);
513 break;
514 default:
515 return -EINVAL;
516 }
517
518 /* Only support SYS_XTAL 24M, PAD_CLK not take into consideration */
519 if ((pll_gnrl_ctl & INTPLL_REF_CLK_SEL_MASK) != 0)
520 return 0;
521
522 if ((pll_gnrl_ctl & INTPLL_RST_MASK) == 0)
523 return 0;
524
525 /*
526 * When BYPASS is equal to 1, PLL enters the bypass mode
527 * regardless of the values of RESETB
528 */
529 if (pll_gnrl_ctl & INTPLL_BYPASS_MASK)
530 return 24000000u;
531
532 if (!(pll_gnrl_ctl & INTPLL_LOCK_MASK)) {
533 puts("pll not locked\n");
534 return 0;
535 }
536
537 switch (intpll) {
538 case ARM_PLL_CLK:
539 case GPU_PLL_CLK:
540 case VPU_PLL_CLK:
541 case SYSTEM_PLL3_CLK:
542 case SYSTEM_PLL1_800M_CLK:
543 case SYSTEM_PLL2_1000M_CLK:
544 pll_clke_mask = INTPLL_CLKE_MASK;
545 div = 1;
546 break;
547
548 case SYSTEM_PLL1_400M_CLK:
549 case SYSTEM_PLL2_500M_CLK:
550 pll_clke_mask = INTPLL_DIV2_CLKE_MASK;
551 div = 2;
552 break;
553
554 case SYSTEM_PLL1_266M_CLK:
555 case SYSTEM_PLL2_333M_CLK:
556 pll_clke_mask = INTPLL_DIV3_CLKE_MASK;
557 div = 3;
558 break;
559
560 case SYSTEM_PLL1_200M_CLK:
561 case SYSTEM_PLL2_250M_CLK:
562 pll_clke_mask = INTPLL_DIV4_CLKE_MASK;
563 div = 4;
564 break;
565
566 case SYSTEM_PLL1_160M_CLK:
567 case SYSTEM_PLL2_200M_CLK:
568 pll_clke_mask = INTPLL_DIV5_CLKE_MASK;
569 div = 5;
570 break;
571
572 case SYSTEM_PLL1_133M_CLK:
573 case SYSTEM_PLL2_166M_CLK:
574 pll_clke_mask = INTPLL_DIV6_CLKE_MASK;
575 div = 6;
576 break;
577
578 case SYSTEM_PLL1_100M_CLK:
579 case SYSTEM_PLL2_125M_CLK:
580 pll_clke_mask = INTPLL_DIV8_CLKE_MASK;
581 div = 8;
582 break;
583
584 case SYSTEM_PLL1_80M_CLK:
585 case SYSTEM_PLL2_100M_CLK:
586 pll_clke_mask = INTPLL_DIV10_CLKE_MASK;
587 div = 10;
588 break;
589
590 case SYSTEM_PLL1_40M_CLK:
591 case SYSTEM_PLL2_50M_CLK:
592 pll_clke_mask = INTPLL_DIV20_CLKE_MASK;
593 div = 20;
594 break;
595 default:
596 return -EINVAL;
597 }
598
599 if ((pll_gnrl_ctl & pll_clke_mask) == 0)
600 return 0;
601
602 main_div = (pll_div_ctl & INTPLL_MAIN_DIV_MASK) >>
603 INTPLL_MAIN_DIV_SHIFT;
604 pre_div = (pll_div_ctl & INTPLL_PRE_DIV_MASK) >>
605 INTPLL_PRE_DIV_SHIFT;
606 post_div = (pll_div_ctl & INTPLL_POST_DIV_MASK) >>
607 INTPLL_POST_DIV_SHIFT;
608
609 /* FFVCO = (m * FFIN) / p, FFOUT = (m * FFIN) / (p * 2^s) */
610 freq = 24000000ULL * main_div;
611 return lldiv(freq, pre_div * (1 << post_div) * div);
612 }
613
decode_fracpll(enum clk_root_src frac_pll)614 static u32 decode_fracpll(enum clk_root_src frac_pll)
615 {
616 u32 pll_gnrl_ctl, pll_fdiv_ctl0, pll_fdiv_ctl1;
617 u32 main_div, pre_div, post_div, k;
618
619 switch (frac_pll) {
620 case DRAM_PLL1_CLK:
621 pll_gnrl_ctl = readl(&ana_pll->dram_pll_gnrl_ctl);
622 pll_fdiv_ctl0 = readl(&ana_pll->dram_pll_fdiv_ctl0);
623 pll_fdiv_ctl1 = readl(&ana_pll->dram_pll_fdiv_ctl1);
624 break;
625 case AUDIO_PLL1_CLK:
626 pll_gnrl_ctl = readl(&ana_pll->audio_pll1_gnrl_ctl);
627 pll_fdiv_ctl0 = readl(&ana_pll->audio_pll1_fdiv_ctl0);
628 pll_fdiv_ctl1 = readl(&ana_pll->audio_pll1_fdiv_ctl1);
629 break;
630 case AUDIO_PLL2_CLK:
631 pll_gnrl_ctl = readl(&ana_pll->audio_pll2_gnrl_ctl);
632 pll_fdiv_ctl0 = readl(&ana_pll->audio_pll2_fdiv_ctl0);
633 pll_fdiv_ctl1 = readl(&ana_pll->audio_pll2_fdiv_ctl1);
634 break;
635 case VIDEO_PLL_CLK:
636 pll_gnrl_ctl = readl(&ana_pll->video_pll1_gnrl_ctl);
637 pll_fdiv_ctl0 = readl(&ana_pll->video_pll1_fdiv_ctl0);
638 pll_fdiv_ctl1 = readl(&ana_pll->video_pll1_fdiv_ctl1);
639 break;
640 default:
641 printf("Not supported\n");
642 return 0;
643 }
644
645 /* Only support SYS_XTAL 24M, PAD_CLK not take into consideration */
646 if ((pll_gnrl_ctl & GENMASK(1, 0)) != 0)
647 return 0;
648
649 if ((pll_gnrl_ctl & RST_MASK) == 0)
650 return 0;
651 /*
652 * When BYPASS is equal to 1, PLL enters the bypass mode
653 * regardless of the values of RESETB
654 */
655 if (pll_gnrl_ctl & BYPASS_MASK)
656 return 24000000u;
657
658 if (!(pll_gnrl_ctl & LOCK_STATUS)) {
659 puts("pll not locked\n");
660 return 0;
661 }
662
663 if (!(pll_gnrl_ctl & CLKE_MASK))
664 return 0;
665
666 main_div = (pll_fdiv_ctl0 & MDIV_MASK) >>
667 MDIV_SHIFT;
668 pre_div = (pll_fdiv_ctl0 & PDIV_MASK) >>
669 PDIV_SHIFT;
670 post_div = (pll_fdiv_ctl0 & SDIV_MASK) >>
671 SDIV_SHIFT;
672
673 k = pll_fdiv_ctl1 & KDIV_MASK;
674
675 return lldiv((main_div * 65536 + k) * 24000000ULL,
676 65536 * pre_div * (1 << post_div));
677 }
678
get_root_src_clk(enum clk_root_src root_src)679 static u32 get_root_src_clk(enum clk_root_src root_src)
680 {
681 switch (root_src) {
682 case OSC_24M_CLK:
683 return 24000000u;
684 case OSC_HDMI_CLK:
685 return 26000000u;
686 case OSC_32K_CLK:
687 return 32000u;
688 case ARM_PLL_CLK:
689 case GPU_PLL_CLK:
690 case VPU_PLL_CLK:
691 case SYSTEM_PLL1_800M_CLK:
692 case SYSTEM_PLL1_400M_CLK:
693 case SYSTEM_PLL1_266M_CLK:
694 case SYSTEM_PLL1_200M_CLK:
695 case SYSTEM_PLL1_160M_CLK:
696 case SYSTEM_PLL1_133M_CLK:
697 case SYSTEM_PLL1_100M_CLK:
698 case SYSTEM_PLL1_80M_CLK:
699 case SYSTEM_PLL1_40M_CLK:
700 case SYSTEM_PLL2_1000M_CLK:
701 case SYSTEM_PLL2_500M_CLK:
702 case SYSTEM_PLL2_333M_CLK:
703 case SYSTEM_PLL2_250M_CLK:
704 case SYSTEM_PLL2_200M_CLK:
705 case SYSTEM_PLL2_166M_CLK:
706 case SYSTEM_PLL2_125M_CLK:
707 case SYSTEM_PLL2_100M_CLK:
708 case SYSTEM_PLL2_50M_CLK:
709 case SYSTEM_PLL3_CLK:
710 return decode_intpll(root_src);
711 case DRAM_PLL1_CLK:
712 case AUDIO_PLL1_CLK:
713 case AUDIO_PLL2_CLK:
714 case VIDEO_PLL_CLK:
715 return decode_fracpll(root_src);
716 case ARM_A53_ALT_CLK:
717 return get_root_clk(ARM_A53_CLK_ROOT);
718 default:
719 return 0;
720 }
721
722 return 0;
723 }
724
get_root_clk(enum clk_root_index clock_id)725 static u32 get_root_clk(enum clk_root_index clock_id)
726 {
727 enum clk_root_src root_src;
728 u32 post_podf, pre_podf, root_src_clk;
729
730 if (clock_root_enabled(clock_id) <= 0)
731 return 0;
732
733 if (clock_get_prediv(clock_id, &pre_podf) < 0)
734 return 0;
735
736 if (clock_get_postdiv(clock_id, &post_podf) < 0)
737 return 0;
738
739 if (clock_get_src(clock_id, &root_src) < 0)
740 return 0;
741
742 root_src_clk = get_root_src_clk(root_src);
743
744 return root_src_clk / (post_podf + 1) / (pre_podf + 1);
745 }
746
get_arm_core_clk(void)747 u32 get_arm_core_clk(void)
748 {
749 enum clk_root_src root_src;
750 u32 root_src_clk;
751
752 if (clock_get_src(CORE_SEL_CFG, &root_src) < 0)
753 return 0;
754
755 root_src_clk = get_root_src_clk(root_src);
756
757 return root_src_clk;
758 }
759
mxc_get_clock(enum mxc_clock clk)760 u32 mxc_get_clock(enum mxc_clock clk)
761 {
762 u32 val;
763
764 switch (clk) {
765 case MXC_ARM_CLK:
766 return get_arm_core_clk();
767 case MXC_IPG_CLK:
768 clock_get_target_val(IPG_CLK_ROOT, &val);
769 val = val & 0x3;
770 return get_root_clk(AHB_CLK_ROOT) / 2 / (val + 1);
771 case MXC_CSPI_CLK:
772 return get_root_clk(ECSPI1_CLK_ROOT);
773 case MXC_ESDHC_CLK:
774 return get_root_clk(USDHC1_CLK_ROOT);
775 case MXC_ESDHC2_CLK:
776 return get_root_clk(USDHC2_CLK_ROOT);
777 case MXC_ESDHC3_CLK:
778 return get_root_clk(USDHC3_CLK_ROOT);
779 case MXC_I2C_CLK:
780 return get_root_clk(I2C1_CLK_ROOT);
781 case MXC_UART_CLK:
782 return get_root_clk(UART1_CLK_ROOT);
783 case MXC_QSPI_CLK:
784 return get_root_clk(QSPI_CLK_ROOT);
785 default:
786 printf("Unsupported mxc_clock %d\n", clk);
787 break;
788 }
789
790 return 0;
791 }
792
793 #ifdef CONFIG_DWC_ETH_QOS
set_clk_eqos(enum enet_freq type)794 int set_clk_eqos(enum enet_freq type)
795 {
796 u32 target;
797 u32 enet1_ref;
798
799 switch (type) {
800 case ENET_125MHZ:
801 enet1_ref = ENET1_REF_CLK_ROOT_FROM_PLL_ENET_MAIN_125M_CLK;
802 break;
803 case ENET_50MHZ:
804 enet1_ref = ENET1_REF_CLK_ROOT_FROM_PLL_ENET_MAIN_50M_CLK;
805 break;
806 case ENET_25MHZ:
807 enet1_ref = ENET1_REF_CLK_ROOT_FROM_PLL_ENET_MAIN_25M_CLK;
808 break;
809 default:
810 return -EINVAL;
811 }
812
813 /* disable the clock first */
814 clock_enable(CCGR_QOS_ETHENET, 0);
815 clock_enable(CCGR_SDMA2, 0);
816
817 /* set enet axi clock 266Mhz */
818 target = CLK_ROOT_ON | ENET_AXI_CLK_ROOT_FROM_SYS1_PLL_266M |
819 CLK_ROOT_PRE_DIV(CLK_ROOT_PRE_DIV1) |
820 CLK_ROOT_POST_DIV(CLK_ROOT_POST_DIV1);
821 clock_set_target_val(ENET_AXI_CLK_ROOT, target);
822
823 target = CLK_ROOT_ON | enet1_ref |
824 CLK_ROOT_PRE_DIV(CLK_ROOT_PRE_DIV1) |
825 CLK_ROOT_POST_DIV(CLK_ROOT_POST_DIV1);
826 clock_set_target_val(ENET_QOS_CLK_ROOT, target);
827
828 target = CLK_ROOT_ON |
829 ENET1_TIME_CLK_ROOT_FROM_PLL_ENET_MAIN_100M_CLK |
830 CLK_ROOT_PRE_DIV(CLK_ROOT_PRE_DIV1) |
831 CLK_ROOT_POST_DIV(CLK_ROOT_POST_DIV4);
832 clock_set_target_val(ENET_QOS_TIMER_CLK_ROOT, target);
833
834 /* enable clock */
835 clock_enable(CCGR_QOS_ETHENET, 1);
836 clock_enable(CCGR_SDMA2, 1);
837
838 return 0;
839 }
840
imx_eqos_txclk_set_rate(u32 rate)841 int imx_eqos_txclk_set_rate(u32 rate)
842 {
843 u32 val;
844 u32 eqos_post_div;
845
846 /* disable the clock first */
847 clock_enable(CCGR_QOS_ETHENET, 0);
848 clock_enable(CCGR_SDMA2, 0);
849
850 switch (rate) {
851 case 125000000:
852 eqos_post_div = 1;
853 break;
854 case 25000000:
855 eqos_post_div = 125000000 / 25000000;
856 break;
857 case 2500000:
858 eqos_post_div = 125000000 / 2500000;
859 break;
860 default:
861 return -EINVAL;
862 }
863
864 clock_get_target_val(ENET_QOS_CLK_ROOT, &val);
865 val &= ~(CLK_ROOT_PRE_DIV_MASK | CLK_ROOT_POST_DIV_MASK);
866 val |= CLK_ROOT_PRE_DIV(CLK_ROOT_PRE_DIV1) |
867 CLK_ROOT_POST_DIV(eqos_post_div - 1);
868 clock_set_target_val(ENET_QOS_CLK_ROOT, val);
869
870 /* enable clock */
871 clock_enable(CCGR_QOS_ETHENET, 1);
872 clock_enable(CCGR_SDMA2, 1);
873
874 return 0;
875 }
876
imx_get_eqos_csr_clk(void)877 u32 imx_get_eqos_csr_clk(void)
878 {
879 return get_root_clk(ENET_AXI_CLK_ROOT);
880 }
881 #endif
882
883 #ifdef CONFIG_FEC_MXC
set_clk_enet(enum enet_freq type)884 int set_clk_enet(enum enet_freq type)
885 {
886 u32 target;
887 u32 enet1_ref;
888
889 switch (type) {
890 case ENET_125MHZ:
891 enet1_ref = ENET1_REF_CLK_ROOT_FROM_PLL_ENET_MAIN_125M_CLK;
892 break;
893 case ENET_50MHZ:
894 enet1_ref = ENET1_REF_CLK_ROOT_FROM_PLL_ENET_MAIN_50M_CLK;
895 break;
896 case ENET_25MHZ:
897 enet1_ref = ENET1_REF_CLK_ROOT_FROM_PLL_ENET_MAIN_25M_CLK;
898 break;
899 default:
900 return -EINVAL;
901 }
902
903 /* disable the clock first */
904 clock_enable(CCGR_ENET1, 0);
905 clock_enable(CCGR_SIM_ENET, 0);
906
907 /* set enet axi clock 266Mhz */
908 target = CLK_ROOT_ON | ENET_AXI_CLK_ROOT_FROM_SYS1_PLL_266M |
909 CLK_ROOT_PRE_DIV(CLK_ROOT_PRE_DIV1) |
910 CLK_ROOT_POST_DIV(CLK_ROOT_POST_DIV1);
911 clock_set_target_val(ENET_AXI_CLK_ROOT, target);
912
913 target = CLK_ROOT_ON | enet1_ref |
914 CLK_ROOT_PRE_DIV(CLK_ROOT_PRE_DIV1) |
915 CLK_ROOT_POST_DIV(CLK_ROOT_POST_DIV1);
916 clock_set_target_val(ENET_REF_CLK_ROOT, target);
917
918 target = CLK_ROOT_ON |
919 ENET1_TIME_CLK_ROOT_FROM_PLL_ENET_MAIN_100M_CLK |
920 CLK_ROOT_PRE_DIV(CLK_ROOT_PRE_DIV1) |
921 CLK_ROOT_POST_DIV(CLK_ROOT_POST_DIV4);
922 clock_set_target_val(ENET_TIMER_CLK_ROOT, target);
923
924 /* enable clock */
925 clock_enable(CCGR_SIM_ENET, 1);
926 clock_enable(CCGR_ENET1, 1);
927
928 return 0;
929 }
930 #endif
931