1 // SPDX-License-Identifier: GPL-2.0+
2 /*
3 * (C) Copyright 2007
4 * Sascha Hauer, Pengutronix
5 *
6 * (C) Copyright 2009 Freescale Semiconductor, Inc.
7 */
8
9 #include <common.h>
10 #include <cpu_func.h>
11 #include <asm/arch/imx-regs.h>
12 #include <asm/arch/clock.h>
13 #include <asm/arch/sys_proto.h>
14 #include <asm/cache.h>
15
16 #include <linux/errno.h>
17 #include <asm/io.h>
18 #include <asm/mach-imx/boot_mode.h>
19
20 #if !(defined(CONFIG_MX51) || defined(CONFIG_MX53))
21 #error "CPU_TYPE not defined"
22 #endif
23
get_cpu_rev(void)24 u32 get_cpu_rev(void)
25 {
26 #ifdef CONFIG_MX51
27 int system_rev = 0x51000;
28 #else
29 int system_rev = 0x53000;
30 #endif
31 int reg = __raw_readl(ROM_SI_REV);
32
33 #if defined(CONFIG_MX51)
34 switch (reg) {
35 case 0x02:
36 system_rev |= CHIP_REV_1_1;
37 break;
38 case 0x10:
39 if ((__raw_readl(GPIO1_BASE_ADDR + 0x0) & (0x1 << 22)) == 0)
40 system_rev |= CHIP_REV_2_5;
41 else
42 system_rev |= CHIP_REV_2_0;
43 break;
44 case 0x20:
45 system_rev |= CHIP_REV_3_0;
46 break;
47 default:
48 system_rev |= CHIP_REV_1_0;
49 break;
50 }
51 #else
52 if (reg < 0x20)
53 system_rev |= CHIP_REV_1_0;
54 else
55 system_rev |= reg;
56 #endif
57 return system_rev;
58 }
59
60 #ifdef CONFIG_REVISION_TAG
get_board_rev(void)61 u32 __weak get_board_rev(void)
62 {
63 return get_cpu_rev();
64 }
65 #endif
66
67 #if !CONFIG_IS_ENABLED(SYS_DCACHE_OFF)
enable_caches(void)68 void enable_caches(void)
69 {
70 /* Enable D-cache. I-cache is already enabled in start.S */
71 dcache_enable();
72 }
73 #endif
74
75 #if defined(CONFIG_FEC_MXC)
imx_get_mac_from_fuse(int dev_id,unsigned char * mac)76 void imx_get_mac_from_fuse(int dev_id, unsigned char *mac)
77 {
78 int i;
79 struct iim_regs *iim = (struct iim_regs *)IMX_IIM_BASE;
80 struct fuse_bank *bank = &iim->bank[1];
81 struct fuse_bank1_regs *fuse =
82 (struct fuse_bank1_regs *)bank->fuse_regs;
83
84 for (i = 0; i < 6; i++)
85 mac[i] = readl(&fuse->mac_addr[i]) & 0xff;
86 }
87 #endif
88
89 #ifdef CONFIG_MX53
90 #define IMX53_SRTC_LPGR_PERSIST_SECONDARY_BOOT BIT(30)
91
boot_mode_apply(unsigned cfg_val)92 void boot_mode_apply(unsigned cfg_val)
93 {
94 void *lpgr = &((struct srtc_regs *)SRTC_BASE_ADDR)->lpgr;
95
96 if (cfg_val == MAKE_CFGVAL_PRIMARY_BOOT)
97 clrbits_le32(lpgr, IMX53_SRTC_LPGR_PERSIST_SECONDARY_BOOT);
98 else if (cfg_val == MAKE_CFGVAL_SECONDARY_BOOT)
99 setbits_le32(lpgr, IMX53_SRTC_LPGR_PERSIST_SECONDARY_BOOT);
100 else
101 writel(cfg_val, lpgr);
102 }
103
boot_mode_getprisec(void)104 int boot_mode_getprisec(void)
105 {
106 void *lpgr = &((struct srtc_regs *)SRTC_BASE_ADDR)->lpgr;
107
108 return !!(readl(lpgr) & IMX53_SRTC_LPGR_PERSIST_SECONDARY_BOOT);
109 }
110
111 /*
112 * cfg_val will be used for
113 * Boot_cfg3[7:0]:Boot_cfg2[7:0]:Boot_cfg1[7:0]
114 *
115 * If bit 28 of LPGR is set upon watchdog reset,
116 * bits[25:0] of LPGR will move to SBMR.
117 */
118 const struct boot_mode soc_boot_modes[] = {
119 {"normal", MAKE_CFGVAL(0x00, 0x00, 0x00, 0x00)},
120 /* usb or serial download */
121 {"usb", MAKE_CFGVAL(0x00, 0x00, 0x00, 0x13)},
122 {"sata", MAKE_CFGVAL(0x28, 0x00, 0x00, 0x12)},
123 {"escpi1:0", MAKE_CFGVAL(0x38, 0x20, 0x00, 0x12)},
124 {"escpi1:1", MAKE_CFGVAL(0x38, 0x20, 0x04, 0x12)},
125 {"escpi1:2", MAKE_CFGVAL(0x38, 0x20, 0x08, 0x12)},
126 {"escpi1:3", MAKE_CFGVAL(0x38, 0x20, 0x0c, 0x12)},
127 /* 4 bit bus width */
128 {"esdhc1", MAKE_CFGVAL(0x40, 0x20, 0x00, 0x12)},
129 {"esdhc2", MAKE_CFGVAL(0x40, 0x20, 0x08, 0x12)},
130 {"esdhc3", MAKE_CFGVAL(0x40, 0x20, 0x10, 0x12)},
131 {"esdhc4", MAKE_CFGVAL(0x40, 0x20, 0x18, 0x12)},
132 {"primary", MAKE_CFGVAL_PRIMARY_BOOT},
133 {"secondary", MAKE_CFGVAL_SECONDARY_BOOT},
134 {NULL, 0},
135 };
136 #endif
137